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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents 3de3d5e778f2
children
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1 //==========================================================================
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2 //
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3 // var_misc.c
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4 //
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5 // HAL CPU variant miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): nickg
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44 // Contributors: nickg, jlarmour, dmoseley
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45 // Date: 1999-01-21
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46 // Purpose: HAL miscellaneous functions
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47 // Description: This file contains miscellaneous functions provided by the
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48 // HAL.
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49 //
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50 //####DESCRIPTIONEND####
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51 //
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52 //========================================================================*/
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/infra/cyg_type.h> // Base types
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57 #include <cyg/infra/cyg_trac.h> // tracing macros
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58 #include <cyg/infra/cyg_ass.h> // assertion macros
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59
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60 #include <cyg/hal/hal_cache.h>
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61
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62 #include <cyg/hal/hal_intr.h> // HAL_CLOCK_READ
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63 #include CYGHWR_MEMORY_LAYOUT_H
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64
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65 /*------------------------------------------------------------------------*/
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66 /* Variant specific initialization routine. */
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67
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68 void hal_variant_init(void)
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69 {
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70 // Let the timer run at a default rate (for delays)
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71 HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
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72 }
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73
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74 /*------------------------------------------------------------------------*/
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75 /* Cache functions. */
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76
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77 #if 0 //!defined(CYG_HAL_MN10300_SIM)
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78 void cyg_hal_dcache_store(CYG_ADDRWORD base, int size)
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79 {
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80 volatile register CYG_BYTE *way0 = HAL_DCACHE_PURGE_WAY0;
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81 volatile register CYG_BYTE *way1 = HAL_DCACHE_PURGE_WAY1;
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82 volatile register CYG_BYTE *way2 = HAL_DCACHE_PURGE_WAY2;
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83 volatile register CYG_BYTE *way3 = HAL_DCACHE_PURGE_WAY3;
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84 register int i;
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85 register CYG_ADDRWORD state;
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86
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87 HAL_DCACHE_IS_ENABLED(state);
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88 if (state)
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89 HAL_DCACHE_DISABLE();
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90
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91 way0 += base & 0x000003f0;
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92 way1 += base & 0x000003f0;
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93 way2 += base & 0x000003f0;
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94 way3 += base & 0x000003f0;
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95 for( i = 0; i < size; i += HAL_DCACHE_LINE_SIZE )
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96 {
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97 *(CYG_ADDRWORD *)way0 = 0;
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98 *(CYG_ADDRWORD *)way1 = 0;
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99 *(CYG_ADDRWORD *)way2 = 0;
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100 *(CYG_ADDRWORD *)way3 = 0;
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101 way0 += HAL_DCACHE_LINE_SIZE;
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102 way1 += HAL_DCACHE_LINE_SIZE;
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103 way2 += HAL_DCACHE_LINE_SIZE;
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104 way3 += HAL_DCACHE_LINE_SIZE;
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105 }
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106 if (state)
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107 HAL_DCACHE_ENABLE();
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108 }
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109 #endif
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110
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111 /*------------------------------------------------------------------------*/
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112 /* Clock functions. */
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113
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114 cyg_uint32 __hal_period__;
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115
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116 // Delay for some usecs.
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117 void
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118 hal_delay_us(cyg_int32 delay)
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119 {
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120 #define _TICKS_PER_USEC (CYGHWR_HAL_MN10300_PROCESSOR_OSC/1000000)
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121 cyg_uint32 now, prev, diff, usecs;
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122
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123 diff = usecs = 0;
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124 HAL_CLOCK_READ(&prev);
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125
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126 while (delay > usecs) {
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127 HAL_CLOCK_READ(&now);
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128
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129 if (now < prev)
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130 diff += (now + (__hal_period__ - prev));
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131 else
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132 diff += (now - prev);
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133
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134 prev = now;
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135
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136 if (diff >= _TICKS_PER_USEC) {
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137 usecs += (diff / _TICKS_PER_USEC);
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138 diff %= _TICKS_PER_USEC;
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139 }
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140 }
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141 }
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142
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143
453
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144 /*------------------------------------------------------------------------*/
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145 /* Memory top support */
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146
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147 #define SDBASE0 ((volatile unsigned *)0xDA000008)
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148 #define SDBASE1 ((volatile unsigned *)0xDA00000C)
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149 #define SDRAMBUS ((volatile unsigned *)0xDA000000)
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150
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151 #if CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP
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152 externC cyg_uint8 *
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153 hal_mn10300_mem_real_region_top( cyg_uint8 *regionend )
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154 {
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155 unsigned dram_size, dram_base;
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156
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157 // Figure out actual DRAM size from memory controller config.
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158 dram_size = 0x400000 << ((*SDRAMBUS >> 16) & 0x3);
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159 if (*SDBASE1 & 1)
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160 dram_size *= 2;
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161 dram_base = (*SDBASE0 & ((*SDBASE0 & 0xfff0) << 16));
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162
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163 CYG_ASSERT( dram_size >= 8<<20, "Less than 8MB SDRAM reported!" );
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164 CYG_ASSERT( dram_size <= 256<<20, "More than 256MB SDRAM reported!" );
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165
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166 // is it the "normal" end of the DRAM region? If so, it should be
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167 // replaced by the real size
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168 if ( regionend ==
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169 ((cyg_uint8 *)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) ) {
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170 regionend = (cyg_uint8 *)dram_base + dram_size;
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171 }
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172 return regionend;
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173 }
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174 #endif
421
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175
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176
115
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177 #ifdef CYGPKG_CYGMON
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178 /*------------------------------------------------------------------------*/
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179 /* GDB Register functions. */
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180 #include <cyg/hal/var_arch.h>
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181 #include <cyg/hal/hal_stub.h>
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182
208
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183 #if CYGHWR_HAL_MN10300_AM33_REVISION == 2
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184 int fpu_regs_read = 0;
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185 #endif
115
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186
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187 int msp_read = 0;
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188
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189 extern int *_registers_valid;
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190
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191 void am33_get_gdb_extra_registers(CYG_ADDRWORD *registers, HAL_SavedRegisters *regs)
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192 {
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193 register CYG_ADDRWORD epsw;
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194 asm volatile (" mov epsw, %0 " : "=r" (epsw) : );
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195
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196 registers[15] = regs->e0;
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197 registers[16] = regs->e1;
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198 registers[17] = regs->e2;
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199 registers[18] = regs->e3;
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200 registers[19] = regs->e4;
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201 registers[20] = regs->e5;
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202 registers[21] = regs->e6;
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203 registers[22] = regs->e7;
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204
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205 registers[26] = regs->mcrh;
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206 registers[27] = regs->mcrl;
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207 registers[28] = regs->mcvf;
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208
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209 registers[14] = regs->mdrq;
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210
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211 {
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212 register CYG_ADDRWORD ssp, usp, msp;
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213 asm volatile (" mov usp, %0 " : "=a" (usp) : );
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214 asm volatile (" mov ssp, %0 " : "=a" (ssp) : );
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215 if ((epsw & HAL_ARCH_AM33_PSW_ML) == HAL_ARCH_AM33_PSW_ML)
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216 {
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217 // We are running in Monitor mode. Go ahead and read the MSP.
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218 asm volatile (" mov msp, %0 " : "=a" (msp) : );
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219 msp_read = 1;
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220 } else {
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221 msp = 0;
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222 msp_read = 0;
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223 }
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224
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225 // Now we need to determine which sp was in effect when we hit this exception,
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226 // since we want the register image to reflect the state at the time of the
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227 // exception.
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228 if ((regs->psw & HAL_ARCH_AM33_PSW_ML) == HAL_ARCH_AM33_PSW_ML)
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229 {
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230 msp = regs->sp;
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231 }
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232 else if ((regs->psw & HAL_ARCH_AM33_PSW_nSL) == 0)
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233 {
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234 ssp = regs->sp;
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235 }
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236 else
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237 {
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238 usp = regs->sp;
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239 }
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240
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241 registers[23] = ssp;
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242 registers[24] = msp;
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243 registers[25] = usp;
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244 }
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245
208
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246 #if CYGHWR_HAL_MN10300_AM33_REVISION == 2
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247 if ((regs->psw & HAL_ARCH_AM33_PSW_FE) == HAL_ARCH_AM33_PSW_FE)
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248 {
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249 // The FPU is enabled. Go ahead and read the registers
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250 asm volatile (" fmov fpcr, %0 " : "=d" (registers[29]) : );
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251 asm volatile (" fmov fs0, %0 " : "=m" (registers[32]) : );
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252 asm volatile (" fmov fs1, %0 " : "=m" (registers[33]) : );
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253 asm volatile (" fmov fs2, %0 " : "=m" (registers[34]) : );
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254 asm volatile (" fmov fs3, %0 " : "=m" (registers[35]) : );
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255 asm volatile (" fmov fs4, %0 " : "=m" (registers[36]) : );
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256 asm volatile (" fmov fs5, %0 " : "=m" (registers[37]) : );
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257 asm volatile (" fmov fs6, %0 " : "=m" (registers[38]) : );
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258 asm volatile (" fmov fs7, %0 " : "=m" (registers[39]) : );
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259 asm volatile (" fmov fs8, %0 " : "=m" (registers[40]) : );
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260 asm volatile (" fmov fs9, %0 " : "=m" (registers[41]) : );
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261 asm volatile (" fmov fs10, %0 " : "=m" (registers[42]) : );
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262 asm volatile (" fmov fs11, %0 " : "=m" (registers[43]) : );
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263 asm volatile (" fmov fs12, %0 " : "=m" (registers[44]) : );
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264 asm volatile (" fmov fs13, %0 " : "=m" (registers[45]) : );
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265 asm volatile (" fmov fs14, %0 " : "=m" (registers[46]) : );
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266 asm volatile (" fmov fs15, %0 " : "=m" (registers[47]) : );
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267 asm volatile (" fmov fs16, %0 " : "=m" (registers[48]) : );
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268 asm volatile (" fmov fs17, %0 " : "=m" (registers[49]) : );
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269 asm volatile (" fmov fs18, %0 " : "=m" (registers[50]) : );
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270 asm volatile (" fmov fs19, %0 " : "=m" (registers[51]) : );
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271 asm volatile (" fmov fs20, %0 " : "=m" (registers[52]) : );
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272 asm volatile (" fmov fs21, %0 " : "=m" (registers[53]) : );
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273 asm volatile (" fmov fs22, %0 " : "=m" (registers[54]) : );
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274 asm volatile (" fmov fs23, %0 " : "=m" (registers[55]) : );
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275 asm volatile (" fmov fs24, %0 " : "=m" (registers[56]) : );
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276 asm volatile (" fmov fs25, %0 " : "=m" (registers[57]) : );
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277 asm volatile (" fmov fs26, %0 " : "=m" (registers[58]) : );
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278 asm volatile (" fmov fs27, %0 " : "=m" (registers[59]) : );
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279 asm volatile (" fmov fs28, %0 " : "=m" (registers[60]) : );
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280 asm volatile (" fmov fs29, %0 " : "=m" (registers[61]) : );
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281 asm volatile (" fmov fs30, %0 " : "=m" (registers[62]) : );
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282 asm volatile (" fmov fs31, %0 " : "=m" (registers[63]) : );
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283 fpu_regs_read = 1;
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284 } else {
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285 fpu_regs_read = 0;
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286 }
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287 #endif
115
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288
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289 #ifdef CYGHWR_REGISTER_VALIDITY_CHECKING
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290 {
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291 int i;
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292
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293 // Initially set all registers to valid
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294 for (i = 0; i < NUMREGS; i++)
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295 _registers_valid[i] = 1;
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296
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297 if (msp_read == 0)
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298 _registers_valid[MSP] = 0;
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299
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300 if (fpu_regs_read == 0)
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301 {
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302 for (i = FP_START; i <= FP_END; i++)
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303 _registers_valid[i] = 0;
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304 }
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305 }
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306 #endif
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307 }
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308
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309 void am33_set_gdb_extra_registers(CYG_ADDRWORD *registers, HAL_SavedRegisters *regs)
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310 {
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311 regs->e0 = registers[15];
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312 regs->e1 = registers[16];
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313 regs->e2 = registers[17];
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314 regs->e3 = registers[18];
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315 regs->e4 = registers[19];
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316 regs->e5 = registers[20];
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317 regs->e6 = registers[21];
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318 regs->e7 = registers[22];
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319
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320 regs->mcrh = registers[26];
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321 regs->mcrl = registers[27];
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322 regs->mcvf = registers[28];
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323
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324 regs->mdrq = registers[14];
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325
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326 {
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327 register CYG_ADDRWORD ssp, usp, msp;
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328 ssp = registers[23];
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329 msp = registers[24];
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330 usp = registers[25];
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331 if ((registers[11] & HAL_ARCH_AM33_PSW_ML) == HAL_ARCH_AM33_PSW_ML)
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332 {
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333 // We were running in monitor mode.
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334 // Go ahead and manually restore ssp and usp.
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335 // msp will be restored by the rti.
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336 asm volatile (" mov %0, usp " : : "a" (usp));
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337 asm volatile (" mov %0, ssp " : : "a" (ssp));
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338 }
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339 else if ((registers[11] & HAL_ARCH_AM33_PSW_nSL) == 0)
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340 {
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341 // We were running in system mode.
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342 // Go ahead and manually restore msp and usp.
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343 // ssp will be restored by the rti.
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344 asm volatile (" mov %0, usp " : : "a" (usp));
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345 if (msp_read)
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346 {
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347 asm volatile (" mov %0, msp " : : "a" (msp));
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348 }
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349 }
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350 else
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351 {
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352 // We were running in user mode.
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353 // Go ahead and manually restore msp and ssp.
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354 // usp will be restored by the rti.
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355 asm volatile (" mov %0, ssp " : : "a" (ssp));
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356 if (msp_read)
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357 {
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358 asm volatile (" mov %0, msp " : : "a" (msp));
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359 }
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360 }
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361 }
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362
208
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363 #if CYGHWR_HAL_MN10300_AM33_REVISION == 2
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364 if (fpu_regs_read)
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365 {
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366 // The FPU registers have been read and the FPU is enabled.
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367 // Go ahead and write the registers
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368 asm volatile (" fmov %0, fpcr " : : "d" (registers[29]) );
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369 asm volatile (" fmov %0, fs0 " : : "m" (registers[32]) );
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370 asm volatile (" fmov %0, fs1 " : : "m" (registers[33]) );
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371 asm volatile (" fmov %0, fs2 " : : "m" (registers[34]) );
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372 asm volatile (" fmov %0, fs3 " : : "m" (registers[35]) );
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373 asm volatile (" fmov %0, fs4 " : : "m" (registers[36]) );
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374 asm volatile (" fmov %0, fs5 " : : "m" (registers[37]) );
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375 asm volatile (" fmov %0, fs6 " : : "m" (registers[38]) );
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376 asm volatile (" fmov %0, fs7 " : : "m" (registers[39]) );
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377 asm volatile (" fmov %0, fs8 " : : "m" (registers[40]) );
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378 asm volatile (" fmov %0, fs9 " : : "m" (registers[41]) );
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379 asm volatile (" fmov %0, fs10 " : : "m" (registers[42]) );
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380 asm volatile (" fmov %0, fs11 " : : "m" (registers[43]) );
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381 asm volatile (" fmov %0, fs12 " : : "m" (registers[44]) );
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382 asm volatile (" fmov %0, fs13 " : : "m" (registers[45]) );
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383 asm volatile (" fmov %0, fs14 " : : "m" (registers[46]) );
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384 asm volatile (" fmov %0, fs15 " : : "m" (registers[47]) );
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385 asm volatile (" fmov %0, fs16 " : : "m" (registers[48]) );
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386 asm volatile (" fmov %0, fs17 " : : "m" (registers[49]) );
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387 asm volatile (" fmov %0, fs18 " : : "m" (registers[50]) );
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388 asm volatile (" fmov %0, fs19 " : : "m" (registers[51]) );
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389 asm volatile (" fmov %0, fs20 " : : "m" (registers[52]) );
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390 asm volatile (" fmov %0, fs21 " : : "m" (registers[53]) );
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391 asm volatile (" fmov %0, fs22 " : : "m" (registers[54]) );
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392 asm volatile (" fmov %0, fs23 " : : "m" (registers[55]) );
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393 asm volatile (" fmov %0, fs24 " : : "m" (registers[56]) );
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394 asm volatile (" fmov %0, fs25 " : : "m" (registers[57]) );
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395 asm volatile (" fmov %0, fs26 " : : "m" (registers[58]) );
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396 asm volatile (" fmov %0, fs27 " : : "m" (registers[59]) );
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397 asm volatile (" fmov %0, fs28 " : : "m" (registers[60]) );
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398 asm volatile (" fmov %0, fs29 " : : "m" (registers[61]) );
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399 asm volatile (" fmov %0, fs30 " : : "m" (registers[62]) );
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400 asm volatile (" fmov %0, fs31 " : : "m" (registers[63]) );
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401 }
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402 #endif
115
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403 }
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404 #endif // CYGPKG_CYGMON
76
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
405
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
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406 /*------------------------------------------------------------------------*/
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
jlarmour
parents:
diff changeset
407 /* End of var_misc.c */