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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents d2c90368aeef
children
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1 ##=============================================================================
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2 ##
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3 ## cogent.S
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4 ##
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5 ## Cogent board hardware setup
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6 ##
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7 ##=============================================================================
208
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8 #####ECOSGPLCOPYRIGHTBEGIN####
210
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later version.
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16 ##
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17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 ## for more details.
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21 ##
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22 ## You should have received a copy of the GNU General Public License along
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23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
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24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 ##
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26 ## As a special exception, if other files instantiate templates or use macros
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27 ## or inline functions from this file, or you compile this file and link it
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28 ## with other works to produce a work based on this file, this file does not
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29 ## by itself cause the resulting work to be covered by the GNU General Public
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30 ## License. However the source code for this file must still be made available
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31 ## in accordance with section (3) of the GNU General Public License.
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32 ##
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33 ## This exception does not invalidate any other reasons why a work based on
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34 ## this file might be covered by the GNU General Public License.
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35 ##
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36 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 ## at http://sources.redhat.com/ecos/ecos-license/
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38 ## -------------------------------------------
208
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39 #####ECOSGPLCOPYRIGHTEND####
0
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40 ##=============================================================================
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41 #######DESCRIPTIONBEGIN####
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42 ##
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43 ## Author(s): nickg
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44 ## Contributors: nickg
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45 ## Date: 1997-11-11
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46 ## Purpose: Cogent board hardware setup
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47 ## Description: This file contains any code needed to initialize the
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48 ## hardware on a Cogent PowerPC board.
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49 ##
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50 ######DESCRIPTIONEND####
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51 ##
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52 ##=============================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/hal/ppc_regs.h>
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57 #include <cyg/hal/arch.inc>
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58
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59 #------------------------------------------------------------------------------
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60
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61 .globl hal_hardware_init
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62 hal_hardware_init:
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63
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64 #if defined(CYGPKG_HAL_POWERPC_COGENT) && defined(CYGPKG_HAL_POWERPC_MPC8xx)
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65
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66 # Set up MPC8xx mapping registers for cogent
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67
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68 lwi r3,CYGARC_REG_IMM_BASE # base address of control registers
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69 mtspr CYGARC_REG_IMMR,r3
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70
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71 # Set timebase divisor to busclock/16, pitrtc divisor to 512.
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72 lwz r4,(CYGARC_REG_IMM_SCCR - CYGARC_REG_IMM_BASE)(r3)
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73 lwi r5,(CYGARC_REG_IMM_SCCR_RTDIV | CYGARC_REG_IMM_SCCR_RTSEL | CYGARC_REG_IMM_SCCR_TBS)
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74 or r4,r4,r5
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75 stw r4,(CYGARC_REG_IMM_SCCR - CYGARC_REG_IMM_BASE)(r3)
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76
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77 # Enable TimeBase
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78 li r4,CYGARC_REG_IMM_TBSCR_TBE
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79 sth r4,(CYGARC_REG_IMM_TBSCR - CYGARC_REG_IMM_BASE)(r3)
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80
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81 # Note: I do not know if the timeout is correct/optimal.
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82 # Works with the above memory mappings/wait states and
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83 # the PromICE.
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84 # Disable watchdog, enable bus monitor, timeout after 255*8 cycles
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85 lwi r4,(CYGARC_REG_IMM_SYPCR_BMT_MASK | CYGARC_REG_IMM_SYPCR_BME)
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86 stw r4,(CYGARC_REG_IMM_SYPCR - CYGARC_REG_IMM_BASE)(r3)
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87
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88 # Set CS0 to
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89 # base addr 0xfff00000
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90 # wait states 4
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91 # size 1M
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92 # Covers ROM
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93 # Note: After a reset code is currently executing via the default
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94 # mapping defined in bank 0. This bank must remain valid while
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95 # it is being configured.
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96 lwi r4,(0xfff00000 | CYGARC_REG_IMM_BR_PS_16 | CYGARC_REG_IMM_BR_V)
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97 stw r4,(CYGARC_REG_IMM_BR0 - CYGARC_REG_IMM_BASE)(r3)
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98 lwi r4,(0xfff00000 | CYGARC_REG_IMM_OR_BI | 4 << CYGARC_REG_IMM_OR_SCY_SHIFT)
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99 stw r4,(CYGARC_REG_IMM_OR0 - CYGARC_REG_IMM_BASE)(r3)
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100
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101 # Set CS1 to
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102 # base addr 0x00000000
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103 # external ACK
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104 # size 64M
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105 # Covers DRAM and slot0
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106 lwi r4,(0xfc000000 | CYGARC_REG_IMM_OR_SETA)
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107 stw r4,(CYGARC_REG_IMM_OR1 - CYGARC_REG_IMM_BASE)(r3)
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108 lwi r4,(0x00000000 | CYGARC_REG_IMM_BR_PS_32 | CYGARC_REG_IMM_BR_V)
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109 stw r4,(CYGARC_REG_IMM_BR1 - CYGARC_REG_IMM_BASE)(r3)
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110
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111 # Set CS2 to
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112 # base addr 0x04000000
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113 # external ACK
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114 # size 64M
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115 # slot1 and slot2
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116 lwi r4,(0xfc000000 | CYGARC_REG_IMM_OR_SETA)
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117 stw r4,(CYGARC_REG_IMM_OR2 - CYGARC_REG_IMM_BASE)(r3)
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118 lwi r4,(0x04000000 | CYGARC_REG_IMM_BR_PS_32 | CYGARC_REG_IMM_BR_V)
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119 stw r4,(CYGARC_REG_IMM_BR2 - CYGARC_REG_IMM_BASE)(r3)
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120
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121 # Set CS3 to
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122 # base addr 0x0e000000
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123 # exernal ack
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124 # size 32M
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125 # covers IO registers
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126 lwi r4,(0xfe000000 | CYGARC_REG_IMM_OR_BI | CYGARC_REG_IMM_OR_SETA)
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127 stw r4,(CYGARC_REG_IMM_OR3 - CYGARC_REG_IMM_BASE)(r3)
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128 lwi r4,(0x0e000000 | CYGARC_REG_IMM_BR_PS_32 | CYGARC_REG_IMM_BR_V)
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129 stw r4,(CYGARC_REG_IMM_BR3 - CYGARC_REG_IMM_BASE)(r3)
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130
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131 #endif
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132
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133 sync
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134 blr
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135
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136 #------------------------------------------------------------------------------
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137 # end of cogent.S