//==========================================================================
//
//      devs/watchdog/arm/at91/watchdog_at91.cxx
//
//      Watchdog implementation for ARM AT91 CPU
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// the terms of the GNU General Public License as published by the Free
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
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// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
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//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    tkoeller
// Contributors: tkoeller
// Date:         2002-05-05
// Purpose:      Watchdog class implementation
// Description:  Contains an implementation of the Watchdog class for use
//               with the ATMEL AT91 watchdog timer.
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/kernel.h>
#include <pkgconf/infra.h>
#include <pkgconf/kernel.h>
#include <pkgconf/watchdog.h>
#include <pkgconf/devs_watchdog_arm_at91.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_ass.h>
#include <cyg/infra/cyg_trac.h>
#include <cyg/hal/hal_io.h>
#include <cyg/hal/plf_io.h>
#include <cyg/hal/hal_diag.h>
#include <cyg/io/watchdog.hxx>
#if !defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT)
#include <cyg/hal/hal_platform_ints.h>
#include <cyg/kernel/intr.hxx>
#endif

#define MCLK_FREQUENCY_KHZ  32768
#define MAX_TICKS     	    0x0000ffff
#define BASE_TICKS    	    (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TMEOUT_MS)

#if   BASE_TICKS / 8 <= MAX_TICKS
#define DIVIDER 0
#define DIV_FACTOR 8
#elif BASE_TICKS / 32 <= MAX_TICKS
#define DIVIDER 1
#define DIV_FACTOR 32
#elif BASE_TICKS / 128 <= MAX_TICKS
#define DIVIDER 2
#define DIV_FACTOR 128
#elif BASE_TICKS / 1024 <= MAX_TICKS
#define DIVIDER 3
#define DIV_FACTOR 1024
#else
#error Desired resolution beyond hardware capabilities
#endif

#define TICKS 	    ((BASE_TICKS / DIV_FACTOR) | 0xfff)
#define RESOLUTION  ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)



#if defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT)

#define OMRVAL	(AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN)

void
Cyg_Watchdog::init_hw(void)
{
  CYG_REPORT_FUNCTION();
  CYG_REPORT_FUNCARGVOID();
  resolution = RESOLUTION;
  CYG_REPORT_RETURN();
}

#else /* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */

#define OMRVAL	(AT91_WD_OMR_OKEY | AT91_WD_OMR_IRQEN | AT91_WD_OMR_WDEN)
#define INT_PRIO    7


static void *
operator new(size_t size)
{
  static cyg_uint8 buf[sizeof (Cyg_Interrupt)];
  CYG_REPORT_FUNCTION();
  CYG_REPORT_FUNCARG1XV(size);
  CYG_ASSERTC(size == sizeof buf);
  CYG_REPORT_RETVAL(buf);
  return buf;
}

static cyg_uint32
isr(cyg_vector vector, CYG_ADDRWORD data)
{
  Cyg_Watchdog &wd = *(Cyg_Watchdog *) data;

  CYG_REPORT_FUNCTION();
  CYG_REPORT_FUNCARG2XV(vector, data);

  wd.trigger();
  Cyg_Interrupt::acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
  CYG_REPORT_RETVAL(Cyg_Interrupt::HANDLED);
  return Cyg_Interrupt::HANDLED;
}

static Cyg_Interrupt * wdint;

void
Cyg_Watchdog::init_hw(void)
{
  CYG_REPORT_FUNCTION();
  CYG_REPORT_FUNCARGVOID();

  resolution = RESOLUTION;
  wdint = new Cyg_Interrupt(
    CYGNUM_HAL_INTERRUPT_WATCHDOG,
    INT_PRIO,
    (CYG_ADDRWORD) this,
    isr,
    NULL
  );
  wdint->configure_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG, false, true);
  wdint->attach();
  wdint->acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
  wdint->unmask_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
  CYG_REPORT_RETURN();
}

#endif	/* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */



/*
 * Reset watchdog timer. This needs to be called regularly to prevent
 * the watchdog from firing.
 */
void
Cyg_Watchdog::reset(void)
{
  CYG_REPORT_FUNCTION();
  CYG_REPORT_FUNCARGVOID();

  /* Write magic code to reset the watchdog. */
  HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
  CYG_REPORT_RETURN();
}

/*
 * Start watchdog to generate a hardware reset
 * or interrupt when expiring.
 */
void
Cyg_Watchdog::start(void)
{
  CYG_REPORT_FUNCTION();
  CYG_REPORT_FUNCARGVOID();
  
  HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY);
  HAL_WRITE_UINT32(
    AT91_WD + AT91_WD_CMR,
    AT91_WD_CMR_CKEY | ((TICKS >> 10) & AT91_WD_CMR_HPCV) | DIVIDER
  );
  HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
  HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, OMRVAL);
  CYG_REPORT_RETURN();
}
