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comparison packages/hal/mips/arch/current/include/hal_cache.h @ 92:08ffab08d2ee ecos-sw-2000-05-26

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Merge from eCos master repository on 2000-05-26-07:47:03-BST
author jlarmour
date Fri, 26 May 2000 13:46:34 +0000
parents 435cced73e2f
children 6bd9d475ed4b
comparison
equal deleted inserted replaced
91:86f6a8b98920 92:08ffab08d2ee
89 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) 89 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
90 90
91 #endif 91 #endif
92 92
93 //----------------------------------------------------------------------------- 93 //-----------------------------------------------------------------------------
94 // Cache instruction uses LSB to specify which WAY to affect. This macro
95 // defines the necessary cache instructions to affect all ways.
96 #if (HAL_DCACHE_WAYS == 1)
97 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
98 asm volatile ("cache %0,0(%1);" \
99 : : "I" (_cmd_), "r"(_addr_) )
100 #elif (HAL_DCACHE_WAYS == 2)
101 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
102 asm volatile ("cache %0,0(%1);" \
103 "cache %0,1(%1);" \
104 : : "I" (_cmd_), "r"(_addr_) )
105 #elif (HAL_DCACHE_WAYS == 4)
106 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
107 asm volatile ("cache %0,0(%1);" \
108 "cache %0,1(%1);" \
109 "cache %0,2(%1);" \
110 "cache %0,3(%1);" \
111 : : "I" (_cmd_), "r"(_addr_) )
112 #else
113 # error "Unsupported number of ways"
114 #endif
115
116 #if (HAL_ICACHE_WAYS == 1)
117 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
118 asm volatile ("cache %0,0(%1);" \
119 : : "I" (_cmd_), "r"(_addr_) )
120 #elif (HAL_ICACHE_WAYS == 2)
121 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
122 asm volatile ("cache %0,0(%1);" \
123 "cache %0,1(%1);" \
124 : : "I" (_cmd_), "r"(_addr_) )
125 #elif (HAL_ICACHE_WAYS == 4)
126 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
127 asm volatile ("cache %0,0(%1);" \
128 "cache %0,1(%1);" \
129 "cache %0,2(%1);" \
130 "cache %0,3(%1);" \
131 : : "I" (_cmd_), "r"(_addr_) )
132 #else
133 # error "Unsupported number of ways"
134 #endif
135
136 //-----------------------------------------------------------------------------
94 // Global control of data cache 137 // Global control of data cache
95 138
96 // Enable the data cache 139 // Enable the data cache
97 // There is no default mechanism for enabling or disabling the caches. 140 // There is no default mechanism for enabling or disabling the caches.
98 #ifndef HAL_DCACHE_ENABLE_DEFINED 141 #ifndef HAL_DCACHE_ENABLE_DEFINED
117 #endif 160 #endif
118 161
119 // Synchronize the contents of the cache with memory. 162 // Synchronize the contents of the cache with memory.
120 // This uses the index-writeback-invalidate operation. 163 // This uses the index-writeback-invalidate operation.
121 #ifndef HAL_DCACHE_SYNC_DEFINED 164 #ifndef HAL_DCACHE_SYNC_DEFINED
122 #define HAL_DCACHE_SYNC() \ 165 #define HAL_DCACHE_SYNC() \
123 { \ 166 CYG_MACRO_START \
124 register CYG_ADDRESS _baddr_ = 0x80000000; \ 167 register CYG_ADDRESS _baddr_ = 0x80000000; \
125 register CYG_ADDRESS _addr_ = 0x80000000; \ 168 register CYG_ADDRESS _addr_ = 0x80000000; \
126 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ 169 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
127 _HAL_ASM_SET_MIPS_ISA(3); \ 170 _HAL_ASM_SET_MIPS_ISA(3); \
128 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 171 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
129 { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \ 172 { _HAL_ASM_DCACHE_ALL_WAYS(0x01, _addr_); } \
130 _HAL_ASM_SET_MIPS_ISA(0); \ 173 _HAL_ASM_SET_MIPS_ISA(0); \
131 } 174 CYG_MACRO_END
132 #endif 175 #endif
133 176
134 // Set the data cache refill burst size 177 // Set the data cache refill burst size
135 //#define HAL_DCACHE_BURST_SIZE(_size_) 178 //#define HAL_DCACHE_BURST_SIZE(_size_)
136 179
142 185
143 // Load the contents of the given address range into the data cache 186 // Load the contents of the given address range into the data cache
144 // and then lock the cache so that it stays there. 187 // and then lock the cache so that it stays there.
145 // This uses the fetch-and-lock cache operation. 188 // This uses the fetch-and-lock cache operation.
146 #ifndef HAL_DCACHE_LOCK_DEFINED 189 #ifndef HAL_DCACHE_LOCK_DEFINED
147 #define HAL_DCACHE_LOCK(_base_, _asize_) \ 190 #define HAL_DCACHE_LOCK(_base_, _asize_) \
148 CYG_MACRO_START \ 191 CYG_MACRO_START \
149 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 192 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
150 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 193 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
151 register CYG_WORD _size_ = (_asize_); \ 194 register CYG_WORD _size_ = (_asize_); \
152 register CYG_WORD _state_; \ 195 register CYG_WORD _state_; \
153 HAL_DCACHE_IS_ENABLED( _state_ ); \ 196 HAL_DCACHE_IS_ENABLED( _state_ ); \
154 if( _state_ ) { \ 197 if( _state_ ) { \
155 _HAL_ASM_SET_MIPS_ISA(3); \ 198 _HAL_ASM_SET_MIPS_ISA(3); \
156 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 199 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
157 { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \ 200 { _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); } \
158 _HAL_ASM_SET_MIPS_ISA(0); \ 201 _HAL_ASM_SET_MIPS_ISA(0); \
159 } \ 202 } \
160 CYG_MACRO_END 203 CYG_MACRO_END
161 #endif 204 #endif
162 205
163 // Undo a previous lock operation. 206 // Undo a previous lock operation.
164 // Do this by flushing the cache, which is defined to clear the lock bit. 207 // Do this by flushing the cache, which is defined to clear the lock bit.
165 #ifndef HAL_DCACHE_UNLOCK_DEFINED 208 #ifndef HAL_DCACHE_UNLOCK_DEFINED
182 225
183 // Write dirty cache lines to memory and invalidate the cache entries 226 // Write dirty cache lines to memory and invalidate the cache entries
184 // for the given address range. 227 // for the given address range.
185 // This uses the hit-writeback-invalidate cache operation. 228 // This uses the hit-writeback-invalidate cache operation.
186 #ifndef HAL_DCACHE_FLUSH_DEFINED 229 #ifndef HAL_DCACHE_FLUSH_DEFINED
187 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ 230 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
188 CYG_MACRO_START \ 231 CYG_MACRO_START \
189 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 232 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
190 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 233 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
191 register CYG_WORD _size_ = (_asize_); \ 234 register CYG_WORD _size_ = (_asize_); \
192 register CYG_WORD _state_; \ 235 register CYG_WORD _state_; \
193 HAL_DCACHE_IS_ENABLED( _state_ ); \ 236 HAL_DCACHE_IS_ENABLED( _state_ ); \
194 if( _state_ ) { \ 237 if( _state_ ) { \
195 _HAL_ASM_SET_MIPS_ISA(3); \ 238 _HAL_ASM_SET_MIPS_ISA(3); \
196 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 239 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
197 { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \ 240 { _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); } \
198 _HAL_ASM_SET_MIPS_ISA(0); \ 241 _HAL_ASM_SET_MIPS_ISA(0); \
199 } \ 242 } \
200 CYG_MACRO_END 243 CYG_MACRO_END
201 #endif 244 #endif
202 245
203 // Invalidate cache lines in the given range without writing to memory. 246 // Invalidate cache lines in the given range without writing to memory.
204 // This uses the hit-invalidate cache operation. 247 // This uses the hit-invalidate cache operation.
205 #ifndef HAL_DCACHE_INVALIDATE_DEFINED 248 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
206 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ 249 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
207 { \ 250 CYG_MACRO_START \
208 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 251 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
209 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 252 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
210 register CYG_WORD _size_ = (_asize_); \ 253 register CYG_WORD _size_ = (_asize_); \
211 _HAL_ASM_SET_MIPS_ISA(3); \ 254 _HAL_ASM_SET_MIPS_ISA(3); \
212 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 255 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
213 { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \ 256 { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); } \
214 _HAL_ASM_SET_MIPS_ISA(0); \ 257 _HAL_ASM_SET_MIPS_ISA(0); \
215 } 258 CYG_MACRO_END
216 #endif 259 #endif
217 260
218 // Write dirty cache lines to memory for the given address range. 261 // Write dirty cache lines to memory for the given address range.
219 // This uses the hit-writeback cache operation. 262 // This uses the hit-writeback cache operation.
220 #ifndef HAL_DCACHE_STORE_DEFINED 263 #ifndef HAL_DCACHE_STORE_DEFINED
221 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \ 264 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
222 CYG_MACRO_START \ 265 CYG_MACRO_START \
223 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 266 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
224 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 267 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
225 register CYG_WORD _size_ = (_asize_); \ 268 register CYG_WORD _size_ = (_asize_); \
226 register CYG_WORD _state_; \ 269 register CYG_WORD _state_; \
227 HAL_DCACHE_IS_ENABLED( _state_ ); \ 270 HAL_DCACHE_IS_ENABLED( _state_ ); \
228 if( _state_ ) { \ 271 if( _state_ ) { \
229 _HAL_ASM_SET_MIPS_ISA(3); \ 272 _HAL_ASM_SET_MIPS_ISA(3); \
230 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 273 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
231 { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \ 274 { _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); } \
232 _HAL_ASM_SET_MIPS_ISA(0); \ 275 _HAL_ASM_SET_MIPS_ISA(0); \
233 } \ 276 } \
234 CYG_MACRO_END 277 CYG_MACRO_END
235 #endif 278 #endif
236 279
237 // Preread the given range into the cache with the intention of reading 280 // Preread the given range into the cache with the intention of reading
238 // from it later. 281 // from it later.
239 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) 282 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
264 #endif 307 #endif
265 308
266 // Invalidate the entire cache 309 // Invalidate the entire cache
267 // This uses the index-invalidate cache operation. 310 // This uses the index-invalidate cache operation.
268 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED 311 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
269 #define HAL_ICACHE_INVALIDATE_ALL() \ 312 #define HAL_ICACHE_INVALIDATE_ALL() \
270 { \ 313 CYG_MACRO_START \
271 register CYG_ADDRESS _baddr_ = 0x80000000; \ 314 register CYG_ADDRESS _baddr_ = 0x80000000; \
272 register CYG_ADDRESS _addr_ = 0x80000000; \ 315 register CYG_ADDRESS _addr_ = 0x80000000; \
273 _HAL_ASM_SET_MIPS_ISA(3); \ 316 _HAL_ASM_SET_MIPS_ISA(3); \
274 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 317 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
275 { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \ 318 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
276 _HAL_ASM_SET_MIPS_ISA(0); \ 319 _HAL_ASM_SET_MIPS_ISA(0); \
277 } 320 CYG_MACRO_END
278 #endif 321 #endif
279 322
280 // Synchronize the contents of the cache with memory. 323 // Synchronize the contents of the cache with memory.
281 // Simply force the cache to reload. 324 // Simply force the cache to reload.
282 #ifndef HAL_ICACHE_SYNC_DEFINED 325 #ifndef HAL_ICACHE_SYNC_DEFINED
288 331
289 // Load the contents of the given address range into the instruction cache 332 // Load the contents of the given address range into the instruction cache
290 // and then lock the cache so that it stays there. 333 // and then lock the cache so that it stays there.
291 // This uses the fetch-and-lock cache operation. 334 // This uses the fetch-and-lock cache operation.
292 #ifndef HAL_ICACHE_LOCK_DEFINED 335 #ifndef HAL_ICACHE_LOCK_DEFINED
293 #define HAL_ICACHE_LOCK(_base_, _asize_) \ 336 #define HAL_ICACHE_LOCK(_base_, _asize_) \
294 CYG_MACRO_START \ 337 CYG_MACRO_START \
295 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 338 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
296 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 339 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
297 register CYG_WORD _size_ = (_asize_); \ 340 register CYG_WORD _size_ = (_asize_); \
298 register CYG_WORD _state_; \ 341 register CYG_WORD _state_; \
299 HAL_ICACHE_IS_ENABLED( _state_ ); \ 342 HAL_ICACHE_IS_ENABLED( _state_ ); \
300 if( _state_ ) { \ 343 if( _state_ ) { \
301 _HAL_ASM_SET_MIPS_ISA(3); \ 344 _HAL_ASM_SET_MIPS_ISA(3); \
302 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 345 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
303 { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \ 346 { _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); } \
304 _HAL_ASM_SET_MIPS_ISA(0); \ 347 _HAL_ASM_SET_MIPS_ISA(0); \
305 } \ 348 } \
306 CYG_MACRO_END 349 CYG_MACRO_END
307 #endif 350 #endif
308 351
309 // Undo a previous lock operation. 352 // Undo a previous lock operation.
310 // Do this by invalidating the cache, which is defined to clear the lock bit. 353 // Do this by invalidating the cache, which is defined to clear the lock bit.
311 #ifndef HAL_ICACHE_UNLOCK_DEFINED 354 #ifndef HAL_ICACHE_UNLOCK_DEFINED
320 // Instruction cache line control 363 // Instruction cache line control
321 364
322 // Invalidate cache lines in the given range without writing to memory. 365 // Invalidate cache lines in the given range without writing to memory.
323 // This uses the hit-invalidate cache operation. 366 // This uses the hit-invalidate cache operation.
324 #ifndef HAL_ICACHE_INVALIDATE_DEFINED 367 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
325 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ 368 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
326 { \ 369 CYG_MACRO_START \
327 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ 370 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
328 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 371 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
329 register CYG_WORD _size_ = (_asize_); \ 372 register CYG_WORD _size_ = (_asize_); \
330 _HAL_ASM_SET_MIPS_ISA(3); \ 373 _HAL_ASM_SET_MIPS_ISA(3); \
331 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 374 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
332 { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \ 375 { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); } \
333 _HAL_ASM_SET_MIPS_ISA(0); \ 376 _HAL_ASM_SET_MIPS_ISA(0); \
334 } 377 CYG_MACRO_END
335 #endif 378 #endif
336 379
337 //----------------------------------------------------------------------------- 380 //-----------------------------------------------------------------------------
338 // Check that a supported configuration has actually defined some macros. 381 // Check that a supported configuration has actually defined some macros.
339 382