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comparison packages/kernel/current/src/common/clock.cxx @ 34:29bc183297e1 ecos-sw-1999-09-02

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Merge from eCos master repository on 1999-09-02-16:26:10-BST
author jlarmour
date Thu, 02 Sep 1999 16:11:22 +0000
parents 7253dcc42a09
children c38311975d4f
comparison
equal deleted inserted replaced
33:7a567ebab069 34:29bc183297e1
658 interrupt.unmask_interrupt(CYGNUM_HAL_INTERRUPT_RTC); 658 interrupt.unmask_interrupt(CYGNUM_HAL_INTERRUPT_RTC);
659 659
660 Cyg_Clock::real_time_clock = this; 660 Cyg_Clock::real_time_clock = this;
661 } 661 }
662 662
663 #ifdef HAL_CLOCK_LATENCY 663 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && defined(HAL_CLOCK_LATENCY)
664 cyg_tick_count total_clock_latency, total_clock_interrupts; 664 cyg_tick_count total_clock_latency, total_clock_interrupts;
665 cyg_int32 min_clock_latency = 0x7FFFFFFF; 665 cyg_int32 min_clock_latency = 0x7FFFFFFF;
666 cyg_int32 max_clock_latency = 0; 666 cyg_int32 max_clock_latency = 0;
667 bool measure_clock_latency = false; 667 bool measure_clock_latency = false;
668 #endif 668 #endif
669 669
670 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY)
671 cyg_tick_count total_clock_dsr_latency, total_clock_dsr_calls;
672 cyg_int32 min_clock_dsr_latency = 0x7FFFFFFF;
673 cyg_int32 max_clock_dsr_latency = 0;
674 cyg_int32 clock_dsr_start = 0;
675 #endif
676
670 // ------------------------------------------------------------------------- 677 // -------------------------------------------------------------------------
671 678
672 cyg_uint32 Cyg_RealTimeClock::isr(cyg_vector vector, CYG_ADDRWORD data) 679 cyg_uint32 Cyg_RealTimeClock::isr(cyg_vector vector, CYG_ADDRWORD data)
673 { 680 {
674 // CYG_REPORT_FUNCTION(); 681 // CYG_REPORT_FUNCTION();
675 682
676 #ifdef HAL_CLOCK_LATENCY 683 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && defined(HAL_CLOCK_LATENCY)
677 if (measure_clock_latency) { 684 if (measure_clock_latency) {
678 cyg_int32 delta; 685 cyg_int32 delta;
679 HAL_CLOCK_LATENCY(&delta); 686 HAL_CLOCK_LATENCY(&delta);
680 // Note: Ignore a latency of 0 when finding min_clock_latency. 687 // Note: Ignore a latency of 0 when finding min_clock_latency.
681 if (delta > 0) { 688 if (delta > 0) {
691 CYG_INSTRUMENT_CLOCK( ISR, 0, 0); 698 CYG_INSTRUMENT_CLOCK( ISR, 0, 0);
692 699
693 HAL_CLOCK_RESET( CYGNUM_HAL_INTERRUPT_RTC, CYGNUM_KERNEL_COUNTERS_RTC_PERIOD ); 700 HAL_CLOCK_RESET( CYGNUM_HAL_INTERRUPT_RTC, CYGNUM_KERNEL_COUNTERS_RTC_PERIOD );
694 701
695 Cyg_Interrupt::acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_RTC); 702 Cyg_Interrupt::acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_RTC);
696 703
704 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY)
705 HAL_CLOCK_READ(&clock_dsr_start);
706 #endif
697 return Cyg_Interrupt::CALL_DSR|Cyg_Interrupt::HANDLED; 707 return Cyg_Interrupt::CALL_DSR|Cyg_Interrupt::HANDLED;
698 } 708 }
699 709
700 // ------------------------------------------------------------------------- 710 // -------------------------------------------------------------------------
701 711
702 void Cyg_RealTimeClock::dsr(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data) 712 void Cyg_RealTimeClock::dsr(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data)
703 { 713 {
704 // CYG_REPORT_FUNCTION(); 714 // CYG_REPORT_FUNCTION();
715
716 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_DSR_LATENCY)
717 if (measure_clock_latency) {
718 cyg_int32 delta;
719 HAL_CLOCK_READ(&delta);
720 delta -= clock_dsr_start;
721 // Note: Ignore a latency of <= 0 when finding min_clock_latency.
722 if (delta > 0 ) {
723 // Valid delta measured
724 total_clock_dsr_latency += delta;
725 total_clock_dsr_calls++;
726 if (min_clock_dsr_latency > delta) min_clock_dsr_latency = delta;
727 if (max_clock_dsr_latency < delta) max_clock_dsr_latency = delta;
728 }
729 }
730 #endif
705 731
706 Cyg_RealTimeClock *rtc = (Cyg_RealTimeClock *)data; 732 Cyg_RealTimeClock *rtc = (Cyg_RealTimeClock *)data;
707 733
708 CYG_INSTRUMENT_CLOCK( TICK_START, 734 CYG_INSTRUMENT_CLOCK( TICK_START,
709 rtc->current_value_lo(), 735 rtc->current_value_lo(),