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comparison packages/hal/arm/aeb/current/include/hal_cache.h @ 44:41bd4f3a90de ecos-sw-1999-10-08

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Merge from eCos master repository on 1999-10-08-07:47:04-BST
author jlarmour
date Fri, 08 Oct 1999 13:16:25 +0000
parents 443894e2e912
children c38311975d4f
comparison
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43:3e1bfbe59ff6 44:41bd4f3a90de
49 49
50 #include <cyg/infra/cyg_type.h> 50 #include <cyg/infra/cyg_type.h>
51 #include <cyg/hal/hal_io.h> 51 #include <cyg/hal/hal_io.h>
52 52
53 //----------------------------------------------------------------------------- 53 //-----------------------------------------------------------------------------
54 // Cache dimensions 54 // Cache dimensions - one unified cache
55 55
56 // Data cache 56 #define HAL_CACHE_UNIFIED
57 #define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes 57
58 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line 58 #define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes
59 #define HAL_DCACHE_WAYS 4 // Associativity of the cache 59 #define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line
60 60 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
61 // Instruction cache 61
62 #define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes 62 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
63 #define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line
64 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
65
66 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
67 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
68 63
69 // Cache & SRAM control 64 // Cache & SRAM control
70 #define CYG_DEVICE_CCR ((volatile cyg_uint8 *)0xFFFFA400) 65 #define CYG_DEVICE_CCR 0xFFFFA400
71 #define CYG_DEVICE_LSCR ((volatile cyg_uint8 *)0xFFFFA404) 66 #define CYG_DEVICE_LSCR 0xFFFFA404
67 #define CYG_DEVICE_CACHE_MEM 0x60000800
72 68
73 #define CCR_E 0x01 // Cache enabled 69 #define CCR_E 0x01 // Cache enabled
74 #define CCR_S 0x02 // SRAM mode enabled 70 #define CCR_S 0x02 // SRAM mode enabled
75 #define CCR_F 0x04 // Flush mode enabled 71 #define CCR_F 0x04 // Flush mode enabled
76 #define CCR_I 0x08 // Invalidate mode 72 #define CCR_I 0x08 // Invalidate mode
77 73
78 #define LCSR_E 0x01 // Local SRAM enabled 74 #define LCSR_E 0x01 // Local SRAM enabled
79 #define LCSR_L 0x02 // Local SRAM mapped to high memory 75 #define LCSR_L 0x02 // Local SRAM mapped to high memory
80 76
81 //----------------------------------------------------------------------------- 77 //-----------------------------------------------------------------------------
82 // Global control of data cache 78 // Global control of cache
83 79
84 // Enable the data cache 80 // Enable the cache
85 #define HAL_DCACHE_ENABLE() \ 81 #define HAL_UCACHE_ENABLE() \
86 { \ 82 { \
87 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_E); \ 83 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \
88 } 84 }
89 85
90 // Disable the data cache 86 // Disable the cache
91 #define HAL_DCACHE_DISABLE() \ 87 #define HAL_UCACHE_DISABLE() \
92 { \ 88 { \
93 HAL_WRITE_UINT32(CYG_DEVICE_CCR, 0); \ 89 HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \
94 } 90 }
95 91
96 // Invalidate the entire cache 92 // Invalidate the entire cache
97 #define HAL_DCACHE_INVALIDATE_ALL() \ 93 #define HAL_UCACHE_INVALIDATE_ALL() \
98 { \ 94 { \
99 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \ 95 register cyg_uint8 old_ccr; \
96 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \
97 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \
98 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \
100 } 99 }
101 100
102 // Synchronize the contents of the cache with memory. 101 // Synchronize the contents of the cache with memory.
103 #define HAL_DCACHE_SYNC() \ 102 #define HAL_UCACHE_SYNC() \
104 { \ 103 { \
105 cyg_uint32 *cache_SRAM = (cyg_uint32 *)0x60000800; \ 104 register volatile cyg_uint8 *cache_SRAM = \
106 int i; \ 105 (volatile cyg_uint8*) CYG_DEVICE_CACHE_MEM; \
107 cyg_uint32 old_ccr; \ 106 register int i; \
108 HAL_READ_UINT32(CYG_DEVICE_CCR, old_ccr); \ 107 register cyg_uint8 old_ccr; \
109 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_F); \ 108 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \
109 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \
110 for (i = 0; i < HAL_DCACHE_SETS; i++) { \ 110 for (i = 0; i < HAL_DCACHE_SETS; i++) { \
111 *cache_SRAM = 0; \ 111 *cache_SRAM = 0; \
112 cache_SRAM += HAL_DCACHE_LINE_SIZE; \ 112 cache_SRAM += HAL_DCACHE_LINE_SIZE; \
113 } \ 113 } \
114 HAL_WRITE_UINT32(CYG_DEVICE_CCR, CCR_I); \ 114 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \
115 HAL_WRITE_UINT32(CYG_DEVICE_CCR, old_ccr); \ 115 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \
116 } 116 }
117 117
118 // Purge contents of data cache 118 // Query the state of the cache
119 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_INVALIDATE_ALL() 119 #define HAL_UCACHE_IS_ENABLED(_state_) \
120 { \
121 cyg_uint8 __ccr; \
122 HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \
123 (_state_) = (CCR_E == __ccr) ? 1 : 0; \
124 }
125
126 // Purge contents of cache
127 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
128
129 // Set the cache refill burst size
130 //#define HAL_UCACHE_BURST_SIZE(_size_)
131
132 // Set the cache write mode
133 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
134
135 //#define HAL_UCACHE_WRITETHRU_MODE 0
136 //#define HAL_UCACHE_WRITEBACK_MODE 1
137
138 // Load the contents of the given address range into the cache
139 // and then lock the cache so that it stays there.
140 //#define HAL_UCACHE_LOCK(_base_, _size_)
141
142 // Undo a previous lock operation
143 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
144
145 // Unlock entire cache
146 //#define HAL_UCACHE_UNLOCK_ALL()
147
148 //-----------------------------------------------------------------------------
149 // Cache line control
150
151 // Allocate cache lines for the given address range without reading its
152 // contents from memory.
153 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
154
155 // Write dirty cache lines to memory and invalidate the cache entries
156 // for the given address range.
157 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
158
159 // Invalidate cache lines in the given range without writing to memory.
160 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
161
162 // Write dirty cache lines to memory for the given address range.
163 //#define HAL_UCACHE_STORE( _base_ , _size_ )
164
165 // Preread the given range into the cache with the intention of reading
166 // from it later.
167 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
168
169 // Preread the given range into the cache with the intention of writing
170 // to it later.
171 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
172
173 // Allocate and zero the cache lines associated with the given range.
174 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
175
176 //-----------------------------------------------------------------------------
177
178 //-----------------------------------------------------------------------------
179 // Data and instruction cache macros map onto the both-cache macros
180
181 //-----------------------------------------------------------------------------
182 // Global control of data cache
183
184 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
185 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
186 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
187 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
188
189 // Enable the data cache
190 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
191
192 // Disable the data cache
193 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
194
195 // Invalidate the entire cache
196 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
197
198 // Synchronize the contents of the cache with memory.
199 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
200
201 // Query the state of the data cache
202 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
120 203
121 // Set the data cache refill burst size 204 // Set the data cache refill burst size
122 //#define HAL_DCACHE_BURST_SIZE(_size_) 205 //#define HAL_DCACHE_BURST_SIZE(_size_)
123 206
124 // Set the data cache write mode 207 // Set the data cache write mode
164 247
165 // Allocate and zero the cache lines associated with the given range. 248 // Allocate and zero the cache lines associated with the given range.
166 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) 249 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
167 250
168 //----------------------------------------------------------------------------- 251 //-----------------------------------------------------------------------------
169 // Global control of Instruction cache - use Data cache controls since they 252 // Global control of Instruction cache
170 // are not separatable. 253
254 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
255 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
256 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
257 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
171 258
172 // Enable the instruction cache 259 // Enable the instruction cache
173 #define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() 260 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
174 261
175 // Disable the instruction cache 262 // Disable the instruction cache
176 #define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() 263 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
177 264
178 // Invalidate the entire cache 265 // Invalidate the entire cache
179 #define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL() 266 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
267
180 268
181 // Synchronize the contents of the cache with memory. 269 // Synchronize the contents of the cache with memory.
182 #define HAL_ICACHE_SYNC() 270 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
271
272 // Query the state of the instruction cache
273 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
183 274
184 // Set the instruction cache refill burst size 275 // Set the instruction cache refill burst size
185 //#define HAL_ICACHE_BURST_SIZE(_size_) 276 //#define HAL_ICACHE_BURST_SIZE(_size_)
186 277
187 // Load the contents of the given address range into the instruction cache 278 // Load the contents of the given address range into the instruction cache
188 // and then lock the cache so that it stays there. 279 // and then lock the cache so that it stays there.
280
189 //#define HAL_ICACHE_LOCK(_base_, _size_) 281 //#define HAL_ICACHE_LOCK(_base_, _size_)
190 282
191 // Undo a previous lock operation 283 // Undo a previous lock operation
192 //#define HAL_ICACHE_UNLOCK(_base_, _size_) 284 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
193 285
198 // Instruction cache line control 290 // Instruction cache line control
199 291
200 // Invalidate cache lines in the given range without writing to memory. 292 // Invalidate cache lines in the given range without writing to memory.
201 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) 293 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
202 294
203 //-----------------------------------------------------------------------------
204 #endif // ifndef CYGONCE_HAL_CACHE_H 295 #endif // ifndef CYGONCE_HAL_CACHE_H
205 // End of hal_cache.h 296 // End of hal_cache.h