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comparison packages/cygmon/current/misc/arm/cpu.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents
children e0c0827131d1
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75:41bf073c0c32 76:435cced73e2f
1 #ifndef __ARM_CPU_H__
2 #define __ARM_CPU_H__
3 //==========================================================================
4 //
5 // cpu.h
6 //
7 // ARM specific processor defines
8 //
9 //==========================================================================
10 //####COPYRIGHTBEGIN####
11 //
12 // -------------------------------------------
13 // The contents of this file are subject to the Red Hat eCos Public License
14 // Version 1.1 (the "License"); you may not use this file except in
15 // compliance with the License. You may obtain a copy of the License at
16 // http://www.redhat.com/
17 //
18 // Software distributed under the License is distributed on an "AS IS"
19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 // License for the specific language governing rights and limitations under
21 // the License.
22 //
23 // The Original Code is eCos - Embedded Configurable Operating System,
24 // released September 30, 1998.
25 //
26 // The Initial Developer of the Original Code is Red Hat.
27 // Portions created by Red Hat are
28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 // All Rights Reserved.
30 // -------------------------------------------
31 //
32 //####COPYRIGHTEND####
33 //==========================================================================
34 //#####DESCRIPTIONBEGIN####
35 //
36 // Author(s):
37 // Contributors: gthomas
38 // Date: 1999-10-20
39 // Purpose: ARM specific processor defines
40 // Description: ARM is a Registered Trademark of Advanced RISC Machines
41 // Limited.
42 // Other Brands and Trademarks are the property of their
43 // respective owners.
44 //
45 //####DESCRIPTIONEND####
46 //
47 //=========================================================================
48
49 #include <bsp/bsp.h>
50 #include <bsp/defs.h>
51 #ifdef __ECOS__
52 #include <cyg/hal/hal_arch.h>
53 #endif
54
55 /*
56 * Only define __NEED_UNDERSCORE__ for arm-coff targets
57 */
58 #if !defined(__ELF__)
59 # define __NEED_UNDERSCORE__
60 #endif
61
62 /*
63 * Macros to glue together two tokens.
64 */
65 # ifdef __STDC__
66 # define XGLUE(a,b) a##b
67 # else
68 # define XGLUE(a,b) a/**/b
69 # endif
70
71 # define GLUE(a,b) XGLUE(a,b)
72
73 /*
74 * Symbol Names with leading underscore if necessary
75 */
76 # ifdef __NEED_UNDERSCORE__
77 # define SYM_NAME(name) GLUE(_,name)
78 # else
79 # define SYM_NAME(name) name
80 # endif /* __NEED_UNDERSCORE__ */
81
82 /*
83 * Various macros to better handle assembler/object format differences
84 */
85 #if defined(__ASSEMBLER__)
86
87 /*
88 * Assembly function start definition
89 */
90 #ifdef __NEED_UNDERSCORE__
91 .macro FUNC_START name
92 .global _\name
93 .align 4
94 _\name:
95 .endm
96 #else
97 .macro FUNC_START name
98 .global \name
99 .align 4
100 \name:
101 .endm
102 #endif
103
104 /*
105 * Assembly function end definition
106 */
107 #ifdef __NEED_UNDERSCORE__
108 .macro FUNC_END name
109 .endm
110 #else
111 .macro FUNC_END name
112 .endm
113 #endif
114
115 /*
116 * Register Prefix
117 */
118 # ifndef __REGISTER_PREFIX__
119 # define __REGISTER_PREFIX__
120 # endif /* __REGISTER_PREFIX__ */
121
122 /*
123 * Immediate Prefix
124 */
125 # ifndef __IMM_PREFIX__
126 # define __IMM_PREFIX__ #
127 # endif /* __IMM_PREFIX__ */
128
129 /*
130 * use the right prefix for registers.
131 */
132 # define REG(x) GLUE(__REGISTER_PREFIX__,x)
133
134 /*
135 * use the right prefix for immediate values.
136 */
137 # define IMM(x) GLUE(__IMM_PREFIX__,x)
138
139 #endif /* defined(__ASSEMBLER__) */
140
141
142 /*
143 * Setup register defines and such
144 */
145 #if defined(__ASSEMBLER__)
146
147 # define r0 REG (r0)
148 # define r1 REG (r1)
149 # define r2 REG (r2)
150 # define r3 REG (r3)
151
152 # define r4 REG (r4)
153 # define r5 REG (r5)
154 # define r6 REG (r6)
155 # define r7 REG (r7)
156 # define r8 REG (r8)
157 # define r9 REG (r9)
158 # define r10 REG (r10)
159 # define r11 REG (r11)
160 # define r12 REG (r12)
161 # define r13 REG (r13)
162 # define sp REG (sp)
163 # define r14 REG (r14)
164 # define lr REG (lr)
165 # define pc REG (pc)
166
167 # define f0 REG (f0)
168 # define f1 REG (f1)
169 # define f2 REG (f2)
170 # define f3 REG (f3)
171 # define f4 REG (f4)
172 # define f5 REG (f5)
173 # define f6 REG (f6)
174 # define f7 REG (f7)
175 # define fps REG (fps)
176
177 # define cpsr REG (cpsr)
178 # define spsr REG (spsr)
179
180 /*
181 * Register offset definitions
182 * These numbers are offsets into the ex_regs_t struct.
183 */
184 # define r0_o 0
185 # define r1_o 4
186 # define r2_o 8
187 # define r3_o 12
188 # define r4_o 16
189 # define r5_o 20
190 # define r6_o 24
191 # define r7_o 28
192 # define r8_o 32
193 # define r9_o 36
194 # define r10_o 40
195 # define r11_o 44
196 # define r12_o 48
197 # define r13_o 52
198 # define sp_o r13_o
199 # define r14_o 56
200 # define lr_o r14_o
201 # define pc_o 60
202
203 # define f0_o 64
204 # define f1_o 76
205 # define f2_o 88
206 # define f3_o 100
207 # define f4_o 112
208 # define f5_o 124
209 # define f6_o 136
210 # define f7_o 148
211 # define fps_o 160
212
213 # define cpsr_o 164
214 # define spsvc_o 168
215 # define ARM_EX_REGS_T_SIZE 172
216
217 #else /* !defined(__ASSEMBLER__) */
218
219 /*
220 * Register name that is used in help strings and such
221 */
222 # define REGNAME_EXAMPLE "r0"
223
224 /*
225 * Register numbers. These are assumed to match the
226 * register numbers used by GDB.
227 */
228 enum __regnames {
229 REG_R0,
230 REG_R1,
231 REG_R2,
232 REG_R3,
233 REG_R4,
234 REG_R5,
235 REG_R6,
236 REG_R7,
237 REG_R8,
238 REG_R9,
239 REG_R10,
240 REG_R11,
241 REG_R12,
242 REG_R13,
243 REG_SP=REG_R13,
244 REG_R14,
245 REG_LR=REG_R14,
246 REG_PC,
247
248 REG_F0,
249 REG_F1,
250 REG_F2,
251 REG_F3,
252 REG_F4,
253 REG_F5,
254 REG_F6,
255 REG_F7,
256 REG_FPS,
257
258 REG_CPSR,
259 REG_SPSVC,
260 REG_MAX=REG_SPSVC
261 };
262
263 /*
264 * 12-byte struct for storing Floating point registers
265 */
266 typedef struct
267 {
268 unsigned long high;
269 unsigned long middle;
270 unsigned long low;
271 } fp_reg;
272
273 /*
274 * How registers are stored for exceptions.
275 */
276 #ifdef __ECOS__
277 #define ex_regs_t HAL_SavedRegisters
278 #define _r0 d[0]
279 #define _r1 d[1]
280 #define _r2 d[2]
281 #define _r3 d[3]
282 #define _r4 d[4]
283 #define _r5 d[5]
284 #define _r6 d[6]
285 #define _r7 d[7]
286 #define _r8 d[8]
287 #define _r9 d[9]
288 #define _r10 d[10]
289 #define _r11 fp
290 #define _r12 ip
291 #define _r13 sp
292 #define _r14 lr
293 #define _pc pc
294 #define _cpsr cpsr
295 #define _spsvc msr
296 #else
297 typedef struct
298 {
299 unsigned long _r0;
300 unsigned long _r1;
301 unsigned long _r2;
302 unsigned long _r3;
303 unsigned long _r4;
304 unsigned long _r5;
305 unsigned long _r6;
306 unsigned long _r7;
307 unsigned long _r8;
308 unsigned long _r9;
309 unsigned long _r10;
310 unsigned long _r11;
311 unsigned long _r12;
312 unsigned long _r13;
313 unsigned long _r14;
314 unsigned long _pc;
315
316 fp_reg _f0;
317 fp_reg _f1;
318 fp_reg _f2;
319 fp_reg _f3;
320 fp_reg _f4;
321 fp_reg _f5;
322 fp_reg _f6;
323 fp_reg _f7;
324 unsigned long _fps;
325 unsigned long _cpsr;
326
327 unsigned long _spsvc; /* saved svc mode sp */
328
329 } ex_regs_t;
330 #endif
331 # define _sp _r13
332 # define _lr _r14
333
334 extern void __icache_flush(void *addr, int nbytes);
335 extern void __dcache_flush(void *addr, int nbytes);
336
337 #endif /* __ASSEMBLER__ */
338
339
340 /*
341 * Program Status Register Definitions
342 */
343 #if defined(__ASSEMBLER__)
344 # define ARM_PSR_NEGATIVE 0x80000000 /* Negative Bit */
345 # define ARM_PSR_ZERO 0x40000000 /* Zero Bit */
346 # define ARM_PSR_CARRY 0x20000000 /* Carry Bit */
347 # define ARM_PSR_OVERFLOW 0x10000000 /* Overflow Bit */
348 # define ARM_PSR_IRQ 0x00000080 /* IRQ Bit */
349 # define ARM_PSR_FIQ 0x00000040 /* FIQ Bit */
350 # define ARM_PSR_THUMB_STATE 0x00000020 /* Thumb/ARM(R) Execution */
351 # define ARM_PSR_MODE_MASK 0x0000001F /* ARM(R) Processor Mode Mask */
352 #else /* ! defined(__ASSEMBLER__) */
353 struct psr_struct {
354 unsigned mode : 5;
355 unsigned t_bit : 1;
356 unsigned f_bit : 1;
357 unsigned i_bit : 1;
358 unsigned rsv1 : 20; /* == 0x00000 */
359 unsigned v_bit : 1;
360 unsigned c_bit : 1;
361 unsigned z_bit : 1;
362 unsigned n_bit : 1;
363 };
364
365 union arm_psr {
366 unsigned long word;
367 struct psr_struct psr;
368 };
369 #endif /* __ASSEMBLER__ */
370
371 /*
372 * PSR Mode values
373 */
374 #define ARM_PSR_MODE_USER 0x00000010 /* User mode */
375 #define ARM_PSR_MODE_FIQ 0x00000011 /* FIQ mode */
376 #define ARM_PSR_MODE_IRQ 0x00000012 /* IRQ mode */
377 #define ARM_PSR_MODE_SVC 0x00000013 /* SVC mode */
378 #define ARM_PSR_MODE_ABORT 0x00000017 /* ABORT mode */
379 #define ARM_PSR_MODE_UNDEF 0x0000001B /* UNDEF mode */
380 #define ARM_PSR_MODE_SYSTEM 0x0000001F /* System Mode */
381 #define ARM_PSR_NUM_MODES 7
382
383 /*
384 * Core Exception vectors.
385 */
386 #define BSP_CORE_EXC_RESET 0
387 #define BSP_CORE_EXC_UNDEFINED_INSTRUCTION 1
388 #define BSP_CORE_EXC_SOFTWARE_INTERRUPT 2
389 #define BSP_CORE_EXC_PREFETCH_ABORT 3
390 #define BSP_CORE_EXC_DATA_ABORT 4
391 #define BSP_CORE_EXC_ADDRESS_ERROR_26_BIT 5
392 #define BSP_CORE_EXC_IRQ 6
393 #define BSP_CORE_EXC_FIQ 7
394 #define BSP_MAX_EXCEPTIONS 8
395 #define BSP_CORE_EXC(vec_num) (unsigned long*)(vec_num << 2)
396
397 #define BREAKPOINT_INSN 0xE7FFDEFE /* Illegal inst opcode */
398 #define SYSCALL_SWI 0x00180001
399
400 #if defined(__ASSEMBLER__)
401 .macro BREAKPOINT
402 .word BREAKPOINT_INSN
403 .endm
404 .macro SYSCALL
405 swi IMM(SYSCALL_SWI)
406 .endm
407 .macro __CLI
408 stmfd sp!, {r0}
409 mrs r0, cpsr
410 bic r0, r0, IMM(ARM_PSR_IRQ | ARM_PSR_FIQ)
411 msr cpsr, r0
412 ldmfd sp!, {r0}
413 .endm
414 .macro __STI
415 stmfd sp!, {r0}
416 mrs r0, cpsr
417 orr r0, r0, IMM(ARM_PSR_IRQ | ARM_PSR_FIQ)
418 msr cpsr, r0
419 ldmfd sp!, {r0}
420 .endm
421
422 # if 0
423 /*
424 * Use this code to verify a particular processing mode
425 */
426 mrs r0, cpsr
427 and r0, r0, IMM(ARM_PSR_MODE_MASK)
428 ldr r1, =ARM_PSR_MODE_IRQ
429 cmps r0, r1
430 0: bne 0b
431 PORT_TOGGLE_DEBUG
432 # endif /* 0 */
433
434 #else /* !defined(__ASSEMBLER__) */
435
436 # define BREAKPOINT() asm volatile(" .word 0xE7FFDEFE")
437 # define SYSCALL() asm volatile(" swi %0" : /* No outputs */ : "i" (SYSCALL_SWI))
438 # define __cli() asm volatile("
439 stmfd sp!, {r0}
440 mrs r0, cpsr
441 bic r0, r0, #0x000000C0
442 msr cpsr, r0
443 ldmfd sp!, {r0}")
444 # define __sti() asm volatile("
445 stmfd sp!, {r0}
446 mrs r0, cpsr
447 orr r0, r0, #0x000000C0
448 msr cpsr, r0
449 ldmfd sp!, {r0}")
450 # define __mcr(cp_num, opcode1, Rd, CRn, CRm, opcode2) \
451 asm volatile (" mcr " cp_num ", " \
452 opcode1 ", " \
453 "%0" ", " \
454 CRn ", " \
455 CRm ", " \
456 opcode2 : /* no outputs */ : "r" (Rd))
457 # define __mrc(cp_num, opcode1, Rd, CRn, CRm, opcode2) \
458 asm volatile (" mrc " cp_num ", " \
459 opcode1 ", " \
460 "%0" ", " \
461 CRn ", " \
462 CRm ", " \
463 opcode2 : "=r" (Rd) : /* no inputs */)
464
465 static inline unsigned __get_cpsr(void)
466 {
467 unsigned long retval;
468 asm volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
469 return retval;
470 }
471
472 static inline void __set_cpsr(unsigned val)
473 {
474 asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
475 }
476
477 static inline unsigned __get_spsr(void)
478 {
479 unsigned long retval;
480 asm volatile (" mrs %0, spsr" : "=r" (retval) : /* no inputs */ );
481 return retval;
482 }
483
484 static inline void __set_spsr(unsigned val)
485 {
486 asm volatile (" msr spsr, %0" : /* no outputs */ : "r" (val) );
487 }
488
489 static inline unsigned __get_sp(void)
490 {
491 unsigned long retval;
492 asm volatile (" mov %0, sp" : "=r" (retval) : /* no inputs */ );
493 return retval;
494 }
495
496 static inline void __set_sp(unsigned val)
497 {
498 asm volatile (" mov sp, %0" : /* no outputs */ : "r" (val) );
499 }
500
501 static inline unsigned __get_fp(void)
502 {
503 unsigned long retval;
504 asm volatile (" mov %0, fp" : "=r" (retval) : /* no inputs */ );
505 return retval;
506 }
507
508 static inline void __set_fp(unsigned val)
509 {
510 asm volatile (" mov fp, %0" : /* no outputs */ : "r" (val) );
511 }
512
513 static inline unsigned __get_pc(void)
514 {
515 unsigned long retval;
516 asm volatile (" mov %0, pc" : "=r" (retval) : /* no inputs */ );
517 return retval;
518 }
519
520 static inline void __set_pc(unsigned val)
521 {
522 asm volatile (" mov pc, %0" : /* no outputs */ : "r" (val) );
523 }
524
525 static inline unsigned __get_lr(void)
526 {
527 unsigned long retval;
528 asm volatile (" mov %0, lr" : "=r" (retval) : /* no inputs */ );
529 return retval;
530 }
531
532 static inline void __set_lr(unsigned val)
533 {
534 asm volatile (" mov lr, %0" : /* no outputs */ : "r" (val) );
535 }
536
537 static inline unsigned __get_r8(void)
538 {
539 unsigned long retval;
540 asm volatile (" mov %0, r8" : "=r" (retval) : /* no inputs */ );
541 return retval;
542 }
543
544 static inline void __set_r8(unsigned val)
545 {
546 asm volatile (" mov r8, %0" : /* no outputs */ : "r" (val) );
547 }
548
549 static inline unsigned __get_r9(void)
550 {
551 unsigned long retval;
552 asm volatile (" mov %0, r9" : "=r" (retval) : /* no inputs */ );
553 return retval;
554 }
555
556 static inline void __set_r9(unsigned val)
557 {
558 asm volatile (" mov r9, %0" : /* no outputs */ : "r" (val) );
559 }
560
561 static inline unsigned __get_r10(void)
562 {
563 unsigned long retval;
564 asm volatile (" mov %0, r10" : "=r" (retval) : /* no inputs */ );
565 return retval;
566 }
567
568 static inline void __set_r10(unsigned val)
569 {
570 asm volatile (" mov r10, %0" : /* no outputs */ : "r" (val) );
571 }
572
573 static inline unsigned __get_r11(void)
574 {
575 unsigned long retval;
576 asm volatile (" mov %0, r11" : "=r" (retval) : /* no inputs */ );
577 return retval;
578 }
579
580 static inline void __set_r11(unsigned val)
581 {
582 asm volatile (" mov r11, %0" : /* no outputs */ : "r" (val) );
583 }
584
585 static inline unsigned __get_r12(void)
586 {
587 unsigned long retval;
588 asm volatile (" mov %0, r12" : "=r" (retval) : /* no inputs */ );
589 return retval;
590 }
591
592 static inline void __set_r12(unsigned val)
593 {
594 asm volatile (" mov r12, %0" : /* no outputs */ : "r" (val) );
595 }
596
597 #endif /* defined(__ASSEMBLER__) */
598
599 #define GDB_BREAKPOINT_VECTOR BSP_CORE_EXC_UNDEFINED_INSTRUCTION
600 #define GDB_SYSCALL_VECTOR BSP_CORE_EXC_SOFTWARE_INTERRUPT
601
602 #define ARM_INST_SIZE sizeof(unsigned long)
603 #define GDB_BREAKPOINT_INST_SIZE ARM_INST_SIZE
604
605 #ifdef __CPU_LH77790A__
606 # include <bsp/lh77790a.h>
607 #endif /* __CPU_LH77790A__ */
608
609 #if !defined(__ASSEMBLER__)
610 /*
611 * Define the CPU specific data
612 */
613 #ifdef __CPU_LH77790A__
614 typedef struct {
615 unsigned char lh77790a_port_control_shadow;
616 } arm_cpu_data;
617 #endif /* __CPU_LH77790A__ */
618 #endif /* !defined(__ASSEMBLER__) */
619
620 #ifdef __CPU_SA110__
621 #include <bsp/sa-110.h>
622 #endif /* __CPU_SA110__ */
623
624 #ifdef __CPU_SA1100__
625 #include <bsp/sa-1100.h>
626 #endif /* __CPU_SA110__ */
627
628 #ifdef __CPU_710T__
629 #include <bsp/arm710t.h>
630 #endif /* __CPU_710T__ */
631
632 #ifdef MMU
633 /*
634 * ARM(R) MMU Definitions
635 */
636
637 #ifndef __ASSEMBLER__
638 extern void *page1;
639 #endif /* __ASSEMBLER__ */
640
641 /*
642 * ARM(R) Cache and MMU Control Registers
643 *
644 * Accessed through coprocessor instructions.
645 */
646 #ifdef __ASSEMBLER__
647 # define ARM_CACHE_COPROCESSOR_NUM p15
648 # define ARM_COPROCESSOR_OPCODE_DONT_CARE 0x0
649 # define ARM_COPROCESSOR_RM_DONT_CARE c0
650 #else /* __ASSEMBLER__ */
651 # define ARM_CACHE_COPROCESSOR_NUM "p15"
652 # define ARM_COPROCESSOR_OPCODE_DONT_CARE "0x0"
653 # define ARM_COPROCESSOR_RM_DONT_CARE "c0"
654 #endif /* __ASSEMBLER__ */
655
656 #ifdef __ASSEMBLER__
657 # define ARM_ID_REGISTER c0
658 # define ARM_CONTROL_REGISTER c1
659 # define ARM_TRANSLATION_TABLE_BASE_REGISTER c2
660 # define ARM_DOMAIN_ACCESS_CONTROL_REGISTER c3
661 # define ARM_FAULT_STATUS_REGISTER c5
662 # define ARM_FAULT_ADDRESS_REGISTER c6
663 # define ARM_CACHE_OPERATIONS_REGISTER c7
664 # define ARM_TLB_OPERATIONS_REGISTER c8
665 # define ARM_READ_BUFFER_OPERATIONS_REGISTER c9
666 #else /* __ASSEMBLER__ */
667 # define ARM_ID_REGISTER "c0"
668 # define ARM_CONTROL_REGISTER "c1"
669 # define ARM_TRANSLATION_TABLE_BASE_REGISTER "c2"
670 # define ARM_DOMAIN_ACCESS_CONTROL_REGISTER "c3"
671 # define ARM_FAULT_STATUS_REGISTER "c5"
672 # define ARM_FAULT_ADDRESS_REGISTER "c6"
673 # define ARM_CACHE_OPERATIONS_REGISTER "c7"
674 # define ARM_TLB_OPERATIONS_REGISTER "c8"
675 # define ARM_READ_BUFFER_OPERATIONS_REGISTER "c9"
676 #endif /* __ASSEMBLER__ */
677
678 /*
679 * SA-1100 Cache and MMU ID Register value
680 */
681 #define ARM_ID_MASK 0xFFFFFFF0
682 #define ARM_ID_VALUE 0x4401a110
683
684 /*
685 * SA-1100 Cache Control Register Bit Fields and Masks
686 */
687 #define ARM_MMU_DISABLED 0x00000000
688 #define ARM_MMU_ENABLED 0x00000001
689 #define ARM_MMU_MASK 0x00000001
690 #define ARM_ADDRESS_FAULT_DISABLED 0x00000000
691 #define ARM_ADDRESS_FAULT_ENABLED 0x00000002
692 #define ARM_ADDRESS_FAULT_MASK 0x00000002
693 #define ARM_DATA_CACHE_DISABLED 0x00000000
694 #define ARM_DATA_CACHE_ENABLED 0x00000004
695 #define ARM_DATA_CACHE_MASK 0x00000004
696 #define ARM_WRITE_BUFFER_DISABLED 0x00000000
697 #define ARM_WRITE_BUFFER_ENABLED 0x00000008
698 #define ARM_WRITE_BUFFER_MASK 0x00000008
699 #define ARM_LITTLE_ENDIAN 0x00000000
700 #define ARM_BIG_ENDIAN 0x00000080
701 #define ARM_ACCESS_CHECKS_NONE 0x00000000
702 #define ARM_ACCESS_CHECKS_SYSTEM 0x00000100
703 #define ARM_ACCESS_CHECKS_ROM 0x00000200
704 #define ARM_INSTRUCTION_CACHE_DISABLED 0x00000000
705 #define ARM_INSTRUCTION_CACHE_ENABLED 0x00001000
706 #define ARM_INSTRUCTION_CACHE_MASK 0x00001000
707 #define ARM_VIRTUAL_IVR_BASE_00000000 0x00000000
708 #define ARM_VIRTUAL_IVR_BASE_FFFF0000 0x00002000
709 #define ARM_CONTROL_SBZ_MASK 0x00001FFF
710
711 /*
712 * SA-1100 Translation Table Base Bit Masks
713 */
714 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
715
716 /*
717 * SA-1100 Domain Access Control Bit Masks
718 */
719 #define ARM_DOMAIN_0_MASK 0x00000003
720 #define ARM_DOMAIN_1_MASK 0x0000000C
721 #define ARM_DOMAIN_2_MASK 0x00000030
722 #define ARM_DOMAIN_3_MASK 0x000000C0
723 #define ARM_DOMAIN_4_MASK 0x00000300
724 #define ARM_DOMAIN_5_MASK 0x00000C00
725 #define ARM_DOMAIN_6_MASK 0x00003000
726 #define ARM_DOMAIN_7_MASK 0x0000C000
727 #define ARM_DOMAIN_8_MASK 0x00030000
728 #define ARM_DOMAIN_9_MASK 0x000C0000
729 #define ARM_DOMAIN_10_MASK 0x00300000
730 #define ARM_DOMAIN_11_MASK 0x00C00000
731 #define ARM_DOMAIN_12_MASK 0x03000000
732 #define ARM_DOMAIN_13_MASK 0x0C000000
733 #define ARM_DOMAIN_14_MASK 0x30000000
734 #define ARM_DOMAIN_15_MASK 0xC0000000
735
736 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num))
737 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num))
738 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num))
739
740 /*
741 * SA-1100 Fault Status Bit Masks
742 */
743 #define ARM_FAULT_STATUS_MASK 0x0000000F
744 #define ARM_DOMAIN_MASK 0x000000F0
745 #define ARM_DATA_BREAKPOINT_MASK 0x00000200
746
747 /*
748 * SA-1100 Cache Control Operations Definitions
749 */
750 #ifdef __ASSEMBLER__
751 # define ARM_FLUSH_CACHE_INST_DATA_OPCODE 0x0
752 # define ARM_FLUSH_CACHE_INST_DATA_RM c7
753 # define ARM_FLUSH_CACHE_INST_OPCODE 0x0
754 # define ARM_FLUSH_CACHE_INST_RM c5
755 # define ARM_FLUSH_CACHE_DATA_OPCODE 0x0
756 # define ARM_FLUSH_CACHE_DATA_RM c6
757 # define ARM_FLUSH_CACHE_DATA_SINGLE_OPCODE 0x1
758 # define ARM_FLUSH_CACHE_DATA_SINGLE_RM c6
759 # define ARM_CLEAN_CACHE_DATA_ENTRY_OPCODE 0x1
760 # define ARM_CLEAN_CACHE_DATA_ENTRY_RM c10
761 # define ARM_DRAIN_CACHE_WRITE_BUFFER_OPCODE 0x4
762 # define ARM_DRAIN_CACHE_WRITE_BUFFER_RM c10
763 #else /* __ASSEMBLER__ */
764 # define ARM_FLUSH_CACHE_INST_DATA_OPCODE "0x0"
765 # define ARM_FLUSH_CACHE_INST_DATA_RM "c7"
766 # define ARM_FLUSH_CACHE_INST_OPCODE "0x0"
767 # define ARM_FLUSH_CACHE_INST_RM "c5"
768 # define ARM_FLUSH_CACHE_DATA_OPCODE "0x0"
769 # define ARM_FLUSH_CACHE_DATA_RM "c6"
770 # define ARM_FLUSH_CACHE_DATA_SINGLE_OPCODE "0x1"
771 # define ARM_FLUSH_CACHE_DATA_SINGLE_RM "c6"
772 # define ARM_CLEAN_CACHE_DATA_ENTRY_OPCODE "0x1"
773 # define ARM_CLEAN_CACHE_DATA_ENTRY_RM "c10"
774 # define ARM_DRAIN_CACHE_WRITE_BUFFER_OPCODE "0x4"
775 # define ARM_DRAIN_CACHE_WRITE_BUFFER_RM "c10"
776 #endif /* __ASSEMBLER__ */
777
778 /*
779 * SA-1100 TLB Operations Definitions
780 */
781 #ifdef __ASSEMBLER__
782 # define ARM_FLUSH_INST_DATA_TLB_OPCODE 0x0
783 # define ARM_FLUSH_INST_DATA_TLB_RM c7
784 # define ARM_FLUSH_INST_TLB_OPCODE 0x0
785 # define ARM_FLUSH_INST_TLB_RM c5
786 # define ARM_FLUSH_DATA_TLB_OPCODE 0x0
787 # define ARM_FLUSH_DATA_TLB_RM c6
788 # define ARM_FLUSH_DATA_ENTRY_TLB_OPCODE 0x1
789 # define ARM_FLUSH_DATA_ENTRY_TLB_RM c6
790 #else /* __ASSEMBLER__ */
791 # define ARM_FLUSH_INST_DATA_TLB_OPCODE "0x0"
792 # define ARM_FLUSH_INST_DATA_TLB_RM "c7"
793 # define ARM_FLUSH_INST_TLB_OPCODE "0x0"
794 # define ARM_FLUSH_INST_TLB_RM "c5"
795 # define ARM_FLUSH_DATA_TLB_OPCODE "0x0"
796 # define ARM_FLUSH_DATA_TLB_RM "c6"
797 # define ARM_FLUSH_DATA_ENTRY_TLB_OPCODE "0x1"
798 # define ARM_FLUSH_DATA_ENTRY_TLB_RM "c6"
799 #endif /* __ASSEMBLER__ */
800
801 /*
802 * SA-1100 Read-Buffer Operations Definitions
803 */
804 #ifdef __ASSEMBLER__
805 # define ARM_FLUSH_ALL_BUFFERS_OPCODE 0x0
806 # define ARM_FLUSH_ALL_BUFFERS_RM c0
807 # define ARM_FLUSH_BUFFER_0_OPCODE 0x1
808 # define ARM_FLUSH_BUFFER_0_RM c0
809 # define ARM_FLUSH_BUFFER_1_OPCODE 0x1
810 # define ARM_FLUSH_BUFFER_1_RM c1
811 # define ARM_FLUSH_BUFFER_2_OPCODE 0x1
812 # define ARM_FLUSH_BUFFER_2_RM c2
813 # define ARM_FLUSH_BUFFER_3_OPCODE 0x1
814 # define ARM_FLUSH_BUFFER_3_RM c3
815 # define ARM_LOAD_BUFFER_0_1_WORD_OPCODE 0x2
816 # define ARM_LOAD_BUFFER_0_1_WORD_RM c0
817 # define ARM_LOAD_BUFFER_0_4_WORD_OPCODE 0x2
818 # define ARM_LOAD_BUFFER_0_4_WORD_RM c4
819 # define ARM_LOAD_BUFFER_0_8_WORD_OPCODE 0x2
820 # define ARM_LOAD_BUFFER_0_8_WORD_RM c8
821 # define ARM_LOAD_BUFFER_1_1_WORD_OPCODE 0x2
822 # define ARM_LOAD_BUFFER_1_1_WORD_RM c1
823 # define ARM_LOAD_BUFFER_1_4_WORD_OPCODE 0x2
824 # define ARM_LOAD_BUFFER_1_4_WORD_RM c5
825 # define ARM_LOAD_BUFFER_1_8_WORD_OPCODE 0x2
826 # define ARM_LOAD_BUFFER_1_8_WORD_RM c9
827 # define ARM_LOAD_BUFFER_2_1_WORD_OPCODE 0x2
828 # define ARM_LOAD_BUFFER_2_1_WORD_RM c2
829 # define ARM_LOAD_BUFFER_2_4_WORD_OPCODE 0x2
830 # define ARM_LOAD_BUFFER_2_4_WORD_RM c6
831 # define ARM_LOAD_BUFFER_2_8_WORD_OPCODE 0x2
832 # define ARM_LOAD_BUFFER_2_8_WORD_RM cA
833 # define ARM_LOAD_BUFFER_3_1_WORD_OPCODE 0x2
834 # define ARM_LOAD_BUFFER_3_1_WORD_RM c3
835 # define ARM_LOAD_BUFFER_3_4_WORD_OPCODE 0x2
836 # define ARM_LOAD_BUFFER_3_4_WORD_RM c7
837 # define ARM_LOAD_BUFFER_3_8_WORD_OPCODE 0x2
838 # define ARM_LOAD_BUFFER_3_8_WORD_RM cB
839 # define ARM_DISABLE_USER_MCR_ACCESS_OPCODE 0x4
840 # define ARM_DISABLE_USER_MCR_ACCESS_RM c0
841 # define ARM_ENABLE_USER_MCR_ACCESS_OPCODE 0x5
842 # define ARM_ENABLE_USER_MCR_ACCESS_RM c0
843 #else /* __ASSEMBLER__ */
844 # define ARM_FLUSH_ALL_BUFFERS_OPCODE "0x0"
845 # define ARM_FLUSH_ALL_BUFFERS_RM "c0"
846 # define ARM_FLUSH_BUFFER_0_OPCODE "0x1"
847 # define ARM_FLUSH_BUFFER_0_RM "c0"
848 # define ARM_FLUSH_BUFFER_1_OPCODE "0x1"
849 # define ARM_FLUSH_BUFFER_1_RM "c1"
850 # define ARM_FLUSH_BUFFER_2_OPCODE "0x1"
851 # define ARM_FLUSH_BUFFER_2_RM "c2"
852 # define ARM_FLUSH_BUFFER_3_OPCODE "0x1"
853 # define ARM_FLUSH_BUFFER_3_RM "c3"
854 # define ARM_LOAD_BUFFER_0_1_WORD_OPCODE "0x2"
855 # define ARM_LOAD_BUFFER_0_1_WORD_RM "c0"
856 # define ARM_LOAD_BUFFER_0_4_WORD_OPCODE "0x2"
857 # define ARM_LOAD_BUFFER_0_4_WORD_RM "c4"
858 # define ARM_LOAD_BUFFER_0_8_WORD_OPCODE "0x2"
859 # define ARM_LOAD_BUFFER_0_8_WORD_RM "c8"
860 # define ARM_LOAD_BUFFER_1_1_WORD_OPCODE "0x2"
861 # define ARM_LOAD_BUFFER_1_1_WORD_RM "c1"
862 # define ARM_LOAD_BUFFER_1_4_WORD_OPCODE "0x2"
863 # define ARM_LOAD_BUFFER_1_4_WORD_RM "c5"
864 # define ARM_LOAD_BUFFER_1_8_WORD_OPCODE "0x2"
865 # define ARM_LOAD_BUFFER_1_8_WORD_RM "c9"
866 # define ARM_LOAD_BUFFER_2_1_WORD_OPCODE "0x2"
867 # define ARM_LOAD_BUFFER_2_1_WORD_RM "c2"
868 # define ARM_LOAD_BUFFER_2_4_WORD_OPCODE "0x2"
869 # define ARM_LOAD_BUFFER_2_4_WORD_RM "c6"
870 # define ARM_LOAD_BUFFER_2_8_WORD_OPCODE "0x2"
871 # define ARM_LOAD_BUFFER_2_8_WORD_RM "cA"
872 # define ARM_LOAD_BUFFER_3_1_WORD_OPCODE "0x2"
873 # define ARM_LOAD_BUFFER_3_1_WORD_RM "c3"
874 # define ARM_LOAD_BUFFER_3_4_WORD_OPCODE "0x2"
875 # define ARM_LOAD_BUFFER_3_4_WORD_RM "c7"
876 # define ARM_LOAD_BUFFER_3_8_WORD_OPCODE "0x2"
877 # define ARM_LOAD_BUFFER_3_8_WORD_RM "cB"
878 # define ARM_DISABLE_USER_MCR_ACCESS_OPCODE "0x4"
879 # define ARM_DISABLE_USER_MCR_ACCESS_RM "c0"
880 # define ARM_ENABLE_USER_MCR_ACCESS_OPCODE "0x5"
881 # define ARM_ENABLE_USER_MCR_ACCESS_RM "c0"
882 #endif /* __ASSEMBLER__ */
883
884 /*
885 * ARM(R) First Level Descriptor Format Definitions
886 */
887 #ifndef __ASSEMBLER__
888 struct ARM_MMU_FIRST_LEVEL_FAULT {
889 int id : 2;
890 int sbz : 30;
891 };
892 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
893
894 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
895 int id : 2;
896 int imp : 2;
897 int domain : 4;
898 int sbz : 1;
899 int base_address : 23;
900 };
901 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
902
903 struct ARM_MMU_FIRST_LEVEL_SECTION {
904 int id : 2;
905 int b : 1;
906 int c : 1;
907 int imp : 1;
908 int domain : 4;
909 int sbz0 : 1;
910 int ap : 2;
911 int sbz1 : 8;
912 int base_address : 12;
913 };
914 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
915
916 struct ARM_MMU_FIRST_LEVEL_RESERVED {
917 int id : 2;
918 int sbz : 30;
919 };
920 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
921
922 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
923 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
924 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, cacheable, bufferable, perm) \
925 { \
926 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
927 \
928 desc.word = 0; \
929 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
930 desc.section.domain = 0; \
931 desc.section.c = (cacheable); \
932 desc.section.b = (bufferable); \
933 desc.section.ap = (perm); \
934 desc.section.base_address = (actual_base); \
935 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) = desc.word; \
936 }
937
938 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
939 unsigned long word;
940 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
941 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
942 struct ARM_MMU_FIRST_LEVEL_SECTION section;
943 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
944 };
945
946 #endif /* __ASSEMBLER__ */
947
948 #define ARM_UNCACHEABLE 0
949 #define ARM_CACHEABLE 1
950 #define ARM_UNBUFFERABLE 0
951 #define ARM_BUFFERABLE 1
952
953 #define ARM_ACCESS_PERM_NONE_NONE 0
954 #define ARM_ACCESS_PERM_RO_NONE 0
955 #define ARM_ACCESS_PERM_RO_RO 0
956 #define ARM_ACCESS_PERM_RW_NONE 1
957 #define ARM_ACCESS_PERM_RW_RO 2
958 #define ARM_ACCESS_PERM_RW_RW 3
959
960 #define ARM_SECTION_SIZE SZ_1M
961 #define ARM_SMALL_PAGE_SIZE SZ_4K
962 #define ARM_LARGE_PAGE_SIZE SZ_64K
963
964 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE SZ_16K
965 #define ARM_SECOND_LEVEL_PAGE_TABLE_SIZE SZ_1K
966
967 #endif /* MMU */
968
969 #endif // __ARM_CPU_H__