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comparison packages/hal/mn10300/arch/current/include/hal_arch.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents bf00f99aec69
children c37d3a9e1b28
comparison
equal deleted inserted replaced
75:41bf073c0c32 76:435cced73e2f
45 45
46 #include <pkgconf/hal.h> 46 #include <pkgconf/hal.h>
47 #include <cyg/infra/cyg_type.h> 47 #include <cyg/infra/cyg_type.h>
48 48
49 #include <cyg/hal/var_arch.h> 49 #include <cyg/hal/var_arch.h>
50
51 //--------------------------------------------------------------------------
52 // Processor saved states:
53
54 typedef struct HAL_SavedRegisters
55 {
56 // These are common to all saved states and are in the order
57 // stored and loaded by the movm instruction.
58 CYG_ADDRWORD vector; /* Vector number/dummy */
59 CYG_ADDRWORD lar; /* Loop address register */
60 CYG_ADDRWORD lir; /* Loop instruction register */
61 CYG_ADDRWORD mdr; /* Multiply/Divide register */
62 CYG_ADDRWORD a1;
63 CYG_ADDRWORD a0;
64 CYG_ADDRWORD d1;
65 CYG_ADDRWORD d0;
66 CYG_ADDRWORD a3;
67 CYG_ADDRWORD a2;
68 CYG_ADDRWORD d3;
69 CYG_ADDRWORD d2;
70
71 /* On interrupts the PC and PSW are pushed automatically by the */
72 /* CPU and SP is pushed for debugging reasons. On a thread switch */
73 /* the saved context is made to look the same. */
74
75 CYG_ADDRWORD sp; /* Saved copy of SP in some states */
76 CYG_ADDRWORD psw; /* Status word */
77 CYG_ADDRWORD pc; /* Program Counter */
78
79 } HAL_SavedRegisters;
80 50
81 //-------------------------------------------------------------------------- 51 //--------------------------------------------------------------------------
82 // Exception handling function. 52 // Exception handling function.
83 // This function is defined by the kernel according to this prototype. It is 53 // This function is defined by the kernel according to this prototype. It is
84 // invoked from the HAL to deal with any CPU exceptions that the HAL does 54 // invoked from the HAL to deal with any CPU exceptions that the HAL does