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comparison packages/hal/mips/arch/current/include/hal_cache.h @ 2:443894e2e912 ecos-v1_2_1-release

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Block commit of eCos version 1.2.1
author jlarmour
date Tue, 11 May 1999 12:24:34 +0000
parents 3111d98ba7b3
children d376b777e2ce
comparison
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1:72f549f0d891 2:443894e2e912
1 #ifndef CYGONCE_HAL_CACHE_H 1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H 2 #define CYGONCE_HAL_CACHE_H
3 3
4 //============================================================================= 4 //=============================================================================
5 // 5 //
6 // hal_cache.h 6 // hal_cache.h
7 // 7 //
8 // HAL cache control API 8 // HAL cache control API
9 // 9 //
10 //============================================================================= 10 //=============================================================================
11 //####COPYRIGHTBEGIN#### 11 //####COPYRIGHTBEGIN####
12 // 12 //
13 // ------------------------------------------- 13 // -------------------------------------------
23 // 23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released 24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998. 25 // September 30, 1998.
26 // 26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created 27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
29 // ------------------------------------------- 29 // -------------------------------------------
30 // 30 //
31 //####COPYRIGHTEND#### 31 //####COPYRIGHTEND####
32 //============================================================================= 32 //=============================================================================
33 //#####DESCRIPTIONBEGIN#### 33 //#####DESCRIPTIONBEGIN####
34 // 34 //
35 // Author(s): nickg 35 // Author(s): nickg
36 // Contributors: nickg 36 // Contributors: nickg
37 // Date: 1998-02-17 37 // Date: 1998-02-17
38 // Purpose: Cache control API 38 // Purpose: Cache control API
39 // Description: The macros defined here provide the HAL APIs for handling 39 // Description: The macros defined here provide the HAL APIs for handling
40 // cache control operations. 40 // cache control operations.
41 // Usage: 41 // Usage:
42 // #include <cyg/hal/hal_cache.h> 42 // #include <cyg/hal/hal_cache.h>
43 // ... 43 // ...
44 // 44 //
45 // 45 //
46 //####DESCRIPTIONEND#### 46 //####DESCRIPTIONEND####
47 // 47 //
48 //============================================================================= 48 //=============================================================================
49 49
50 #include <pkgconf/hal.h>
50 #include <cyg/infra/cyg_type.h> 51 #include <cyg/infra/cyg_type.h>
51 52
52 //============================================================================= 53 //=============================================================================
53 // MIPS simulator 54 // MIPS simulator
54 55
99 //#define HAL_DCACHE_LOCK(_base_, _size_) 100 //#define HAL_DCACHE_LOCK(_base_, _size_)
100 101
101 // Undo a previous lock operation 102 // Undo a previous lock operation
102 //#define HAL_DCACHE_UNLOCK(_base_, _size_) 103 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
103 104
105 // Unlock entire cache
106 //#define HAL_DCACHE_UNLOCK_ALL()
107
104 //----------------------------------------------------------------------------- 108 //-----------------------------------------------------------------------------
105 // Data cache line control 109 // Data cache line control
106 110
107 // Allocate cache lines for the given address range without reading its 111 // Allocate cache lines for the given address range without reading its
108 // contents from memory. 112 // contents from memory.
151 // and then lock the cache so that it stays there. 155 // and then lock the cache so that it stays there.
152 //#define HAL_ICACHE_LOCK(_base_, _size_) 156 //#define HAL_ICACHE_LOCK(_base_, _size_)
153 157
154 // Undo a previous lock operation 158 // Undo a previous lock operation
155 //#define HAL_ICACHE_UNLOCK(_base_, _size_) 159 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
160
161 // Unlock entire cache
162 //#define HAL_ICACHE_UNLOCK_ALL()
156 163
157 //----------------------------------------------------------------------------- 164 //-----------------------------------------------------------------------------
158 // Instruction cache line control 165 // Instruction cache line control
159 166
160 // Invalidate cache lines in the given range without writing to memory. 167 // Invalidate cache lines in the given range without writing to memory.
201 } 208 }
202 209
203 // Disable the data cache 210 // Disable the data cache
204 #define HAL_DCACHE_DISABLE() \ 211 #define HAL_DCACHE_DISABLE() \
205 { \ 212 { \
206 asm volatile ("mfc0 $2,$3;" \ 213 asm volatile ("mfc0 $2,$3;" \
207 "la $3,0xFFFFFFEF;" \ 214 "la $3,0xFFFFFFEF;" \
208 "and $2,$2,$3;" \ 215 "and $2,$2,$3;" \
209 "mtc0 $2,$3;" \ 216 "mtc0 $2,$3;" \
210 : \ 217 : \
211 : \ 218 : \
212 : "$2", "$3" \ 219 : "$2", "$3" \
213 ); \ 220 ); \
214 \ 221 \
215 } 222 }
216 223
217 // Invalidate the entire cache 224 // Invalidate the entire cache
218 // We do this by reading a word from each line to invalidate the current 225 // The TX39 only has hit-invalidate on the DCACHE, not
219 // cache contents. 226 // index-invalidate, so we cannot just empty the cache out without
227 // knowing what is in it. This is annoying. So, the best we can do is
228 // fill the cache with data that is unlikely to be there
229 // otherwise. Hence we read bytes from the ROM space since this is
230 // most likely to be code, and will not get out of sync even if it is not.
220 #define HAL_DCACHE_INVALIDATE_ALL() \ 231 #define HAL_DCACHE_INVALIDATE_ALL() \
221 { \ 232 { \
222 extern char __ram_data_start; \ 233 CYG_BYTE volatile *addr = (CYG_BYTE *)(0x9fc00000); \
223 CYG_WORD *addr = (CYG_WORD *)&__ram_data_start; \ 234 CYG_BYTE volatile tmp = 0; \
224 CYG_WORD sum = 0; \
225 int i; \ 235 int i; \
226 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \ 236 for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
227 { \ 237 { \
228 sum += addr[i]; \ 238 tmp = addr[i]; \
229 } \ 239 } \
230 } 240 }
231 241
232 // Synchronize the contents of the cache with memory. 242 // Synchronize the contents of the cache with memory.
233 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL() 243 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
264 : \ 274 : \
265 : \ 275 : \
266 : "$2", "$3" \ 276 : "$2", "$3" \
267 ); \ 277 ); \
268 } 278 }
279
280 // Unlock entire cache
281 #define HAL_DCACHE_UNLOCK_ALL()
269 282
270 //----------------------------------------------------------------------------- 283 //-----------------------------------------------------------------------------
271 // Data cache line control 284 // Data cache line control
272 285
273 // Allocate cache lines for the given address range without reading its 286 // Allocate cache lines for the given address range without reading its
284 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 297 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
285 register CYG_WORD _size_ = (_asize_); \ 298 register CYG_WORD _size_ = (_asize_); \
286 HAL_DCACHE_DISABLE(); \ 299 HAL_DCACHE_DISABLE(); \
287 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ 300 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
288 { \ 301 { \
289 asm volatile ("cache 17,0(%0)" : : "r"(addr) ); \ 302 asm volatile ("cache 17,0(%0)" : : "r"(_addr_) ); \
290 } \ 303 } \
291 HAL_DCACHE_ENABLE(); \ 304 HAL_DCACHE_ENABLE(); \
292 } 305 }
293 306
294 // Write dirty cache lines to memory for the given address range. 307 // Write dirty cache lines to memory for the given address range.
336 } 349 }
337 350
338 // Invalidate the entire cache 351 // Invalidate the entire cache
339 #define HAL_ICACHE_INVALIDATE_ALL() \ 352 #define HAL_ICACHE_INVALIDATE_ALL() \
340 { \ 353 { \
341 register CYG_ADDRESS addr; \ 354 register CYG_ADDRESS _addr_; \
342 HAL_ICACHE_DISABLE(); \ 355 HAL_ICACHE_DISABLE(); \
343 for( addr = 0; addr < HAL_ICACHE_SIZE; addr += HAL_ICACHE_LINE_SIZE ) \ 356 for( _addr_ = 0; _addr_ < HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
344 { \ 357 { \
345 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \ 358 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
346 } \ 359 } \
347 HAL_ICACHE_ENABLE(); \ 360 HAL_ICACHE_ENABLE(); \
348 } 361 }
349 362
350 // Synchronize the contents of the cache with memory. 363 // Synchronize the contents of the cache with memory.
376 : \ 389 : \
377 : \ 390 : \
378 : "$2", "$3" \ 391 : "$2", "$3" \
379 ); \ 392 ); \
380 } 393 }
394
395 // Unlock entire cache
396 #define HAL_ICACHE_UNLOCK_ALL()
381 397
382 //----------------------------------------------------------------------------- 398 //-----------------------------------------------------------------------------
383 // Instruction cache line control 399 // Instruction cache line control
384 400
385 // Invalidate cache lines in the given range without writing to memory. 401 // Invalidate cache lines in the given range without writing to memory.
388 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ 404 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
389 register CYG_WORD _size_ = (_asize_); \ 405 register CYG_WORD _size_ = (_asize_); \
390 HAL_ICACHE_DISABLE(); \ 406 HAL_ICACHE_DISABLE(); \
391 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ 407 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
392 { \ 408 { \
393 asm volatile ("cache 0,0(%0)" : : "r"(addr) ); \ 409 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
394 } \ 410 } \
395 HAL_ICACHE_ENABLE(); \ 411 HAL_ICACHE_ENABLE(); \
396 } 412 }
397 413
398 #endif 414 #endif
399 415
400 //----------------------------------------------------------------------------- 416 //-----------------------------------------------------------------------------
417 // Check that a supported configuration has actually defined some macros.
418
419 #ifndef HAL_DCACHE_ENABLE
420
421 #error Unsupported MIPS configuration
422
423 #endif
424
425 //-----------------------------------------------------------------------------
401 #endif // ifndef CYGONCE_HAL_CACHE_H 426 #endif // ifndef CYGONCE_HAL_CACHE_H
402 // End of hal_cache.h 427 // End of hal_cache.h