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comparison packages/hal/powerpc/arch/current/src/ppc_860.h @ 2:443894e2e912 ecos-v1_2_1-release

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Block commit of eCos version 1.2.1
author jlarmour
date Tue, 11 May 1999 12:24:34 +0000
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children 4cc3eff958ab
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1:72f549f0d891 2:443894e2e912
1 #ifndef CYGONCE_PPC_860_H
2 #define CYGONCE_PPC_860_H
3
4 //=============================================================================
5 //####UNSUPPORTEDBEGIN####
6 //
7 // -------------------------------------------
8 // This source file has been contributed to eCos/Cygnus. It may have been
9 // changed slightly to provide an interface consistent with those of other
10 // files.
11 //
12 // The functionality and contents of this file is supplied "AS IS"
13 // without any form of support and will not necessarily be kept up
14 // to date by Cygnus.
15 //
16 // The style of programming used in this file may not comply with the
17 // eCos programming guidelines. Please do not use as a base for other
18 // files.
19 //
20 // All inquiries about this file, or the functionality provided by it,
21 // should be directed to the 'ecos-discuss' mailing list (see
22 // http://sourceware.cygnus.com/ecos/intouch.html for details).
23 //
24 // Contributed by: Kevin Hester <khester@opticworks.com>
25 // Maintained by: <Unmaintained>
26 // See also:
27 // Motorola's "Example Software Initializing the SMC as a UART" package
28 // (smc2.zip) at:
29 // http://www.mot.com/SPS/RISC/netcomm/tools/index.html#MPC860_table
30 // -------------------------------------------
31 //
32 //####UNSUPPORTEDEND####
33 //=============================================================================
34
35 #include <cyg/infra/cyg_type.h>
36
37 /******************************************************************************
38 *
39 * Definitions of Parameter RAM entries for each peripheral and mode
40 *
41 ******************************************************************************/
42
43 /*---------------------------------------------------------------------------*/
44 /* HDLC parameter RAM (SCC) */
45 /*---------------------------------------------------------------------------*/
46
47 struct hdlc_pram
48
49 {
50
51 /*-------------------*/
52 /* SCC parameter RAM */
53 /*-------------------*/
54
55 cyg_uint16 rbase; /* RX BD base address */
56 cyg_uint16 tbase; /* TX BD base address */
57 cyg_uint8 rfcr; /* Rx function code */
58 cyg_uint8 tfcr; /* Tx function code */
59 cyg_uint16 mrblr; /* Rx buffer length */
60 cyg_uint32 rstate; /* Rx internal state */
61 cyg_uint32 rptr; /* Rx internal data pointer */
62 cyg_uint16 rbptr; /* rb BD Pointer */
63 cyg_uint16 rcount; /* Rx internal byte count */
64 cyg_uint32 rtemp; /* Rx temp */
65 cyg_uint32 tstate; /* Tx internal state */
66 cyg_uint32 tptr; /* Tx internal data pointer */
67 cyg_uint16 tbptr; /* Tx BD pointer */
68 cyg_uint16 tcount; /* Tx byte count */
69 cyg_uint32 ttemp; /* Tx temp */
70 cyg_uint32 rcrc; /* temp receive CRC */
71 cyg_uint32 tcrc; /* temp transmit CRC */
72
73 /*-----------------------------*/
74 /* HDLC specific parameter RAM */
75 /*-----------------------------*/
76
77 cyg_uint8 RESERVED1[4]; /* Reserved area */
78 cyg_uint32 c_mask; /* CRC constant */
79 cyg_uint32 c_pres; /* CRC preset */
80 cyg_uint16 disfc; /* discarded frame counter */
81 cyg_uint16 crcec; /* CRC error counter */
82 cyg_uint16 abtsc; /* abort sequence counter */
83 cyg_uint16 nmarc; /* nonmatching address rx cnt */
84 cyg_uint16 retrc; /* frame retransmission cnt */
85 cyg_uint16 mflr; /* maximum frame length reg */
86 cyg_uint16 max_cnt; /* maximum length counter */
87 cyg_uint16 rfthr; /* received frames threshold */
88 cyg_uint16 rfcnt; /* received frames count */
89 cyg_uint16 hmask; /* user defined frm addr mask */
90 cyg_uint16 haddr1; /* user defined frm address 1 */
91 cyg_uint16 haddr2; /* user defined frm address 2 */
92 cyg_uint16 haddr3; /* user defined frm address 3 */
93 cyg_uint16 haddr4; /* user defined frm address 4 */
94 cyg_uint16 tmp; /* temp */
95 cyg_uint16 tmp_mb; /* temp */
96 };
97
98
99 /*-------------------------------------------------------------------------*/
100 /* ASYNC HDLC parameter RAM (SCC) */
101 /*-------------------------------------------------------------------------*/
102
103 struct async_hdlc_pram
104
105 {
106
107 /*-------------------*/
108 /* SCC parameter RAM */
109 /*-------------------*/
110
111 cyg_uint16 rbase; /* RX BD base address */
112 cyg_uint16 tbase; /* TX BD base address */
113 cyg_uint8 rfcr; /* Rx function code */
114 cyg_uint8 tfcr; /* Tx function code */
115 cyg_uint16 mrblr; /* Rx buffer length */
116 cyg_uint32 rstate; /* Rx internal state */
117 cyg_uint32 rptr; /* Rx internal data pointer */
118 cyg_uint16 rbptr; /* rb BD Pointer */
119 cyg_uint16 rcount; /* Rx internal byte count */
120 cyg_uint32 rtemp; /* Rx temp */
121 cyg_uint32 tstate; /* Tx internal state */
122 cyg_uint32 tptr; /* Tx internal data pointer */
123 cyg_uint16 tbptr; /* Tx BD pointer */
124 cyg_uint16 tcount; /* Tx byte count */
125 cyg_uint32 ttemp; /* Tx temp */
126 cyg_uint32 rcrc; /* temp receive CRC */
127 cyg_uint32 tcrc; /* temp transmit CRC */
128
129 /*-----------------------------------*/
130 /* ASYNC HDLC specific parameter RAM */
131 /*-----------------------------------*/
132
133 cyg_uint8 RESERVED2[4]; /* Reserved area */
134 cyg_uint32 c_mask; /* CRC constant */
135 cyg_uint32 c_pres; /* CRC preset */
136 cyg_uint16 bof; /* begining of flag character */
137 cyg_uint16 eof; /* end of flag character */
138 cyg_uint16 esc; /* control escape character */
139 cyg_uint8 RESERVED3[4]; /* Reserved area */
140 cyg_uint16 zero; /* zero */
141 cyg_uint8 RESERVED4[2]; /* Reserved area */
142 cyg_uint16 rfthr; /* received frames threshold */
143 cyg_uint8 RESERVED5[4]; /* Reserved area */
144 cyg_uint32 txctl_tbl; /* Tx ctl char mapping table */
145 cyg_uint32 rxctl_tbl; /* Rx ctl char mapping table */
146 cyg_uint16 nof; /* Number of opening flags */
147 };
148
149
150 /*--------------------------------------------------------------------------*/
151 /* UART parameter RAM (SCC) */
152 /*--------------------------------------------------------------------------*/
153
154 /*----------------------------------------*/
155 /* bits in uart control characters table */
156 /*----------------------------------------*/
157
158 #define CC_INVALID 0x8000 /* control character is valid */
159 #define CC_REJ 0x4000 /* don't store char in buffer */
160 #define CC_CHAR 0x00ff /* control character */
161
162 /*------*/
163 /* UART */
164 /*------*/
165
166 struct uart_pram
167
168 {
169 /*-------------------*/
170 /* SCC parameter RAM */
171 /*-------------------*/
172
173 cyg_uint16 rbase; /* RX BD base address */
174 cyg_uint16 tbase; /* TX BD base address */
175 cyg_uint8 rfcr; /* Rx function code */
176 cyg_uint8 tfcr; /* Tx function code */
177 cyg_uint16 mrblr; /* Rx buffer length */
178 cyg_uint32 rstate; /* Rx internal state */
179 cyg_uint32 rptr; /* Rx internal data pointer */
180 cyg_uint16 rbptr; /* rb BD Pointer */
181 cyg_uint16 rcount; /* Rx internal byte count */
182 cyg_uint32 rx_temp; /* Rx temp */
183 cyg_uint32 tstate; /* Tx internal state */
184 cyg_uint32 tptr; /* Tx internal data pointer */
185 cyg_uint16 tbptr; /* Tx BD pointer */
186 cyg_uint16 tcount; /* Tx byte count */
187 cyg_uint32 ttemp; /* Tx temp */
188 cyg_uint32 rcrc; /* temp receive CRC */
189 cyg_uint32 tcrc; /* temp transmit CRC */
190
191 /*------------------------------*/
192 /* UART specific parameter RAM */
193 /*------------------------------*/
194
195 cyg_uint8 RESERVED6[8]; /* Reserved area */
196 cyg_uint16 max_idl; /* maximum idle characters */
197 cyg_uint16 idlc; /* rx idle counter (internal) */
198 cyg_uint16 brkcr; /* break count register */
199
200 cyg_uint16 parec; /* Rx parity error counter */
201 cyg_uint16 frmec; /* Rx framing error counter */
202 cyg_uint16 nosec; /* Rx noise counter */
203 cyg_uint16 brkec; /* Rx break character counter */
204 cyg_uint16 brkln; /* Reaceive break length */
205
206 cyg_uint16 uaddr1; /* address character 1 */
207 cyg_uint16 uaddr2; /* address character 2 */
208 cyg_uint16 rtemp; /* temp storage */
209 cyg_uint16 toseq; /* Tx out of sequence char */
210 cyg_uint16 cc[8]; /* Rx control characters */
211 cyg_uint16 rccm; /* Rx control char mask */
212 cyg_uint16 rccr; /* Rx control char register */
213 cyg_uint16 rlbc; /* Receive last break char */
214 };
215
216
217 /*---------------------------------------------------------------------------
218 * BISYNC parameter RAM (SCC)
219 *--------------------------------------------------------------------------*/
220
221 struct bisync_pram
222
223 {
224 /*-------------------*/
225 /* SCC parameter RAM */
226 /*-------------------*/
227
228 cyg_uint16 rbase; /* RX BD base address */
229 cyg_uint16 tbase; /* TX BD base address */
230 cyg_uint8 rfcr; /* Rx function code */
231 cyg_uint8 tfcr; /* Tx function code */
232 cyg_uint16 mrblr; /* Rx buffer length */
233 cyg_uint32 rstate; /* Rx internal state */
234 cyg_uint32 rptr; /* Rx internal data pointer */
235 cyg_uint16 rbptr; /* rb BD Pointer */
236 cyg_uint16 rcount; /* Rx internal byte count */
237 cyg_uint32 rtemp; /* Rx temp */
238 cyg_uint32 tstate; /* Tx internal state */
239 cyg_uint32 tptr; /* Tx internal data pointer */
240 cyg_uint16 tbptr; /* Tx BD pointer */
241 cyg_uint16 tcount; /* Tx byte count */
242 cyg_uint32 ttemp; /* Tx temp */
243 cyg_uint32 rcrc; /* temp receive CRC */
244 cyg_uint32 tcrc; /* temp transmit CRC */
245
246 /*--------------------------------*/
247 /* BISYNC specific parameter RAM */
248 /*--------------------------------*/
249
250 cyg_uint8 RESERVED7[4]; /* Reserved area */
251 cyg_uint32 crcc; /* CRC Constant Temp Value */
252 cyg_uint16 prcrc; /* Preset Receiver CRC-16/LRC */
253 cyg_uint16 ptcrc; /* Preset Transmitter CRC-16/LRC */
254 cyg_uint16 parec; /* Receive Parity Error Counter */
255 cyg_uint16 bsync; /* BISYNC SYNC Character */
256 cyg_uint16 bdle; /* BISYNC DLE Character */
257 cyg_uint16 cc[8]; /* Rx control characters */
258 cyg_uint16 rccm; /* Receive Control Character Mask */
259 };
260
261
262 /*-------------------------------------------------------------------------*/
263 /* Transparent mode parameter RAM (SCC) */
264 /*-------------------------------------------------------------------------*/
265
266 struct transparent_pram
267
268 {
269 /*--------------------*/
270 /* SCC parameter RAM */
271 /*--------------------*/
272
273 cyg_uint16 rbase; /* RX BD base address */
274 cyg_uint16 tbase; /* TX BD base address */
275 cyg_uint8 rfcr; /* Rx function code */
276 cyg_uint8 tfcr; /* Tx function code */
277 cyg_uint16 mrblr; /* Rx buffer length */
278 cyg_uint32 rstate; /* Rx internal state */
279 cyg_uint32 rptr; /* Rx internal data pointer */
280 cyg_uint16 rbptr; /* rb BD Pointer */
281 cyg_uint16 rcount; /* Rx internal byte count */
282 cyg_uint32 rtemp; /* Rx temp */
283 cyg_uint32 tstate; /* Tx internal state */
284 cyg_uint32 tptr; /* Tx internal data pointer */
285 cyg_uint16 tbptr; /* Tx BD pointer */
286 cyg_uint16 tcount; /* Tx byte count */
287 cyg_uint32 ttemp; /* Tx temp */
288 cyg_uint32 rcrc; /* temp receive CRC */
289 cyg_uint32 tcrc; /* temp transmit CRC */
290
291 /*-------------------------------------*/
292 /* TRANSPARENT specific parameter RAM */
293 /*-------------------------------------*/
294
295 cyg_uint32 crc_p; /* CRC Preset */
296 cyg_uint32 crc_c; /* CRC constant */
297 };
298
299
300 /*-------------------------------------------------------------------------*/
301 /* Ethernet parameter RAM (SCC) */
302 /*-------------------------------------------------------------------------*/
303
304 struct ethernet_pram
305
306 {
307 /*--------------------*/
308 /* SCC parameter RAM */
309 /*--------------------*/
310
311 cyg_uint16 rbase; /* RX BD base address */
312 cyg_uint16 tbase; /* TX BD base address */
313 cyg_uint8 rfcr; /* Rx function code */
314 cyg_uint8 tfcr; /* Tx function code */
315 cyg_uint16 mrblr; /* Rx buffer length */
316 cyg_uint32 rstate; /* Rx internal state */
317 cyg_uint32 rptr; /* Rx internal data pointer */
318 cyg_uint16 rbptr; /* rb BD Pointer */
319 cyg_uint16 rcount; /* Rx internal byte count */
320 cyg_uint32 rtemp; /* Rx temp */
321 cyg_uint32 tstate; /* Tx internal state */
322 cyg_uint32 tptr; /* Tx internal data pointer */
323 cyg_uint16 tbptr; /* Tx BD pointer */
324 cyg_uint16 tcount; /* Tx byte count */
325 cyg_uint32 ttemp; /* Tx temp */
326 cyg_uint32 rcrc; /* temp receive CRC */
327 cyg_uint32 tcrc; /* temp transmit CRC */
328
329 /*---------------------------------*/
330 /* ETHERNET specific parameter RAM */
331 /*---------------------------------*/
332
333 cyg_uint32 c_pres; /* preset CRC */
334 cyg_uint32 c_mask; /* constant mask for CRC */
335 cyg_uint32 crcec; /* CRC error counter */
336 cyg_uint32 alec; /* alighnment error counter */
337 cyg_uint32 disfc; /* discard frame counter */
338 cyg_uint16 pads; /* short frame PAD characters */
339 cyg_uint16 ret_lim; /* retry limit threshold */
340 cyg_uint16 ret_cnt; /* retry limit counter */
341 cyg_uint16 mflr; /* maximum frame length reg */
342 cyg_uint16 minflr; /* minimum frame length reg */
343 cyg_uint16 maxd1; /* maximum DMA1 length reg */
344 cyg_uint16 maxd2; /* maximum DMA2 length reg */
345 cyg_uint16 maxd; /* rx max DMA */
346 cyg_uint16 dma_cnt; /* rx dma counter */
347 cyg_uint16 max_b; /* max bd byte count */
348 cyg_uint16 gaddr1; /* group address filter 1 */
349 cyg_uint16 gaddr2; /* group address filter 2 */
350 cyg_uint16 gaddr3; /* group address filter 3 */
351 cyg_uint16 gaddr4; /* group address filter 4 */
352 cyg_uint32 tbuf0_data0; /* save area 0 - current frm */
353 cyg_uint32 tbuf0_data1; /* save area 1 - current frm */
354 cyg_uint32 tbuf0_rba0;
355 cyg_uint32 tbuf0_crc;
356 cyg_uint16 tbuf0_bcnt;
357 cyg_uint16 paddr_h; /* physical address (MSB) */
358 cyg_uint16 paddr_m; /* physical address */
359 cyg_uint16 paddr_l; /* physical address (LSB) */
360 cyg_uint16 p_per; /* persistence */
361 cyg_uint16 rfbd_ptr; /* rx first bd pointer */
362 cyg_uint16 tfbd_ptr; /* tx first bd pointer */
363 cyg_uint16 tlbd_ptr; /* tx last bd pointer */
364 cyg_uint32 tbuf1_data0; /* save area 0 - next frame */
365 cyg_uint32 tbuf1_data1; /* save area 1 - next frame */
366 cyg_uint32 tbuf1_rba0;
367 cyg_uint32 tbuf1_crc;
368 cyg_uint16 tbuf1_bcnt;
369 cyg_uint16 tx_len; /* tx frame length counter */
370 cyg_uint16 iaddr1; /* individual address filter 1*/
371 cyg_uint16 iaddr2; /* individual address filter 2*/
372 cyg_uint16 iaddr3; /* individual address filter 3*/
373 cyg_uint16 iaddr4; /* individual address filter 4*/
374 cyg_uint16 boff_cnt; /* back-off counter */
375 cyg_uint16 taddr_h; /* temp address (MSB) */
376 cyg_uint16 taddr_m; /* temp address */
377 cyg_uint16 taddr_l; /* temp address (LSB) */
378 };
379
380
381 /*------------------------------------------------------------------*/
382 /* QMC definitions */
383 /*------------------------------------------------------------------*/
384
385
386 struct global_qmc_pram {
387
388 cyg_uint32 mcbase; /* Multichannel Base pointer */
389 cyg_uint16 qmcstate; /* Multichannel Controller state */
390 cyg_uint16 mrblr; /* Maximum Receive Buffer Length */
391 cyg_uint16 tx_s_ptr; /* TSATTx Pointer */
392 cyg_uint16 rxptr; /* Current Time slot entry in TSATRx */
393 cyg_uint16 grfthr; /* Global Receive frame threshold */
394 cyg_uint16 grfcnt; /* Global Receive Frame Count */
395 cyg_uint32 intbase; /* Multichannel Base address */
396 cyg_uint32 intptr; /* Pointer to interrupt queue */
397 cyg_uint16 rx_s_ptr; /* TSATRx Pointer */
398 cyg_uint16 txptr; /* Current Time slot entry in TSATTx */
399 cyg_uint32 c_mask32; /* CRC Constant (debb20e3) */
400 cyg_uint16 tsatrx[32]; /* Time Slot Assignment Table Rx */
401 cyg_uint16 tsattx[32]; /* Time Slot Assignment Table Tx */
402 cyg_uint16 c_mask16; /* CRC Constant (f0b8) */
403
404 };
405
406
407 /*------------------------------------------*/
408 /* QMC HDLC channel specific parameter RAM */
409 /*------------------------------------------*/
410
411 struct qmc_hdlc_pram {
412
413 cyg_uint16 tbase; /* Tx Buffer Descriptors Base Address */
414 cyg_uint16 chamr; /* Channel Mode Register */
415 cyg_uint32 tstate; /* Tx Internal State */
416 cyg_uint32 txintr; /* Tx Internal Data Pointer */
417 cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */
418 cyg_uint16 txcntr; /* Tx Internal Byte Count */
419 cyg_uint32 tupack; /* (Tx Temp) */
420 cyg_uint32 zistate; /* Zero Insertion machine state */
421 cyg_uint32 tcrc; /* Temp Transmit CRC */
422 cyg_uint16 intmsk; /* Channel's interrupt mask flags */
423 cyg_uint16 bdflags;
424 cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */
425 cyg_uint16 mflr; /* Max Frame Length Register */
426 cyg_uint32 rstate; /* Rx Internal State */
427 cyg_uint32 rxintr; /* Rx Internal Data Pointer */
428 cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */
429 cyg_uint16 rxbyc; /* Rx Internal Byte Count */
430 cyg_uint32 rpack; /* (Rx Temp) */
431 cyg_uint32 zdstate; /* Zero Deletion machine state */
432 cyg_uint32 rcrc; /* Temp Transmit CRC */
433 cyg_uint16 maxc; /* Max_length counter */
434 cyg_uint16 tmp_mb; /* Temp */
435 };
436
437
438 /*-------------------------------------------------*/
439 /* QMC Transparent channel specific parameter RAM */
440 /*-------------------------------------------------*/
441
442 struct qmc_tran_pram {
443
444 cyg_uint16 tbase; /* Tx Bufer Descriptors Base Address */
445 cyg_uint16 chamr; /* Channel Mode Register */
446 cyg_uint32 tstate; /* Tx Internal State */
447 cyg_uint32 txintr; /* Tx Internal Data Pointer */
448 cyg_uint16 tbptr; /* Tx Buffer Descriptor Pointer */
449 cyg_uint16 txcntr; /* Tx Internal Byte Count */
450 cyg_uint32 tupack; /* (Tx Temp) */
451 cyg_uint32 zistate; /* Zero Insertion machine state */
452 cyg_uint32 RESERVED8;
453 cyg_uint16 intmsk; /* Channel's interrupt mask flags */
454 cyg_uint16 bdflags;
455 cyg_uint16 rbase; /* Rx Buffer Descriptors Base Address */
456 cyg_uint16 tmrblr; /* Max receive buffer length */
457 cyg_uint32 rstate; /* Rx Internal State */
458 cyg_uint32 rxintr; /* Rx Internal Data Pointer */
459 cyg_uint16 rbptr; /* Rx Buffer Descriptor Pointer */
460 cyg_uint16 rxbyc; /* Rx Internal Byte Count */
461 cyg_uint32 rpack; /* (Rx Temp) */
462 cyg_uint32 zdstate; /* Zero Deletion machine state */
463 cyg_uint32 RESERVED9; /* Temp Transmit CRC */
464 cyg_uint16 trnsync; /* Max_length counter */
465 cyg_uint16 RESERVED10; /* Temp */
466
467 };
468
469 /*----------------------------------------------------------*/
470 /* allows multiprotocol array declaration in the memory map */
471 /*----------------------------------------------------------*/
472
473 struct qmc_chan_pram
474 {
475 union
476 {
477 struct qmc_hdlc_pram h;
478 struct qmc_tran_pram t;
479 }h_or_t;
480 };
481
482
483
484 /*--------------------------------------------------------------------*/
485 /* SMC UART parameter RAM */
486 /*--------------------------------------------------------------------*/
487
488 struct smc_uart_pram
489
490 {
491 cyg_uint16 rbase; /* Rx BD Base Address */
492 cyg_uint16 tbase; /* Tx BD Base Address */
493 cyg_uint8 rfcr; /* Rx function code */
494 cyg_uint8 tfcr; /* Tx function code */
495 cyg_uint16 mrblr; /* Rx buffer length */
496 cyg_uint32 rstate; /* Rx internal state */
497 cyg_uint32 rptr; /* Rx internal data pointer */
498 cyg_uint16 rbptr; /* rb BD Pointer */
499 cyg_uint16 rcount; /* Rx internal byte count */
500 cyg_uint32 rtemp; /* Rx temp */
501 cyg_uint32 tstate; /* Tx internal state */
502 cyg_uint32 tptr; /* Tx internal data pointer */
503 cyg_uint16 tbptr; /* Tx BD pointer */
504 cyg_uint16 tcount; /* Tx byte count */
505 cyg_uint32 ttemp; /* Tx temp */
506 cyg_uint16 max_idl; /* Maximum IDLE Characters */
507 cyg_uint16 idlc; /* Temporary IDLE Counter */
508 cyg_uint16 brkln; /* Last Rx Break Length */
509 cyg_uint16 brkec; /* Rx Break Condition Counter */
510 cyg_uint16 brkcr; /* Break Count Register (Tx) */
511 cyg_uint16 r_mask; /* Temporary bit mask */
512 };
513
514
515 /*--------------------------------------------------------------------------*/
516 /* SMC Transparent mode parameter RAM */
517 /*--------------------------------------------------------------------------*/
518
519 struct smc_trnsp_pram
520
521 {
522 cyg_uint16 rbase; /* Rx BD Base Address */
523 cyg_uint16 tbase; /* Tx BD Base Address */
524 cyg_uint8 rfcr; /* Rx function code */
525 cyg_uint8 tfcr; /* Tx function code */
526 cyg_uint16 mrblr; /* Rx buffer length */
527 cyg_uint32 rstate; /* Rx internal state */
528 cyg_uint32 rptr; /* Rx internal data pointer */
529 cyg_uint16 rbptr; /* rb BD Pointer */
530 cyg_uint16 rcount; /* Rx internal byte count */
531 cyg_uint32 rtemp; /* Rx temp */
532 cyg_uint32 tstate; /* Tx internal state */
533 cyg_uint32 tptr; /* Tx internal data pointer */
534 cyg_uint16 tbptr; /* Tx BD pointer */
535 cyg_uint16 tcount; /* Tx byte count */
536 cyg_uint32 ttemp; /* Tx temp */
537 cyg_uint16 RESERVED11[5]; /* Reserved */
538 };
539
540
541 /*--------------------------------------------------------------------------*/
542 /* SPI parameter RAM */
543 /*--------------------------------------------------------------------------*/
544
545 #define SPI_R 0x8000 /* Ready bit in BD */
546
547 struct spi_pram
548
549 {
550 cyg_uint16 rbase; /* Rx BD Base Address */
551 cyg_uint16 tbase; /* Tx BD Base Address */
552 cyg_uint8 rfcr; /* Rx function code */
553 cyg_uint8 tfcr; /* Tx function code */
554 cyg_uint16 mrblr; /* Rx buffer length */
555 cyg_uint32 rstate; /* Rx internal state */
556 cyg_uint32 rptr; /* Rx internal data pointer */
557 cyg_uint16 rbptr; /* rb BD Pointer */
558 cyg_uint16 rcount; /* Rx internal byte count */
559 cyg_uint32 rtemp; /* Rx temp */
560 cyg_uint32 tstate; /* Tx internal state */
561 cyg_uint32 tptr; /* Tx internal data pointer */
562 cyg_uint16 tbptr; /* Tx BD pointer */
563 cyg_uint16 tcount; /* Tx byte count */
564 cyg_uint32 ttemp; /* Tx temp */
565 };
566
567
568 /*--------------------------------------------------------------------------*/
569 /* I2C parameter RAM */
570 /*--------------------------------------------------------------------------*/
571
572 struct i2c_pram
573
574 {
575 /*--------------------*/
576 /* I2C parameter RAM */
577 /*--------------------*/
578
579 cyg_uint16 rbase; /* RX BD base address */
580 cyg_uint16 tbase; /* TX BD base address */
581 cyg_uint8 rfcr; /* Rx function code */
582 cyg_uint8 tfcr; /* Tx function code */
583 cyg_uint16 mrblr; /* Rx buffer length */
584 cyg_uint32 rstate; /* Rx internal state */
585 cyg_uint32 rptr; /* Rx internal data pointer */
586 cyg_uint16 rbptr; /* rb BD Pointer */
587 cyg_uint16 rcount; /* Rx internal byte count */
588 cyg_uint32 rtemp; /* Rx temp */
589 cyg_uint32 tstate; /* Tx internal state */
590 cyg_uint32 tptr; /* Tx internal data pointer */
591 cyg_uint16 tbptr; /* Tx BD pointer */
592 cyg_uint16 tcount; /* Tx byte count */
593 cyg_uint32 ttemp; /* Tx temp */
594 };
595
596
597 /*--------------------------------------------------------------------------*/
598 /* PIP Centronics parameter RAM */
599 /*--------------------------------------------------------------------------*/
600
601 struct centronics_pram
602
603 {
604 cyg_uint16 rbase; /* Rx BD Base Address */
605 cyg_uint16 tbase; /* Tx BD Base Address */
606 cyg_uint8 fcr; /* function code */
607 cyg_uint8 smask; /* Status Mask */
608 cyg_uint16 mrblr; /* Rx buffer length */
609 cyg_uint32 rstate; /* Rx internal state */
610 cyg_uint32 rptr; /* Rx internal data pointer */
611 cyg_uint16 rbptr; /* rb BD Pointer */
612 cyg_uint16 rcount; /* Rx internal byte count */
613 cyg_uint32 rtemp; /* Rx temp */
614 cyg_uint32 tstate; /* Tx internal state */
615 cyg_uint32 tptr; /* Tx internal data pointer */
616 cyg_uint16 tbptr; /* Tx BD pointer */
617 cyg_uint16 tcount; /* Tx byte count */
618 cyg_uint32 ttemp; /* Tx temp */
619 cyg_uint16 max_sl; /* Maximum Silence period */
620 cyg_uint16 sl_cnt; /* Silence Counter */
621 cyg_uint16 char1; /* CONTROL char 1 */
622 cyg_uint16 char2; /* CONTROL char 2 */
623 cyg_uint16 char3; /* CONTROL char 3 */
624 cyg_uint16 char4; /* CONTROL char 4 */
625 cyg_uint16 char5; /* CONTROL char 5 */
626 cyg_uint16 char6; /* CONTROL char 6 */
627 cyg_uint16 char7; /* CONTROL char 7 */
628 cyg_uint16 char8; /* CONTROL char 8 */
629 cyg_uint16 rccm; /* Rx Control Char Mask */
630 cyg_uint16 rccr; /* Rx Char Control Register */
631 };
632
633
634 /*--------------------------------------------------------------------------*/
635 /* IDMA parameter RAM */
636 /*--------------------------------------------------------------------------*/
637
638 struct idma_pram
639
640 {
641 cyg_uint16 ibase; /* IDMA BD Base Address */
642 cyg_uint16 dcmr; /* DMA Channel Mode Register */
643 cyg_uint32 sapr; /* Source Internal Data Pointer */
644 cyg_uint32 dapr; /* Destination Internal Data Pointer */
645 cyg_uint16 ibptr; /* Buffer Descriptor Pointer */
646 cyg_uint16 write_sp; /* No description given in manual */
647 cyg_uint32 s_byte_c; /* Internal Source Byte Count */
648 cyg_uint32 d_byte_c; /* Internal Destination Byte Count */
649 cyg_uint32 s_state; /* Internal State */
650 cyg_uint32 itemp0; /* Temp Data Storage */
651 cyg_uint32 itemp1; /* Temp Data Storage */
652 cyg_uint32 itemp2; /* Temp Data Storage */
653 cyg_uint32 itemp3; /* Temp Data Storage */
654 cyg_uint32 sr_mem; /* Data Storage for Peripherial Write */
655 cyg_uint16 read_sp; /* No description given in manual */
656 cyg_uint16 nodesc0; /* Diff Between Source and Destination Residue*/
657 cyg_uint16 nodesc1; /* Temp Storage Address Pointer */
658 cyg_uint16 nodesc2; /* SR_MEM Byte Count */
659 cyg_uint32 d_state; /* Internal State */
660 };
661
662
663
664 /*--------------------------------------------------------------------------*/
665 /* RISC timer parameter RAM */
666 /*--------------------------------------------------------------------------*/
667
668 struct timer_pram
669
670 {
671 /*----------------------------*/
672 /* RISC timers parameter RAM */
673 /*----------------------------*/
674
675 cyg_uint16 tm_base; /* RISC timer table base adr */
676 cyg_uint16 tm_ptr; /* RISC timer table pointer */
677 cyg_uint16 r_tmr; /* RISC timer mode register */
678 cyg_uint16 r_tmv; /* RISC timer valid register */
679 cyg_uint32 tm_cmd; /* RISC timer cmd register */
680 cyg_uint32 tm_cnt; /* RISC timer internal cnt */
681 };
682
683
684 /*--------------------------------------------------------------------------*/
685 /* ROM Microcode parameter RAM */
686 /*--------------------------------------------------------------------------*/
687
688 struct ucode_pram
689
690 {
691 /*---------------------------*/
692 /* RISC ucode parameter RAM */
693 /*---------------------------*/
694
695 cyg_uint16 rev_num; /* Ucode Revision Number */
696 cyg_uint16 d_ptr; /* MISC Dump area pointer */
697 cyg_uint32 temp1; /* MISC Temp1 */
698 cyg_uint32 temp2; /* MISC Temp2 */
699 };
700
701
702 /*---------------------------------------------------------------------------*/
703 /* Example structuring of user data area of memory at 0x2000 (base of DPRAM) */
704 /* Note that this area can also be used by microcodes and the QMC channel */
705 /* specific parameter ram. */
706 /*---------------------------------------------------------------------------*/
707
708 struct user_data
709
710 {
711
712 volatile cyg_uint8 udata_bd_ucode[0x200]; /* user data bd's or Ucode (small) */
713 volatile cyg_uint8 udata_bd_ucode2[0x200]; /* user data bd's or Ucode (medium) */
714 volatile cyg_uint8 udata_bd_ucode3[0x400]; /* user data bd's or Ucode (large) */
715 volatile cyg_uint8 udata_bd[0x700]; /* user data bd's*/
716 volatile cyg_uint8 ucode_ext[0x100]; /* Ucode Extension ram*/
717 volatile cyg_uint8 RESERVED12[0x0c00]; /* Reserved area */
718
719 };
720
721
722
723 /***************************************************************************/
724 /* */
725 /* Definitions of Embedded PowerPC (EPPC) internal memory structures, */
726 /* including registers and dual-port RAM */
727 /* */
728 /***************************************************************************/
729
730 typedef struct eppc
731
732 {
733 /*-----------------------------------*/
734 /* BASE + 0x0000: INTERNAL REGISTERS */
735 /*-----------------------------------*/
736
737 /*-----*/
738 /* SIU */
739 /*-----*/
740
741 volatile cyg_uint32 siu_mcr; /* module configuration reg */
742 volatile cyg_uint32 siu_sypcr; /* System protection cnt */
743 cyg_uint8 RESERVED13[0x6];
744 volatile cyg_uint16 siu_swsr; /* sw service */
745 volatile cyg_uint32 siu_sipend; /* Interrupt pend reg */
746 volatile cyg_uint32 siu_simask; /* Interrupt mask reg */
747 volatile cyg_uint32 siu_siel; /* Interrupt edge level mask reg */
748 volatile cyg_uint32 siu_sivec; /* Interrupt vector */
749 volatile cyg_uint32 siu_tesr; /* Transfer error status */
750 volatile cyg_uint8 RESERVED14[0xc]; /* Reserved area */
751 volatile cyg_uint32 dma_sdcr; /* SDMA configuration reg */
752 cyg_uint8 RESERVED15[0x4c];
753
754 /*--------*/
755 /* PCMCIA */
756 /*--------*/
757
758 volatile cyg_uint32 pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
759 volatile cyg_uint32 pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
760 volatile cyg_uint32 pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
761 volatile cyg_uint32 pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
762 volatile cyg_uint32 pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
763 volatile cyg_uint32 pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
764 volatile cyg_uint32 pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
765 volatile cyg_uint32 pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
766 volatile cyg_uint32 pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
767 volatile cyg_uint32 pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
768 volatile cyg_uint32 pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
769 volatile cyg_uint32 pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
770 volatile cyg_uint32 pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
771 volatile cyg_uint32 pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
772 volatile cyg_uint32 pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
773 volatile cyg_uint32 pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
774 volatile cyg_uint8 RESERVED16[0x20]; /* Reserved area */
775 volatile cyg_uint32 pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
776 volatile cyg_uint32 pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
777 volatile cyg_uint32 pcmcia_pscr; /* PCMCIA Status Reg */
778 volatile cyg_uint8 RESERVED17[0x4]; /* Reserved area */
779 volatile cyg_uint32 pcmcia_pipr; /* PCMCIA Pins Value Reg */
780 volatile cyg_uint8 RESERVED18[0x4]; /* Reserved area */
781 volatile cyg_uint32 pcmcia_per; /* PCMCIA Enable Reg */
782 volatile cyg_uint8 RESERVED19[0x4]; /* Reserved area */
783
784 /*------*/
785 /* MEMC */
786 /*------*/
787
788 volatile cyg_uint32 memc_br0; /* base register 0 */
789 volatile cyg_uint32 memc_or0; /* option register 0 */
790 volatile cyg_uint32 memc_br1; /* base register 1 */
791 volatile cyg_uint32 memc_or1; /* option register 1 */
792 volatile cyg_uint32 memc_br2; /* base register 2 */
793 volatile cyg_uint32 memc_or2; /* option register 2 */
794 volatile cyg_uint32 memc_br3; /* base register 3 */
795 volatile cyg_uint32 memc_or3; /* option register 3 */
796 volatile cyg_uint32 memc_br4; /* base register 3 */
797 volatile cyg_uint32 memc_or4; /* option register 3 */
798 volatile cyg_uint32 memc_br5; /* base register 3 */
799 volatile cyg_uint32 memc_or5; /* option register 3 */
800 volatile cyg_uint32 memc_br6; /* base register 3 */
801 volatile cyg_uint32 memc_or6; /* option register 3 */
802 volatile cyg_uint32 memc_br7; /* base register 3 */
803 volatile cyg_uint32 memc_or7; /* option register 3 */
804 volatile cyg_uint8 RESERVED20[0x24]; /* Reserved area */
805 volatile cyg_uint32 memc_mar; /* Memory address */
806 volatile cyg_uint32 memc_mcr; /* Memory command */
807 volatile cyg_uint8 RESERVED21[0x4]; /* Reserved area */
808 volatile cyg_uint32 memc_mamr; /* Machine A mode */
809 volatile cyg_uint32 memc_mbmr; /* Machine B mode */
810 volatile cyg_uint16 memc_mstat; /* Memory status */
811 volatile cyg_uint16 memc_mptpr; /* Memory preidic timer prescalar */
812 volatile cyg_uint32 memc_mdr; /* Memory data */
813 volatile cyg_uint8 RESERVED22[0x80]; /* Reserved area */
814
815 /*---------------------------*/
816 /* SYSTEM INTEGRATION TIMERS */
817 /*---------------------------*/
818
819 volatile cyg_uint16 simt_tbscr; /* Time base stat&ctr */
820 volatile cyg_uint8 RESERVED23[0x2]; /* Reserved area */
821 volatile cyg_uint32 simt_tbreff0; /* Time base reference 0 */
822 volatile cyg_uint32 simt_tbreff1; /* Time base reference 1 */
823 volatile cyg_uint8 RESERVED24[0x14]; /* Reserved area */
824 volatile cyg_uint16 simt_rtcsc; /* Realtime clk stat&cntr 1 */
825 volatile cyg_uint8 RESERVED25[0x2]; /* Reserved area */
826 volatile cyg_uint32 simt_rtc; /* Realtime clock */
827 volatile cyg_uint32 simt_rtsec; /* Realtime alarm seconds */
828 volatile cyg_uint32 simt_rtcal; /* Realtime alarm */
829 volatile cyg_uint8 RESERVED26[0x10]; /* Reserved area */
830 volatile cyg_uint32 simt_piscr; /* PIT stat&ctrl */
831 volatile cyg_uint32 simt_pitc; /* PIT counter */
832 volatile cyg_uint32 simt_pitr; /* PIT */
833 volatile cyg_uint8 RESERVED27[0x34]; /* Reserved area */
834
835 /*---------------*/
836 /* CLOCKS, RESET */
837 /*---------------*/
838
839 volatile cyg_uint32 clkr_sccr; /* System clk cntrl */
840 volatile cyg_uint32 clkr_plprcr; /* PLL reset&ctrl */
841 volatile cyg_uint32 clkr_rsr; /* reset status */
842 cyg_uint8 RESERVED28[0x74]; /* Reserved area */
843
844 /*--------------------------------*/
845 /* System Integration Timers Keys */
846 /*--------------------------------*/
847
848 volatile cyg_uint32 simt_tbscrk; /* Timebase Status&Ctrl Key */
849 volatile cyg_uint32 simt_tbreff0k; /* Timebase Reference 0 Key */
850 volatile cyg_uint32 simt_tbreff1k; /* Timebase Reference 1 Key */
851 volatile cyg_uint32 simt_tbk; /* Timebase and Decrementer Key */
852 cyg_uint8 RESERVED29[0x10]; /* Reserved area */
853 volatile cyg_uint32 simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
854
855 volatile cyg_uint32 simt_rtck; /* Real-Time Clock Key */
856 volatile cyg_uint32 simt_rtseck; /* Real-Time Alarm Seconds Key */
857 volatile cyg_uint32 simt_rtcalk; /* Real-Time Alarm Key */
858 cyg_uint8 RESERVED30[0x10]; /* Reserved area */
859 volatile cyg_uint32 simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
860 volatile cyg_uint32 simt_pitck; /* Periodic Interrupt Count Key */
861 cyg_uint8 RESERVED31[0x38]; /* Reserved area */
862
863 /*----------------------*/
864 /* Clock and Reset Keys */
865 /*----------------------*/
866
867 volatile cyg_uint32 clkr_sccrk; /* System Clock Control Key */
868 volatile cyg_uint32 clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
869 volatile cyg_uint32 clkr_rsrk; /* Reset Status Key */
870 cyg_uint8 RESERVED32[0x4d4]; /* Reserved area */
871
872 /*-----*/
873 /* I2C */
874 /*-----*/
875
876 volatile cyg_uint8 i2c_i2mod; /* i2c mode */
877 cyg_uint8 RESERVED33[3];
878 volatile cyg_uint8 i2c_i2add; /* i2c address */
879 cyg_uint8 RESERVED34[3];
880 volatile cyg_uint8 i2c_i2brg; /* i2c brg */
881 cyg_uint8 RESERVED35[3];
882 volatile cyg_uint8 i2c_i2com; /* i2c command */
883 cyg_uint8 RESERVED36[3];
884 volatile cyg_uint8 i2c_i2cer; /* i2c event */
885 cyg_uint8 RESERVED37[3];
886 volatile cyg_uint8 i2c_i2cmr; /* i2c mask */
887 volatile cyg_uint8 RESERVED38[0x8b]; /* Reserved area */
888
889 /*-----*/
890 /* DMA */
891 /*-----*/
892
893 volatile cyg_uint8 RESERVED39[0x4]; /* Reserved area */
894 volatile cyg_uint32 dma_sdar; /* SDMA address reg */
895 volatile cyg_uint8 RESERVED40[0x2]; /* Reserved area */
896 volatile cyg_uint8 dma_sdsr; /* SDMA status reg */
897 volatile cyg_uint8 RESERVED41[0x3]; /* Reserved area */
898 volatile cyg_uint8 dma_sdmr; /* SDMA mask reg */
899 volatile cyg_uint8 RESERVED42[0x1]; /* Reserved area */
900 volatile cyg_uint8 dma_idsr1; /* IDMA1 status reg */
901 volatile cyg_uint8 RESERVED43[0x3]; /* Reserved area */
902 volatile cyg_uint8 dma_idmr1; /* IDMA1 mask reg */
903 volatile cyg_uint8 RESERVED44[0x3]; /* Reserved area */
904 volatile cyg_uint8 dma_idsr2; /* IDMA2 status reg */
905 volatile cyg_uint8 RESERVED45[0x3]; /* Reserved area */
906 volatile cyg_uint8 dma_idmr2; /* IDMA2 mask reg */
907 volatile cyg_uint8 RESERVED46[0x13]; /* Reserved area */
908
909 /*--------------------------*/
910 /* CPM Interrupt Controller */
911 /*--------------------------*/
912
913 volatile cyg_uint16 cpmi_civr; /* CP interrupt vector reg */
914 volatile cyg_uint8 RESERVED47[0xe]; /* Reserved area */
915 volatile cyg_uint32 cpmi_cicr; /* CP interrupt configuration reg */
916 volatile cyg_uint32 cpmi_cipr; /* CP interrupt pending reg */
917 volatile cyg_uint32 cpmi_cimr; /* CP interrupt mask reg */
918 volatile cyg_uint32 cpmi_cisr; /* CP interrupt in-service reg */
919
920 /*----------*/
921 /* I/O port */
922 /*----------*/
923
924 volatile cyg_uint16 pio_padir; /* port A data direction reg */
925 volatile cyg_uint16 pio_papar; /* port A pin assignment reg */
926 volatile cyg_uint16 pio_paodr; /* port A open drain reg */
927 volatile cyg_uint16 pio_padat; /* port A data register */
928 volatile cyg_uint8 RESERVED48[0x8]; /* Reserved area */
929 volatile cyg_uint16 pio_pcdir; /* port C data direction reg */
930 volatile cyg_uint16 pio_pcpar; /* port C pin assignment reg */
931 volatile cyg_uint16 pio_pcso; /* port C special options */
932 volatile cyg_uint16 pio_pcdat; /* port C data register */
933 volatile cyg_uint16 pio_pcint; /* port C interrupt cntrl reg */
934 cyg_uint8 RESERVED49[6];
935 volatile cyg_uint16 pio_pddir; /* port D Data Direction reg */
936 volatile cyg_uint16 pio_pdpar; /* port D pin assignment reg */
937 cyg_uint8 RESERVED50[2];
938 volatile cyg_uint16 pio_pddat; /* port D data reg */
939 volatile cyg_uint8 RESERVED51[0x8]; /* Reserved area */
940
941 /*-----------*/
942 /* CPM Timer */
943 /*-----------*/
944
945 volatile cyg_uint16 timer_tgcr; /* timer global configuration reg */
946 volatile cyg_uint8 RESERVED52[0xe]; /* Reserved area */
947 volatile cyg_uint16 timer_tmr1; /* timer 1 mode reg */
948 volatile cyg_uint16 timer_tmr2; /* timer 2 mode reg */
949 volatile cyg_uint16 timer_trr1; /* timer 1 referance reg */
950 volatile cyg_uint16 timer_trr2; /* timer 2 referance reg */
951 volatile cyg_uint16 timer_tcr1; /* timer 1 capture reg */
952 volatile cyg_uint16 timer_tcr2; /* timer 2 capture reg */
953 volatile cyg_uint16 timer_tcn1; /* timer 1 counter reg */
954 volatile cyg_uint16 timer_tcn2; /* timer 2 counter reg */
955 volatile cyg_uint16 timer_tmr3; /* timer 3 mode reg */
956 volatile cyg_uint16 timer_tmr4; /* timer 4 mode reg */
957 volatile cyg_uint16 timer_trr3; /* timer 3 referance reg */
958 volatile cyg_uint16 timer_trr4; /* timer 4 referance reg */
959 volatile cyg_uint16 timer_tcr3; /* timer 3 capture reg */
960 volatile cyg_uint16 timer_tcr4; /* timer 4 capture reg */
961 volatile cyg_uint16 timer_tcn3; /* timer 3 counter reg */
962 volatile cyg_uint16 timer_tcn4; /* timer 4 counter reg */
963 volatile cyg_uint16 timer_ter1; /* timer 1 event reg */
964 volatile cyg_uint16 timer_ter2; /* timer 2 event reg */
965 volatile cyg_uint16 timer_ter3; /* timer 3 event reg */
966 volatile cyg_uint16 timer_ter4; /* timer 4 event reg */
967 volatile cyg_uint8 RESERVED53[0x8]; /* Reserved area */
968
969 /*----*/
970 /* CP */
971 /*----*/
972
973 volatile cyg_uint16 cp_cr; /* command register */
974 volatile cyg_uint8 RESERVED54[0x2]; /* Reserved area */
975 volatile cyg_uint16 cp_rccr; /* main configuration reg */
976 volatile cyg_uint8 RESERVED55; /* Reserved area */
977 volatile cyg_uint8 cp_resv1; /* Reserved reg */
978 volatile cyg_uint32 cp_resv2; /* Reserved reg */
979 volatile cyg_uint16 cp_rctr1; /* ram break register 1 */
980 volatile cyg_uint16 cp_rctr2; /* ram break register 2 */
981 volatile cyg_uint16 cp_rctr3; /* ram break register 3 */
982 volatile cyg_uint16 cp_rctr4; /* ram break register 4 */
983 volatile cyg_uint8 RESERVED56[0x2]; /* Reserved area */
984 volatile cyg_uint16 cp_rter; /* RISC timers event reg */
985 volatile cyg_uint8 RESERVED57[0x2]; /* Reserved area */
986 volatile cyg_uint16 cp_rtmr; /* RISC timers mask reg */
987 volatile cyg_uint8 RESERVED58[0x14]; /* Reserved area */
988
989 /*-----*/
990 /* BRG */
991 /*-----*/
992
993 volatile cyg_uint32 brgc1; /* BRG1 configuration reg */
994 volatile cyg_uint32 brgc2; /* BRG2 configuration reg */
995 volatile cyg_uint32 brgc3; /* BRG3 configuration reg */
996 volatile cyg_uint32 brgc4; /* BRG4 configuration reg */
997
998 /*---------------*/
999 /* SCC registers */
1000 /*---------------*/
1001
1002 struct scc_regs
1003
1004 {
1005 volatile cyg_uint32 scc_gsmr_l; /* SCC Gen mode (LOW) */
1006 volatile cyg_uint32 scc_gsmr_h; /* SCC Gen mode (HIGH) */
1007 volatile cyg_uint16 scc_psmr; /* protocol specific mode register */
1008 volatile cyg_uint8 RESERVED59[0x2]; /* Reserved area */
1009 volatile cyg_uint16 scc_todr; /* SCC transmit on demand */
1010 volatile cyg_uint16 scc_dsr; /* SCC data sync reg */
1011 volatile cyg_uint16 scc_scce; /* SCC event reg */
1012 volatile cyg_uint8 RESERVED60[0x2]; /* Reserved area */
1013 volatile cyg_uint16 scc_sccm; /* SCC mask reg */
1014 volatile cyg_uint8 RESERVED61[0x1]; /* Reserved area */
1015 volatile cyg_uint8 scc_sccs; /* SCC status reg */
1016 volatile cyg_uint8 RESERVED62[0x8]; /* Reserved area */
1017
1018 } scc_regs[4];
1019
1020
1021 /*-----*/
1022 /* SMC */
1023 /*-----*/
1024
1025 struct smc_regs
1026
1027 {
1028 volatile cyg_uint8 RESERVED63[0x2]; /* Reserved area */
1029 volatile cyg_uint16 smc_smcmr; /* SMC mode reg */
1030 volatile cyg_uint8 RESERVED64[0x2]; /* Reserved area */
1031 volatile cyg_uint8 smc_smce; /* SMC event reg */
1032 volatile cyg_uint8 RESERVED65[0x3]; /* Reserved area */
1033 volatile cyg_uint8 smc_smcm; /* SMC mask reg */
1034 volatile cyg_uint8 RESERVED66[0x5]; /* Reserved area */
1035
1036 } smc_regs[2];
1037
1038
1039 /*-----*/
1040 /* SPI */
1041 /*-----*/
1042
1043 volatile cyg_uint16 spi_spmode; /* SPI mode reg */
1044 volatile cyg_uint8 RESERVED67[0x4]; /* Reserved area */
1045 volatile cyg_uint8 spi_spie; /* SPI event reg */
1046 volatile cyg_uint8 RESERVED68[0x3]; /* Reserved area */
1047 volatile cyg_uint8 spi_spim; /* SPI mask reg */
1048 volatile cyg_uint8 RESERVED69[0x2]; /* Reserved area */
1049 volatile cyg_uint8 spi_spcom; /* SPI command reg */
1050 volatile cyg_uint8 RESERVED70[0x4]; /* Reserved area */
1051
1052 /*-----*/
1053 /* PIP */
1054 /*-----*/
1055
1056 volatile cyg_uint16 pip_pipc; /* pip configuration reg */
1057 volatile cyg_uint8 RESERVED71[0x2]; /* Reserved area */
1058 volatile cyg_uint16 pip_ptpr; /* pip timing parameters reg */
1059 volatile cyg_uint32 pip_pbdir; /* port b data direction reg */
1060 volatile cyg_uint32 pip_pbpar; /* port b pin assignment reg */
1061 volatile cyg_uint8 RESERVED72[0x2]; /* Reserved area */
1062 volatile cyg_uint16 pip_pbodr; /* port b open drain reg */
1063 volatile cyg_uint32 pip_pbdat; /* port b data reg */
1064 volatile cyg_uint8 RESERVED73[0x18]; /* Reserved area */
1065
1066
1067 /*------------------*/
1068 /* Serial Interface */
1069 /*------------------*/
1070
1071 volatile cyg_uint32 si_simode; /* SI mode register */
1072 volatile cyg_uint8 si_sigmr; /* SI global mode register */
1073 volatile cyg_uint8 RESERVED74; /* Reserved area */
1074 volatile cyg_uint8 si_sistr; /* SI status register */
1075 volatile cyg_uint8 si_sicmr; /* SI command register */
1076 volatile cyg_uint8 RESERVED75[0x4]; /* Reserved area */
1077 volatile cyg_uint32 si_sicr; /* SI clock routing */
1078 volatile cyg_uint32 si_sirp; /* SI ram pointers */
1079 volatile cyg_uint8 RESERVED76[0x10c]; /* Reserved area */
1080 volatile cyg_uint8 si_siram[0x200]; /* SI routing ram */
1081 volatile cyg_uint8 RESERVED77[0x1200]; /* Reserved area */
1082
1083 /*-----------------------------------------------------------------*/
1084 /* BASE + 0x2000: user data memory, microcode, or QMC channel PRAM */
1085 /*-----------------------------------------------------------------*/
1086
1087 union
1088 {
1089 struct qmc_chan_pram qcp[64];
1090 struct user_data ud;
1091 cyg_uint8 RESERVED[0x1c00];
1092 } qcp_or_ud;
1093
1094
1095 /*-----------------------------------------------------------------------*/
1096 /* BASE + 0x3c00: PARAMETER RAM. This main union defines 4 memory blocks */
1097 /* of an identical size. See the Parameter RAM definition in the MPC860 */
1098 /* user's manual. */
1099 /*-----------------------------------------------------------------------*/
1100
1101 /*------------------------*/
1102 /* Base + 0x3C00 (page 1) */
1103 /* + 0x3D00 (page 2) */
1104 /* + 0x3E00 (page 3) */
1105 /* + 0x3F00 (page 4) */
1106 /*------------------------*/
1107
1108 union
1109
1110 {
1111 struct page_of_pram
1112
1113 {
1114 /*------------------------------------------------------------*/
1115 /* scc parameter area - 1st memory block (protocol dependent) */
1116 /*------------------------------------------------------------*/
1117
1118 union
1119
1120 {
1121 struct hdlc_pram h;
1122 struct uart_pram u;
1123 struct bisync_pram b;
1124 struct transparent_pram t;
1125 struct async_hdlc_pram a;
1126 cyg_uint8 RESERVED78[0x80];
1127
1128 } scc;
1129
1130 /*----------------------------------------------------------------*/
1131 /* Other protocol areas for the rest of the memory blocks in each */
1132 /* page. */
1133 /*----------------------------------------------------------------*/
1134
1135 union
1136
1137 {
1138 /*---------------------------------------------------------------*/
1139 /* This structure defines the rest of the blocks on the 1st page */
1140 /*---------------------------------------------------------------*/
1141
1142 struct
1143
1144 {
1145 struct i2c_pram i2c; /* I2C */
1146 struct idma_pram idma1; /* IDMA1 */
1147
1148 } i2c_idma;
1149
1150 /*---------------------------------------------------------------*/
1151 /* This structure defines the rest of the blocks on the 2nd page */
1152 /*---------------------------------------------------------------*/
1153
1154 struct
1155
1156 {
1157 struct spi_pram spi; /* SPI */
1158 struct timer_pram timer; /* Timers */
1159 struct idma_pram idma2; /* IDMA2 */
1160
1161 } spi_timer_idma;
1162
1163 /*---------------------------------------------------------------*/
1164 /* This structure defines the rest of the blocks on the 3rd page */
1165 /*---------------------------------------------------------------*/
1166
1167 struct
1168
1169 {
1170 union
1171
1172 {
1173 struct smc_uart_pram u1; /* SMC1 */
1174 struct smc_trnsp_pram t1; /* SMC1 */
1175 cyg_uint8 RESERVED78[0x80]; /* declare full block */
1176
1177 } psmc1;
1178
1179 } smc_dsp1;
1180
1181
1182 /*---------------------------------------------------------------*/
1183 /* This structure defines the rest of the blocks on the 4th page */
1184 /*---------------------------------------------------------------*/
1185
1186 struct
1187
1188 {
1189 union
1190
1191 {
1192 struct smc_uart_pram u2; /* SMC2 */
1193 struct smc_trnsp_pram t2; /* SMC2 */
1194 struct centronics_pram c; /* Uses SM2's space */
1195 cyg_uint8 RESERVED79[0x80]; /* declare full block */
1196
1197 } psmc2;
1198
1199 } smc_dsp2;
1200
1201 cyg_uint8 RESERVED80[0x80]; /* declare full block */
1202
1203 } other;
1204
1205 } pg;
1206
1207 /*---------------------------------------------------------------*/
1208 /* When selecting Ethernet as protocol for an SCC, this protocol */
1209 /* uses a complete page of Parameter RAM memory. */
1210 /*---------------------------------------------------------------*/
1211
1212 struct ethernet_pram enet_scc;
1213
1214 /*---------------------------------------------------------------*/
1215 /* When using QMC as a mode for an SCC, the QMC global parameter */
1216 /* ram uses from SCC BASE to BASE+AC. */
1217 /*---------------------------------------------------------------*/
1218
1219 struct global_qmc_pram gqp;
1220
1221 /*--------------------------------------------------------*/
1222 /* declaration to guarantee a page of memory is allocated */
1223 /*--------------------------------------------------------*/
1224
1225 cyg_uint8 RESERVED83[0x100];
1226
1227 } PRAM[4]; /* end of union */
1228
1229 } EPPC;
1230
1231
1232 /***************************************************************************/
1233 /* General Global Definitions */
1234 /***************************************************************************/
1235
1236
1237 #define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */
1238 #define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */
1239 #define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */
1240 #define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */
1241
1242 #define SCC1_REG 0 /* SCC1 Index into SCC Regs Array */
1243 #define SCC2_REG 1 /* SCC2 Index into SCC Regs Array */
1244 #define SCC3_REG 2 /* SCC3 Index into SCC Regs Array */
1245 #define SCC4_REG 3 /* SCC4 Index into SCC Regs Array */
1246
1247
1248 /*--------------------------------*/
1249 /* KEEP ALIVE POWER REGISTERS KEY */
1250 /*--------------------------------*/
1251
1252 #define KEEP_ALIVE_KEY 0x55ccaa33
1253
1254
1255 #define SMC2_REG 1 /* SMC Regs Array Index for SMC2 */
1256
1257 /*-------------------------*/
1258 /* Single buffer component */
1259 /*-------------------------*/
1260
1261 typedef struct BufferPool
1262
1263 {
1264 cyg_uint8 RxBuffer;
1265 cyg_uint8 TxBuffer;
1266
1267 } LB;
1268
1269
1270 /*--------------------------*/
1271 /* Buffer Descriptor Format */
1272 /*--------------------------*/
1273
1274 typedef struct BufferDescriptor
1275
1276 {
1277 cyg_uint16 bd_cstatus; /* control and status */
1278 cyg_uint16 bd_length; /* transfer length */
1279 cyg_uint8 *bd_addr; /* buffer address */
1280
1281 } BD;
1282
1283
1284 /*-------------------------------*/
1285 /* Buffer Descriptor Ring format */
1286 /*-------------------------------*/
1287
1288 typedef struct BufferDescRings
1289
1290 {
1291 volatile BD RxBD; /* Rx BD ring */
1292 volatile BD TxBD; /* Tx BD ring */
1293
1294 } BDRINGS;
1295
1296
1297 #endif