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comparison packages/hal/sparclite/arch/current/src/vectors.S @ 2:443894e2e912 ecos-v1_2_1-release

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Block commit of eCos version 1.2.1
author jlarmour
date Tue, 11 May 1999 12:24:34 +0000
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1 /*=============================================================================
2 //
3 // vectors.S
4 //
5 // SPARClite vectors and bootup code
6 //
7 //=============================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Cygnus eCos Public License
12 // Version 1.0 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://sourceware.cygnus.com/ecos
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Cygnus Operating System, released
22 // September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Cygnus. Portions created
25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
26 // -------------------------------------------
27 //
28 //###COPYRIGHTEND####
29 //=============================================================================
30 //#####DESCRIPTIONBEGIN####
31 //
32 // Author(s): hmt
33 // Contributors:hmt
34 // Date: 1998-12-15
35 // Purpose: SPARClite vector code
36 // Description: This file contains the code which hangs off SPARClite vectors
37 // including reset; it handles register under/overflow as well
38 // as bootup, anything else is deferred to the default interrupt
39 // or exception vsrs respectively. See vec_[ix]vsr.S ...
40 //
41 //####DESCRIPTIONEND####
42 //
43 //===========================================================================*/
44
45 !-----------------------------------------------------------------------------
46
47 .file "vectors.S"
48
49 !-----------------------------------------------------------------------------
50
51 #include <pkgconf/system.h>
52 #include <pkgconf/hal.h>
53
54 #ifdef CYGPKG_KERNEL
55 # include <pkgconf/kernel.h>
56 #endif
57
58 !------------------------------------------------------------------------
59
60 #include <cyg/hal/vectors.h>
61
62 #define DELAYS_AFTER_WRPSR_SAME_WINDOW
63 #define DELAYS_AFTER_WRWIM
64
65 !------------------------------------------------------------------------
66 ! The start of the code; this is the entry point:
67
68 .section ".vectors","ax"
69
70 .global rom_vectors
71 rom_vectors:
72 .global reset_vector
73 reset_vector:
74 ! this code goes to the real reset handler, it will be
75 ! overwritten by the start of vectoring handler...
76 b genuine_reset
77 nop
78 ! usually drop through to:
79 real_vector:
80 ! here,locals have been set up as follows:
81 ! %l0 = psr
82 ! %l1 = pc
83 ! %l2 = npc
84 ! %l3 = tbr
85 and %l3, TT_IS_INTR_MASK, %l4
86 cmp %l4, TT_IS_INTR_VALUE
87 bne not_an_interrupt ! delay slot does not matter
88 ! here be the pre-vector interrupt handler
89 interrupt:
90 and %l3, 0x0f0, %l4 ! get an interrupt number out
91 srl %l4, 2, %l5 ! to a word address offset
92 sethi %hi(hal_vsr_table), %l6
93 or %l6, %lo(hal_vsr_table), %l6
94 ld [ %l6 + %l5 ], %l6 ! get vector in %l6
95 jmp %l6 ! and go there
96 srl %l4, 4, %l3 ! vector number into %l3: so that
97 ! interrupts and exceptions/traps
98 ! have the same API to VSRs
99
100 not_an_interrupt:
101 and %l3, TT_MASK, %l4
102 cmp %l4, (TRAP_WUNDER << TT_SHL)
103
104 bne,a not_window_underflow
105 cmp %l4, (TRAP_WOVER << TT_SHL) ! (if taken)
106
107 ! here be the window underflow handler:
108 window_underflow:
109 ! CWP is trap handler
110 ! CWP + 1 is trapped RESTORE instruction
111 ! CWP + 2 is invalid context which must be restored
112 ! CWP + 3 is next invalid context
113
114 wr %l0, %psr ! restore the condition flags
115 ! (CWP is unchanged)
116 ! the following instructions delay enough; no need for NOPs
117 rd %wim, %l0 ! get the wim
118 sll %l0, 1, %l3 ! Rotate wim left
119 srl %l0, __WINSIZE-1, %l0
120 wr %l0, %l3, %wim ! Install the new wim
121
122 #ifdef DELAYS_AFTER_WRWIM
123 nop ! are these delays needed?
124 nop ! (following restore uses wim)
125 nop
126 #endif
127 restore ! Users window
128 restore ! Her callers window (now valid)
129
130 ldd [%sp + 0 * 4], %l0 ! restore L & I registers
131 ldd [%sp + 2 * 4], %l2
132 ldd [%sp + 4 * 4], %l4
133 ldd [%sp + 6 * 4], %l6
134
135 ldd [%sp + 8 * 4], %i0
136 ldd [%sp + 10 * 4], %i2
137 ldd [%sp + 12 * 4], %i4
138 ldd [%sp + 14 * 4], %i6
139
140 save ! Back to trap window
141 save
142
143 jmp %l1
144 rett %l2
145
146 not_window_underflow:
147 bne,a not_window_overflow
148 srl %l4, 4, %l4 ! (if taken)
149
150 ! here be the window overflow handler:
151 window_overflow:
152 ! CWP + 1 is caller whose SAVE bounced
153 ! CWP is trap handler = invalid window
154 ! CWP - 1 is next invalid window which needs to be saved
155
156 wr %l0, %psr ! restore the condition flags
157 ! (CWP is unchanged)
158 ! the following instructions delay enough; no need for NOPs
159 rd %wim, %l0
160 mov %g1, %l3 ! Save g1, we use it to hold the wim
161 srl %l0, 1, %g1 ! Rotate wim right
162 sll %l0, __WINSIZE-1, %l0
163 or %l0, %g1, %g1
164
165 save ! Slip into next window
166 mov %g1, %wim ! Install the new wim
167 ! (invalidates current window!)
168
169 std %l0, [%sp + 0 * 4] ! save L & I registers
170 std %l2, [%sp + 2 * 4]
171 std %l4, [%sp + 4 * 4]
172 std %l6, [%sp + 6 * 4]
173
174 std %i0, [%sp + 8 * 4]
175 std %i2, [%sp + 10 * 4]
176 std %i4, [%sp + 12 * 4]
177 std %i6, [%sp + 14 * 4]
178
179 restore ! Go back to trap window.
180 mov %l3, %g1 ! Restore %g1
181
182 jmpl %l1, %g0
183 rett %l2
184
185 not_window_overflow:
186 ! from here on in, %l4 is the trap number in clear
187 cmp %l4, 128
188 bge 1f
189 mov 0, %l5 ! offset 0 for user traps
190
191 cmp %l4, 36 ! coprocessor special case
192 beq 1f
193 mov 4, %l5 ! ...treated as FP, code 4
194
195 cmp %l4, 10
196 bge 1f
197 mov 10, %l5 ! offset 10 for "others"
198
199 ! if we are here, the trap number is 1-9 inclusive
200 ! so put it in %l5 and drop through...
201 mov %l4, %l5
202 1:
203 or %l5, 16, %l5 ! offset into table is 16... for traps.
204 sll %l5, 2, %l5 ! to a word address offset
205 sethi %hi(hal_vsr_table), %l6
206 or %l6, %lo(hal_vsr_table), %l6
207 ld [ %l6 + %l5 ], %l6 ! get vector in %l6
208 jmp %l6 ! and go there
209 or %l4, 16, %l3 ! vector number into %l3: so that
210 ! interrupts and exceptions/traps
211 ! have the same API to VSRs
212 ! and that is the end of the pre-vector trap handler
213
214 .global rom_vectors_end
215 rom_vectors_end:
216
217 ! these instructions are copied into the reset vector
218 ! after startup to _not_ branch to the genuine_reset code below
219 real_vector_instructions:
220 rd %tbr, %l3
221 rd %psr, %l0
222
223
224
225 ! genuine reset code called from time zero:
226 genuine_reset: ! set psr, mask interrupts & traps
227 wr %g0, 0xfc0 + __WIN_INIT, %psr
228 nop ! mode = prevMode = S, CWP=7
229 nop
230 nop
231 wr %g0, 0, %wim ! No invalid windows (yet)
232 nop
233 nop
234 nop
235
236 sethi %hi(reset_vector), %g1
237 andn %g1, 0xfff, %g1 ! should not be needed
238 wr %g1, %tbr ! Traps are at reset_vector
239 nop
240 nop
241 nop
242 wr %g0, 1, %asr17 ! Single vector trapping
243 nop
244 nop
245 nop
246
247 // INCLUDE PLATFORM BOOT
248
249 // This should set up RAM and caches, and calm down any external interrupt
250 // sources. Also copy two instructions from real_vector_instructions
251 // into reset_vector, then invalidate the instruction cache.
252
253 #include <cyg/hal/halboot.si>
254
255 // halboot.si returns with %sp all set, in sleb versions.
256
257 led 0x80
258
259 ! now set up a stack and initial frame linkage
260 ! so as to be able to make C function calls:
261 ! current window is 7, the highest, so we store a
262 ! saved frame thingy that refers to itself in the stack,
263 ! then another which is valid and drop into main from there.
264
265 #ifdef CYG_HAL_SPARCLITE_SIM
266 sethi %hi(cyg_bootup_stack), %i6
267 or %i6, %lo(cyg_bootup_stack), %i6
268 #endif
269 andn %i6, 7, %i6 ! round fp down to double alignment
270 mov 0, %i7 ! null return address
271 sethi %hi(0xb51ac000), %i0 ! "BStac" pattern
272 or %i0, 24, %i0
273 or %i0, 1, %i1
274 or %i0, 2, %i2
275 or %i0, 3, %i3
276 or %i0, 4, %i4
277 or %i0, 5, %i5
278
279 sethi %hi(0xb51ac000), %l0 ! "BStac" pattern
280 or %l0, 16, %l0
281 or %l0, 1, %l1
282 or %l0, 2, %l2
283 or %l0, 3, %l3
284 or %l0, 4, %l4
285 or %l0, 5, %l5
286 or %l0, 6, %l6
287 or %l0, 7, %l7
288
289 sub %fp, 16 * 4, %sp ! Stack pointer
290
291 led 0x90
292
293 std %l0, [%sp + 0 * 4] ! save L & I registers
294 std %l2, [%sp + 2 * 4] ! into new stack frame
295 std %l4, [%sp + 4 * 4]
296 std %l6, [%sp + 6 * 4]
297
298 led 0x91
299
300 std %i0, [%sp + 8 * 4]
301 std %i2, [%sp + 10 * 4]
302 std %i4, [%sp + 12 * 4]
303 std %i6, [%sp + 14 * 4]
304
305 led 0x92
306
307 sethi %hi(0xb0010000), %o0 ! "Boot" pattern
308 or %o0, 8, %o0
309 or %o0, 1, %o1
310 or %o0, 2, %o2
311 or %o0, 3, %o3
312 or %o0, 4, %o4
313 or %o0, 5, %o5
314
315 led 0x98
316
317 wr %g0, __WIM_INIT, %wim ! Window 7 (current) is invalid
318 nop
319 nop
320 nop
321
322 led 0x99
323
324 sethi %hi(0xb0010000), %g1 ! "Boot" pattern
325 or %g1, 2, %g2
326 or %g1, 3, %g3
327 or %g1, 4, %g4
328 or %g1, 5, %g5
329 or %g1, 6, %g6
330 or %g1, 7, %g7
331 or %g1, 1, %g1
332
333 led 0xa0
334
335 wr %g0, 0xfe0 + __WIN_INIT, %psr
336 nop ! Enable traps:
337 nop ! set psr, _do_ mask interrupts
338 nop ! mode = prevMode = S, CWP=7
339
340 led 0xb0
341
342 ! now we can start calling out and running C code!
343 .extern cyg_hal_start
344 call cyg_hal_start ! puts return address in %o7
345 or %g1, 1, %g1
346
347 loop_forever:
348 ta 1
349 b loop_forever ! if it returns
350 nop
351
352
353 !---------------------------------------------------------------------------
354 ! hal_vsr_table...
355
356 .section ".data"
357 .balign 4
358 .global hal_vsr_table
359 hal_vsr_table:
360 .rept 16
361 .word hal_default_interrupt_vsr
362 .endr
363 .rept 11
364 .word hal_default_exception_vsr
365 .endr
366
367 !---------------------------------------------------------------------------
368 ! Bootup stack (only needed explicitly in sim)
369
370 #ifdef CYG_HAL_SPARCLITE_SIM
371 .section ".bss"
372
373 .balign 16
374 cyg_bootup_stack_base:
375 .rept 4064
376 .byte 0
377 .endr
378 .balign 16
379 cyg_bootup_stack:
380 .long 0,0,0,0,0,0,0,0
381 #endif
382
383 ! end of vectors.S