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comparison packages/io/serial/current/src/sparclite/sleb_sdtr.h @ 2:443894e2e912 ecos-v1_2_1-release

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Block commit of eCos version 1.2.1
author jlarmour
date Tue, 11 May 1999 12:24:34 +0000
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children c38311975d4f
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1:72f549f0d891 2:443894e2e912
1 #ifndef CYGONCE_SLEB_SDTR_H
2 #define CYGONCE_SLEB_SDTR_H
3 //==========================================================================
4 //
5 // io/serial/sparclite/sleb_sdtr.c
6 //
7 // Serial I/O interface module for SPARClite Eval Board (SLEB)
8 //
9 //==========================================================================
10 //####COPYRIGHTBEGIN####
11 //
12 // -------------------------------------------
13 // The contents of this file are subject to the Cygnus eCos Public License
14 // Version 1.0 (the "License"); you may not use this file except in
15 // compliance with the License. You may obtain a copy of the License at
16 // http://sourceware.cygnus.com/ecos
17 //
18 // Software distributed under the License is distributed on an "AS IS"
19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 // License for the specific language governing rights and limitations under
21 // the License.
22 //
23 // The Original Code is eCos - Embedded Cygnus Operating System, released
24 // September 30, 1998.
25 //
26 // The Initial Developer of the Original Code is Cygnus. Portions created
27 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //==========================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): gthomas
35 // Contributors: gthomas
36 // Date: 1999-02-04
37 // Purpose: SLEB serial I/O module
38 // Description:
39 //
40 //####DESCRIPTIONEND####
41 //
42 //==========================================================================
43
44 #include <cyg/hal/hal_io.h> // For I/O macros
45
46 #define reg(n) ((n)*4)
47
48 // SDTR Registers
49 #define SDTR_TXDATA(base) base+reg(0)
50 #define SDTR_RXDATA(base) base+reg(0)
51 #define SDTR_STATUS(base) base+reg(1)
52 #define SDTR_CONTROL(base) base+reg(1)
53
54 // Mode register
55 #define SDTR_MODE_MODE_MASK 0x03 // Mode selection bits (mask)
56 #define SDTR_MODE_MODE_SYNC 0x00 // Synchronous mode
57 #define SDTR_MODE_MODE_ASYNC1 0x01 // Async - clock/1
58 #define SDTR_MODE_MODE_ASYNC16 0x02 // Async - clock/16
59 #define SDTR_MODE_MODE_ASYNC64 0x03 // Async - clock/64
60 #define SDTR_MODE_DTB_MASK 0x0C // Number of data bits (mask)
61 #define SDTR_MODE_DTB_5 0x00 // 5 bits / char
62 #define SDTR_MODE_DTB_6 0x04 // 6 bits / char
63 #define SDTR_MODE_DTB_7 0x08 // 7 bits / char
64 #define SDTR_MODE_DTB_8 0x0C // 8 bits / char
65 #define SDTR_MODE_PARITY_MASK 0x30 // Parity modes (mask)
66 #define SDTR_MODE_PARITY_ENABLE 0x10 // Enable parity
67 #define SDTR_MODE_PARITY_NONE 0x00 // No parity (parity disabled)
68 #define SDTR_MODE_PARITY_ODD 0x00 // Odd parity
69 #define SDTR_MODE_PARITY_EVEN 0x20 // Even parity
70 #define SDTR_MODE_STOP_BITS_MASK 0xC0 // Number of stop bits (mask)
71 #define SDTR_MODE_STOP_BITS_1 0x40 // 1 stop bit
72 #define SDTR_MODE_STOP_BITS_1_5 0x80 // 1.5 stop bits
73 #define SDTR_MODE_STOP_BITS_2 0xC0 // 2 stop bits
74
75 // Command register
76 #define SDTR_CMD_TxEN 0x01 // Enable transmitter
77 #define SDTR_CMD_DTR 0x02 // Assert DTR
78 #define SDTR_CMD_RxEN 0x04 // Enable receiver
79 #define SDTR_CMD_BREAK 0x08 // Send break
80 #define SDTR_CMD_EFR 0x10 // Error flag reset
81 #define SDTR_CMD_RTS 0x20 // Assert RTS
82 #define SDTR_CMD_RST 0x40 // Internal RESET
83 #define SDTR_CMD_EHM 0x80 // Enable Hunt mode
84
85 // Status register
86 #define SDTR_STAT_TxRDY 0x01 // Transmitter ready
87 #define SDTR_STAT_RxRDY 0x02 // Receiver ready
88 #define SDTR_STAT_TxEMP 0x04 // Transmitter empty
89 #define SDTR_STAT_PERR 0x08 // Parity error
90 #define SDTR_STAT_OERR 0x10 // Overrun error
91 #define SDTR_STAT_FERR 0x20 // Framing error
92 #define SDTR_STAT_SYBRK 0x40 // Break
93 #define SDTR_STAT_DSR 0x80 // State of DSR signal
94
95 // Offsets to standard SDTR elements
96 #define SLEB_SDTR0_BASE (8*4)
97 #define SLEB_SDTR0_TX_INT 9
98 #define SLEB_SDTR0_RX_INT 10
99 #define SLEB_SDTR1_BASE (12*4)
100 #define SLEB_SDTR1_TX_INT 6
101 #define SLEB_SDTR1_RX_INT 7
102 #define SLEB_TIMER3_CONTROL reg(29)
103 #define SLEB_TIMER3_RELOAD reg(30)
104
105 // On-board switch, used to determine baud rate
106 #define SLEB_CLOCK_SWITCH (volatile unsigned char *)0x01000003
107
108 static unsigned char select_word_length[] = {
109 SDTR_MODE_DTB_5, // 5 bits / word (char)
110 SDTR_MODE_DTB_6,
111 SDTR_MODE_DTB_7,
112 SDTR_MODE_DTB_8
113 };
114
115 static unsigned char select_stop_bits[] = {
116 0,
117 SDTR_MODE_STOP_BITS_1, // 1 stop bit
118 SDTR_MODE_STOP_BITS_1_5, // 1.5 stop bit
119 SDTR_MODE_STOP_BITS_2 // 2 stop bits
120 };
121
122 static unsigned char select_parity[] = {
123 SDTR_MODE_PARITY_NONE, // No parity
124 SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_EVEN, // Even parity
125 SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_ODD, // ODD parity
126 0xFF, // Mark parity
127 0xFF, // Space parity
128 };
129
130 static cyg_int32 select_baud[] = {
131 0, // Unused
132 50, // 50
133 75, // 75
134 110, // 110
135 0, // 134.5
136 150, // 150
137 200, // 200
138 300, // 300
139 600, // 600
140 1200, // 1200
141 1800, // 1800
142 2400, // 2400
143 3600, // 3600
144 4800, // 4800
145 7200, // 7200
146 9600, // 9600
147 14400, // 14400
148 19200, // 19200
149 38400, // 38400
150 57600, // 57600
151 115200, // 115200
152 230400, // 230400
153 };
154
155 #endif // CYGONCE_SLEB_SDTR_H
156