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comparison packages/hal/sh/arch/current/src/vectors.S @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
parents 2085233a121a
children 489eb5632bc3
comparison
equal deleted inserted replaced
81:89fef2181d7d 82:6736c52df507
81 #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB) 81 #define CYG_SR_BANK1 (CYGARC_REG_SR_MD|CYGARC_REG_SR_IMASK|CYGARC_REG_SR_RB)
82 82
83 #=========================================================================== 83 #===========================================================================
84 # Start by defining the exceptions vectors. 84 # Start by defining the exceptions vectors.
85 .section ".vectors","ax" 85 .section ".vectors","ax"
86 rom_vectors:
87
88 86
89 # reset 0xa0000000 87 # reset 0xa0000000
90 # other exceptions VBR+0x100 88 # other exceptions VBR+0x100
91 # tlb miss VBR+0x400 89 # tlb miss VBR+0x400
92 # interrupts VBR+0x600 90 # interrupts VBR+0x600
93 91
92
93 #===========================================================================
94 # Reset code must be PC relative so it can be executed out of the shadow
95 # area during startup. Not until after hal_hardware_init can the system
96 # be expected to provide the proper address space (at that time we
97 # jump to the VMA base of the code).
98
94 .globl __reset; 99 .globl __reset;
95 __reset: 100 __reset:
96 # Put CPU in a well-known state, disable interrupts. 101
97 mov.l $nCYG_SR,r1 102 # Initialize CPU
103 mov.l $nCYG_SR,r1 ! Put CPU in a well-known state
98 ldc r1,sr 104 ldc r1,sr
99
100 # Initialize VBR if necessary
101 #if defined(CYG_HAL_STARTUP_ROM) || \
102 ( defined(CYG_HAL_STARTUP_RAM) && \
103 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
104 mov.l $__reset,r1 ! Set VBR
105 ldc r1,vbr
106 #endif
107
108 #ifdef CYG_HAL_STARTUP_ROM
109 # This code will be executed from address 0 if started from ROM.
110 # We do not need it when starting from RAM.
111 mov.l $_start,r0
112 jmp @r0
113 nop
114 .align 2
115 $_start:
116 .long _start
117 #endif
118
119 #===========================================================================
120 # Real startup code.
121
122 .globl _start
123 _start:
124 # Initialize CPU
125 mov #0,r0 105 mov #0,r0
126 mov #CYGARC_REG_CCR,r1 ! Disable cache 106 mov #CYGARC_REG_CCR,r1 ! Disable cache
127 mov.l r0,@r1 107 mov.l r0,@r1
128 mov #CYGARC_REG_MMUCR,r1 ! Disable MMU 108 mov #CYGARC_REG_MMUCR,r1 ! Disable MMU
129 mov.l r0,@r1 109 mov.l r0,@r1
137 mov.b r0,@r1 117 mov.b r0,@r1
138 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources 118 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources
139 mov.w r0,@r1 119 mov.w r0,@r1
140 mov.l $CYGARC_REG_IPRB,r1 120 mov.l $CYGARC_REG_IPRB,r1
141 mov.w r0,@r1 121 mov.w r0,@r1
122
123 # Initialize VBR if necessary
124 #if !defined(CYG_HAL_STARTUP_RAM) || \
125 ( defined(CYG_HAL_STARTUP_RAM) && \
126 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
127 mov.l $__reset,r1 ! Set VBR
128 ldc r1,vbr
129 #endif
130
142 131
143 #ifdef __DEBUG 132 #ifdef __DEBUG
144 mov #0,r0 133 mov #0,r0
145 mov #1,r1 134 mov #1,r1
146 mov #2,r2 135 mov #2,r2
159 #endif 148 #endif
160 149
161 # Call platform specific hardware initialization 150 # Call platform specific hardware initialization
162 # This may include memory controller initialization. It is not 151 # This may include memory controller initialization. It is not
163 # safe to access RAM until after this point. 152 # safe to access RAM until after this point.
164 mov.l $_hal_hardware_init,r0 153 hal_hardware_init
165 jsr @r0 154
166 nop 155 # Now copy necessary bits to RAM and jump to the VMA base
167 156
168 # Set up monitor related stuff (vectors primarily) 157 #ifdef CYG_HAL_STARTUP_ROM
169 hal_mon_init
170
171 # set up stack
172 mov.l $__startup_stack,r15
173
174 #if defined(CYG_HAL_STARTUP_ROM)
175 158
176 # Copy data from ROM to ram 159 # Copy data from ROM to ram
177 mov.l $__rom_data_start,r3 ! r3 = rom start 160 mov.l $__rom_data_start,r3 ! r3 = rom start
178 mov.l $__ram_data_start,r4 ! r4 = ram start 161 mov.l $__ram_data_start,r4 ! r4 = ram start
179 mov.l $__ram_data_end,r5 ! r5 = ram end 162 mov.l $__ram_data_end,r5 ! r5 = ram end
184 mov.l r0,@r4 ! store in RAM 167 mov.l r0,@r4 ! store in RAM
185 add #4,r4 168 add #4,r4
186 cmp/eq r4,r5 ! compare 169 cmp/eq r4,r5 ! compare
187 bf 1b ! loop if not yet done 170 bf 1b ! loop if not yet done
188 2: 171 2:
189 #endif 172
173 # Jump to the proper VMA base of the code.
174 mov.l $_complete_setup,r0
175 jmp @r0
176 nop
177 .align 2
178
179 .extern __rom_data_start
180 .extern __ram_data_start
181 .extern __ram_data_end
182
183 $__rom_data_start:
184 .long __rom_data_start
185 $__ram_data_start:
186 .long __ram_data_start
187 $__ram_data_end:
188 .long __ram_data_end
189 $_complete_setup:
190 .long _complete_setup
191
192 #elif defined(CYG_HAL_STARTUP_ROMRAM)
193
194 # Copy everything to the proper VMA base and jump to it.
195 mov.l $_vectors_lma,r0
196 mov.l $_vectors_vma,r1
197 mov.l $_end,r2
198 1: mov.l @r0+,r3 ! get word from ROM
199 mov.l r3,@r1 ! store in RAM
200 add #4,r1
201 cmp/eq r1,r2 ! compare
202 bf 1b ! loop if not yet done
203 mov.l $_complete_setup,r0
204 jmp @r0
205 nop
206 .align 2
207
208 .extern __vector_code_lma
209
210 $_vectors_lma:
211 .long __vector_code_lma
212 $_vectors_vma:
213 .long __reset
214 $_end:
215 .long _end
216 $_complete_setup:
217 .long _complete_setup
218
219 #else
220
221 # Jump to remaining setup code. Relative branch is OK since VMA=LMA.
222 bra _complete_setup
223
224 #endif
225
226 .align 2
227
228 $nCYG_SR:
229 .long CYG_SR
230 $CYGARC_REG_TSTR:
231 .long CYGARC_REG_TSTR
232 $CYGARC_REG_IPRA:
233 .long CYGARC_REG_IPRA
234 $CYGARC_REG_IPRB:
235 .long CYGARC_REG_IPRB
236 $__reset:
237 .long __reset
238
239 #---------------------------------------------------------------------------
240 # Exception entry
241
242 .org 0x100
243 __exception:
244
245 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
246 mov #1,r7
247 #endif
248
249 mov #CYGARC_REG_EXCEVT,r1
250 mov.l @r1,r1
251 shlr2 r1
252 shlr r1 ! divide cause by 0x08
253 mov.l $_hal_vsr_table,r0
254 mov.l @(r0,r1),r1
255 jmp @r1
256 nop
257
258 .align 2
259 $_hal_vsr_table:
260 .long _hal_vsr_table
261
262 #-----------------------------------------------------------------------------
263 # Complete target initialization and setup.
264 # [Placed here to make use of gap between exception and interrupt entry points]
265 # After this point we can use absolute addressing modes and access all the
266 # memory in the system.
267
268 _complete_setup:
269
270 # Set up monitor related stuff (vectors primarily)
271 hal_mon_init
272
273 # set up stack
274 mov.l $__startup_stack,r15
190 275
191 # clear BSS 276 # clear BSS
192 mov.l $__bss_start,r3 ! r3 = start 277 mov.l $__bss_start,r3 ! r3 = start
193 mov.l $__bss_end,r4 ! r4 = end 278 mov.l $__bss_end,r4 ! r4 = end
194 mov #0,r0 ! r0 = 0 279 mov #0,r0 ! r0 = 0
222 mov.l $_initialize_stub,r1 307 mov.l $_initialize_stub,r1
223 jsr @r1 308 jsr @r1
224 nop 309 nop
225 #endif 310 #endif
226 311
227
228 mov.l $_cyg_start,r1 312 mov.l $_cyg_start,r1
229 jsr @r1 313 jsr @r1
230 nop 314 nop
231 9: 315 9:
232 bra 9b ! if we return, loop 316 bra 9b ! if we return, loop
233 nop 317 nop
234 318
235 .align 2 319 .align 2
236 $nCYG_SR:
237 .long CYG_SR
238 $__startup_stack: 320 $__startup_stack:
239 .long __startup_stack 321 .long __startup_stack
240 $__reset: 322
241 .long __reset
242 $CYGARC_REG_TSTR:
243 .long CYGARC_REG_TSTR
244 $CYGARC_REG_IPRA:
245 .long CYGARC_REG_IPRA
246 $CYGARC_REG_IPRB:
247 .long CYGARC_REG_IPRB
248
249 .extern _hal_hardware_init
250 .extern __bss_start 323 .extern __bss_start
251 .extern __bss_end 324 .extern __bss_end
252 .extern _cyg_hal_invoke_constructors 325 .extern _cyg_hal_invoke_constructors
253 .extern _cyg_start 326 .extern _cyg_start
254 .extern __rom_data_start 327
255 .extern __ram_data_start
256 .extern __ram_data_end
257
258 $_hal_hardware_init:
259 .long _hal_hardware_init
260 $__bss_start: 328 $__bss_start:
261 .long __bss_start 329 .long __bss_start
262 $__bss_end: 330 $__bss_end:
263 .long __bss_end 331 .long __bss_end
264 $_cyg_hal_invoke_constructors: 332 $_cyg_hal_invoke_constructors:
265 .long _cyg_hal_invoke_constructors 333 .long _cyg_hal_invoke_constructors
266 $_cyg_hal_enable_caches: 334 $_cyg_hal_enable_caches:
267 .long _cyg_hal_enable_caches 335 .long _cyg_hal_enable_caches
268 $_cyg_start: 336 $_cyg_start:
269 .long _cyg_start 337 .long _cyg_start
270 $__rom_data_start:
271 .long __rom_data_start
272 $__ram_data_start:
273 .long __ram_data_start
274 $__ram_data_end:
275 .long __ram_data_end
276
277
278 338
279 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS 339 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
280 .extern _initialize_stub 340 .extern _initialize_stub
281 $_initialize_stub: 341 $_initialize_stub:
282 .long _initialize_stub 342 .long _initialize_stub
283 #endif 343 #endif
284 344
285
286 .org 0x100
287 __exception:
288
289 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
290 mov #1,r7
291 #endif
292
293 #ifdef __DEBUG
294 mov #CYGARC_REG_EXCEVT,r1
295 mov.l @r1,r1
296 mov.l $trapval,r0
297 cmp/eq r0,r1
298 bt 1f
299 mov.l $safe_excevt,r0
300 mov.l r1,@r0
301 1:
302 #endif
303
304 mov #CYGARC_REG_EXCEVT,r1
305 mov.l @r1,r1
306 shlr2 r1
307 shlr r1 ! divide cause by 0x08
308 mov.l $_hal_vsr_table,r0
309 mov.l @(r0,r1),r1
310 jmp @r1
311 nop
312
313 .align 2
314 $_hal_vsr_table:
315 .long _hal_vsr_table
316
317 #ifdef __DEBUG
318 $safe_excevt:
319 .long 0x080d0200
320 $trapval:
321 .long 0x00000160
322 #endif
323 345
324 #--------------------------------------------------------------------------- 346 #---------------------------------------------------------------------------
325 # This code handles the common part of all exception handlers. 347 # This code handles the common part of all exception handlers.
326 # It saves the machine state onto the stack and then calls 348 # It saves the machine state onto the stack and then calls
327 # a "C" routine to do the rest of the work. This work may result 349 # a "C" routine to do the rest of the work. This work may result
430 .extern _cyg_hal_exception_handler 452 .extern _cyg_hal_exception_handler
431 453
432 $_cyg_hal_exception_handler: 454 $_cyg_hal_exception_handler:
433 .long _cyg_hal_exception_handler 455 .long _cyg_hal_exception_handler
434 456
435 ! When the call returns it will go to restore_state. 457 #---------------------------------------------------------------------------
458 # TLB miss entry
436 459
437 .org 0x400 460 .org 0x400
438 __tlb_miss: 461 __tlb_miss:
439 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) 462 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
440 mov #2,r7 463 mov #2,r7
441 #endif
442
443 #ifdef __DEBUG
444 mov #CYGARC_REG_EXCEVT,r1
445 mov.l @r1,r1
446 mov.l $safe_excevt2,r0
447 mov.l r1,@r0
448 #endif 464 #endif
449 465
450 mov #CYGARC_REG_EXCEVT,r1 466 mov #CYGARC_REG_EXCEVT,r1
451 mov.l @r1,r1 467 mov.l @r1,r1
452 shlr2 r1 468 shlr2 r1
458 474
459 .align 2 475 .align 2
460 $_hal_vsr_table2: 476 $_hal_vsr_table2:
461 .long _hal_vsr_table 477 .long _hal_vsr_table
462 478
463 #ifdef __DEBUG 479 #---------------------------------------------------------------------------
464 $safe_excevt2: 480 # Interrupt entry
465 .long 0x080d0200
466 #endif
467 481
468 .org 0x600 482 .org 0x600
469 __interrupt: 483 __interrupt:
470 484
471 #ifdef CYGHWR_HAL_SH_HANDLE_SPURIOUS_INTERRUPTS 485 #ifdef CYGHWR_HAL_SH_HANDLE_SPURIOUS_INTERRUPTS
482 496
483 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) 497 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
484 mov #3,r7 498 mov #3,r7
485 #endif 499 #endif
486 500
487 #ifdef __DEBUG
488 mov #CYGARC_REG_INTEVT,r1
489 mov.l @r1,r1
490 mov.l $safe_intevt,r0
491 mov.l r1,@r0
492 #endif
493
494 mov.l $_hal_vsr_table_int,r1 501 mov.l $_hal_vsr_table_int,r1
495 mov.l @r1,r1 502 mov.l @r1,r1
496 jmp @r1 503 jmp @r1
497 nop 504 nop
498 505
499 .align 2 506 .align 2
500 $_hal_vsr_table_int: 507 $_hal_vsr_table_int:
501 .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4 508 .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4
502
503 #ifdef __DEBUG
504 $safe_intevt:
505 .long 0x080d0204
506 #endif
507
508 rom_vectors_end:
509 509
510 510
511 #--------------------------------------------------------------------------- 511 #---------------------------------------------------------------------------
512 # Common interrupt handling code. 512 # Common interrupt handling code.
513 513
522 # ssr = saved sr 522 # ssr = saved sr
523 523
524 # Save away some registers 524 # Save away some registers
525 mov r15,r1 ! entry sp 525 mov r15,r1 ! entry sp
526 526
527 #ifdef __DEBUG
528 mov.l $int_state_marker,r0
529 mov.l r0,@-r15
530 mov #CYGARC_REG_INTEVT,r0
531 mov.l @r0,r0
532 mov.l r0,@-r15
533 #endif
534
535 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT 527 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
536 add #-12,r15 ! Space for cause, gbr, and vbr 528 add #-12,r15 ! Space for cause, gbr, and vbr
537 #else 529 #else
538 add #-4,r15 ! Space for cause 530 add #-4,r15 ! Space for cause
539 531
628 .long _cyg_instrument 620 .long _cyg_instrument
629 1: 621 1:
630 #endif 622 #endif
631 623
632 # Decode the interrupt vector 624 # Decode the interrupt vector
625 #ifdef CYGARC_SH_MOD_INTC_V2
626 mov.l $nCYGARC_REG_INTEVT2,r0
627 #else
633 mov #CYGARC_REG_INTEVT,r0 628 mov #CYGARC_REG_INTEVT,r0
629 #endif
634 mov.l @r0,r4 630 mov.l @r0,r4
635 mov #-5,r0 ! divide cause by 0x20 631 mov #-5,r0 ! divide cause by 0x20
636 shld r0,r4 632 shld r0,r4
637 add #-14,r4 ! adjust so NMI becomes 0 633 add #-14,r4 ! adjust so NMI becomes 0
638 mov #CYGARC_SHREG_EVENT,r0 634 mov #CYGARC_SHREG_EVENT,r0
649 shll2 r9 ! get from vector number to ISR index 645 shll2 r9 ! get from vector number to ISR index
650 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN 646 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
651 647
652 648
653 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 649 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
654 mov #CYGNUM_HAL_INTERRUPT_SCI_RXI,r1
655 cmp/eq r1,r4
656 bf 2f
657 mov r4,r10 ! save across call. 650 mov r4,r10 ! save across call.
658 mov #CYGARC_SHREG_PC,r4 651 mov #CYGARC_SHREG_PC,r4
659 add r8,r4 652 add r8,r4
660 mov.l @r4,r4 653 mov.l @r4,r4
661 mov.l $_cyg_hal_gdb_isr,r1 654 mov.l $_cyg_hal_gdb_isr,r1
756 nop 749 nop
757 #endif 750 #endif
758 751
759 restore_state: 752 restore_state:
760 # All done, restore CPU state and continue 753 # All done, restore CPU state and continue
761 #ifdef __DEBUG
762 mov.l $_safe_addr,r0
763 mov.l @r0,r1
764 add #1,r1
765 mov.l r1,@r0
766 add #4,r0
767
768 mov r15,r1
769 mov #CYGARC_SH_EXCEPTION_SIZE/4,r2
770 1: mov.l @r1+,r3
771 mov.l r3,@r0
772 add #4,r0
773 dt r2
774 bf 1b
775
776 bra 2f
777 nop
778 .align 2
779 $_safe_addr:
780 .long 0x080d0000-4
781 2:
782 #endif
783 754
784 # Disable interrupts and switch register bank during the restore 755 # Disable interrupts and switch register bank during the restore
785 # operation 756 # operation
786 mov.l $nCYG_SR_BANK1,r1 757 mov.l $nCYG_SR_BANK1,r1
787 ldc r1,sr 758 ldc r1,sr
881 #endif 852 #endif
882 $nCYG_SR2: 853 $nCYG_SR2:
883 .long CYG_SR 854 .long CYG_SR
884 $nCYG_SR_BANK1: 855 $nCYG_SR_BANK1:
885 .long CYG_SR_BANK1 856 .long CYG_SR_BANK1
857 $nCYGARC_REG_INTEVT2:
858 .long CYGARC_REG_INTEVT2
886 $_hal_interrupt_handlers: 859 $_hal_interrupt_handlers:
887 .long _hal_interrupt_handlers 860 .long _hal_interrupt_handlers
888 $_hal_interrupt_data: 861 $_hal_interrupt_data:
889 .long _hal_interrupt_data 862 .long _hal_interrupt_data
890 $_hal_interrupt_objects: 863 $_hal_interrupt_objects: