Mercurial > flash_v2
comparison packages/hal/mips/arch/current/include/hal_cache.h @ 143:6b5f480c6929 ecos-sw-2000-12-08
Merge from eCos master repository on 2000-12-08-02:09:36-GMT
| author | jlarmour |
|---|---|
| date | Fri, 08 Dec 2000 03:30:06 +0000 |
| parents | 0ec04793409a |
| children | e0c0827131d1 |
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| 142:12eccf9656f3 | 143:6b5f480c6929 |
|---|---|
| 89 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | 89 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
| 90 | 90 |
| 91 #endif | 91 #endif |
| 92 | 92 |
| 93 //----------------------------------------------------------------------------- | 93 //----------------------------------------------------------------------------- |
| 94 // Cache instruction uses LSB to specify which WAY to affect. This macro | 94 // Cache instruction uses LSBs or MSBs (depending on the |
| 95 // defines the necessary cache instructions to affect all ways. | 95 // implementation) of the virtual address to specify which WAY to |
| 96 // affect. The _ALL_WAYS macro defines the necessary cache instructions | |
| 97 // to affect all ways. | |
| 98 | |
| 99 #ifdef HAL_MIPS_CACHE_INSN_USES_LSB | |
| 100 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS+(_n_)) | |
| 101 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS+(_n_)) | |
| 102 #else | |
| 103 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS) | |
| 104 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS) | |
| 105 #endif | |
| 106 | |
| 96 #if (HAL_DCACHE_WAYS == 1) | 107 #if (HAL_DCACHE_WAYS == 1) |
| 97 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ | 108 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ |
| 98 asm volatile ("cache %0,0(%1);" \ | 109 asm volatile ("cache %0,0(%1);" \ |
| 99 : : "I" ((_cmd_) | 1), "r"(_addr_) ) | 110 : : "I" ((_cmd_) | 1), "r"(_addr_) ) |
| 100 #elif (HAL_DCACHE_WAYS == 2) | 111 #elif (HAL_DCACHE_WAYS == 2) |
| 101 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ | 112 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ |
| 102 asm volatile ("cache %0,0(%1);" \ | 113 asm volatile ("cache %0,0(%1);" \ |
| 103 "cache %0,1(%1);" \ | 114 "cache %0,%2(%1);" \ |
| 104 : : "I" ((_cmd_) | 1), "r"(_addr_) ) | 115 : : "I" ((_cmd_) | 1), "r"(_addr_), \ |
| 116 "I" (_DWAY(1))) | |
| 105 #elif (HAL_DCACHE_WAYS == 4) | 117 #elif (HAL_DCACHE_WAYS == 4) |
| 106 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ | 118 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ |
| 107 asm volatile ("cache %0,0(%1);" \ | 119 asm volatile ("cache %0,0(%1);" \ |
| 108 "cache %0,1(%1);" \ | 120 "cache %0,%2(%1);" \ |
| 109 "cache %0,2(%1);" \ | 121 "cache %0,%3(%1);" \ |
| 110 "cache %0,3(%1);" \ | 122 "cache %0,%4(%1);" \ |
| 111 : : "I" ((_cmd_) | 1), "r"(_addr_) ) | 123 : : "I" ((_cmd_) | 1), "r"(_addr_), \ |
| 124 "I" (_DWAY(1)), \ | |
| 125 "I" (_DWAY(2)), \ | |
| 126 "I" (_DWAY(3))) | |
| 112 #else | 127 #else |
| 113 # error "Unsupported number of ways" | 128 # error "Unsupported number of ways" |
| 114 #endif | 129 #endif |
| 115 | 130 |
| 116 #if (HAL_ICACHE_WAYS == 1) | 131 #if (HAL_ICACHE_WAYS == 1) |
| 117 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ | 132 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ |
| 118 asm volatile ("cache %0,0(%1);" \ | 133 asm volatile ("cache %0,0(%1);" \ |
| 119 : : "I" (_cmd_), "r"(_addr_) ) | 134 : : "I" (_cmd_), "r"(_addr_) ) |
| 120 #elif (HAL_ICACHE_WAYS == 2) | 135 #elif (HAL_ICACHE_WAYS == 2) |
| 121 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ | 136 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ |
| 122 asm volatile ("cache %0,0(%1);" \ | 137 asm volatile ("cache %0,0(%1);" \ |
| 123 "cache %0,1(%1);" \ | 138 "cache %0,%2(%1);" \ |
| 124 : : "I" (_cmd_), "r"(_addr_) ) | 139 : : "I" (_cmd_), "r"(_addr_), \ |
| 140 "I" (_IWAY(1))) | |
| 125 #elif (HAL_ICACHE_WAYS == 4) | 141 #elif (HAL_ICACHE_WAYS == 4) |
| 126 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ | 142 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ |
| 127 asm volatile ("cache %0,0(%1);" \ | 143 asm volatile ("cache %0,0(%1);" \ |
| 128 "cache %0,1(%1);" \ | 144 "cache %0,%2(%1);" \ |
| 129 "cache %0,2(%1);" \ | 145 "cache %0,%3(%1);" \ |
| 130 "cache %0,3(%1);" \ | 146 "cache %0,%4(%1);" \ |
| 131 : : "I" (_cmd_), "r"(_addr_) ) | 147 : : "I" (_cmd_), "r"(_addr_), \ |
| 148 "I" (_IWAY(1)), \ | |
| 149 "I" (_IWAY(2)), \ | |
| 150 "I" (_IWAY(3))) | |
| 132 #else | 151 #else |
| 133 # error "Unsupported number of ways" | 152 # error "Unsupported number of ways" |
| 134 #endif | 153 #endif |
| 135 | 154 |
| 136 //----------------------------------------------------------------------------- | 155 //----------------------------------------------------------------------------- |
