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comparison packages/hal/sh/arch/current/src/vectors.S @ 99:97d9d85b42c0 ecos-sw-2000-06-07

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Merge from eCos master repository on 2000-06-07-14:25:36-BST
author jlarmour
date Wed, 07 Jun 2000 14:10:34 +0000
parents 489eb5632bc3
children c37d3a9e1b28
comparison
equal deleted inserted replaced
98:51baf00b8bc1 99:97d9d85b42c0
118 mov.b r0,@r1 118 mov.b r0,@r1
119 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources 119 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources
120 mov.w r0,@r1 120 mov.w r0,@r1
121 mov.l $CYGARC_REG_IPRB,r1 121 mov.l $CYGARC_REG_IPRB,r1
122 mov.w r0,@r1 122 mov.w r0,@r1
123 #ifdef CYGARC_SH_MOD_INTC_V2
124 mov.l $CYGARC_REG_IPRC,r1
125 mov.w r0,@r1
126 mov.l $CYGARC_REG_IPRD,r1
127 mov.w r0,@r1
128 mov.l $CYGARC_REG_IPRE,r1
129 mov.w r0,@r1
130 mov.l $CYGARC_REG_ICR1,r1 ! Set interrupt controller to IRQ mode
131 mov.w r0,@r1
132 #endif
123 133
124 # Initialize VBR if necessary 134 # Initialize VBR if necessary
125 #if !defined(CYG_HAL_STARTUP_RAM) || \ 135 #if !defined(CYG_HAL_STARTUP_RAM) || \
126 ( defined(CYG_HAL_STARTUP_RAM) && \ 136 ( defined(CYG_HAL_STARTUP_RAM) && \
127 !defined(CYGSEM_HAL_USE_ROM_MONITOR)) 137 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
232 .long CYGARC_REG_TSTR 242 .long CYGARC_REG_TSTR
233 $CYGARC_REG_IPRA: 243 $CYGARC_REG_IPRA:
234 .long CYGARC_REG_IPRA 244 .long CYGARC_REG_IPRA
235 $CYGARC_REG_IPRB: 245 $CYGARC_REG_IPRB:
236 .long CYGARC_REG_IPRB 246 .long CYGARC_REG_IPRB
247 #ifdef CYGARC_SH_MOD_INTC_V2
248 $CYGARC_REG_IPRC:
249 .long CYGARC_REG_IPRC
250 $CYGARC_REG_IPRD:
251 .long CYGARC_REG_IPRD
252 $CYGARC_REG_IPRE:
253 .long CYGARC_REG_IPRE
254 $CYGARC_REG_ICR1:
255 .long CYGARC_REG_ICR1
256 #endif
257
237 $__reset: 258 $__reset:
238 .long __reset 259 .long __reset
239 260
240 #--------------------------------------------------------------------------- 261 #---------------------------------------------------------------------------
241 # Exception entry 262 # Exception entry
854 #endif 875 #endif
855 $nCYG_SR2: 876 $nCYG_SR2:
856 .long CYG_SR 877 .long CYG_SR
857 $nCYG_SR_BANK1: 878 $nCYG_SR_BANK1:
858 .long CYG_SR_BANK1 879 .long CYG_SR_BANK1
880 #ifdef CYGARC_SH_MOD_INTC_V2
859 $nCYGARC_REG_INTEVT2: 881 $nCYGARC_REG_INTEVT2:
860 .long CYGARC_REG_INTEVT2 882 .long CYGARC_REG_INTEVT2
883 #endif
861 $_hal_interrupt_handlers: 884 $_hal_interrupt_handlers:
862 .long _hal_interrupt_handlers 885 .long _hal_interrupt_handlers
863 $_hal_interrupt_data: 886 $_hal_interrupt_data:
864 .long _hal_interrupt_data 887 .long _hal_interrupt_data
865 $_hal_interrupt_objects: 888 $_hal_interrupt_objects: