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Merge from eCos master repository on 2001-04-06-18:28:36-BST
author jlarmour
date Fri, 06 Apr 2001 19:06:06 +0000
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children f2545e5de153
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156:b939e9cada46 157:b65ec671dd4c
1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
3
4 //=============================================================================
5 //
6 // hal_cache.h
7 //
8 // HAL cache control API
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 //=============================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): nickg, gthomas
38 // Contributors: nickg, gthomas
39 // Date: 1998-09-28
40 // Purpose: Cache control API
41 // Description: The macros defined here provide the HAL APIs for handling
42 // cache control operations.
43 // Usage:
44 // #include <cyg/hal/hal_cache.h>
45 // ...
46 //
47 //
48 //####DESCRIPTIONEND####
49 //
50 //=============================================================================
51
52 #include <cyg/infra/cyg_type.h>
53 #include <cyg/hal/hal_io.h>
54 #include <cyg/hal/plf_io.h>
55
56 //-----------------------------------------------------------------------------
57 // Cache dimensions - one unified cache
58
59 #define HAL_CACHE_UNIFIED
60
61 #define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes
62 #define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line
63 #define HAL_UCACHE_WAYS 2 // Associativity of the cache
64
65 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
66
67 //-----------------------------------------------------------------------------
68 // Global control of cache
69
70 // Enable the cache
71 #define HAL_UCACHE_ENABLE() \
72 CYG_MACRO_START \
73 cyg_uint32 syscfg; \
74 HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
75 syscfg |= E7T_SYSCFG_CE; \
76 HAL_WRITE_UINT32(E7T_SYSCFG, syscfg); \
77 CYG_MACRO_END
78
79
80 // Disable the cache
81 #define HAL_UCACHE_DISABLE() \
82 CYG_MACRO_START \
83 cyg_uint32 syscfg; \
84 HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
85 syscfg &= ~E7T_SYSCFG_CE; \
86 HAL_WRITE_UINT32(E7T_SYSCFG, syscfg); \
87 CYG_MACRO_END
88
89 // Invalidate the entire cache
90 #define HAL_UCACHE_INVALIDATE_ALL() \
91 CYG_MACRO_START \
92 register cyg_uint32* tag = (cyg_uint32*)E7T_CACHE_TAG_ADDR; \
93 int i; \
94 for (i = 0; i < HAL_UCACHE_SETS; i++) \
95 *tag++ = 0; \
96 CYG_MACRO_END
97
98 // Synchronize the contents of the cache with memory.
99 // No action necessary. Cache is write-through.
100 #define HAL_UCACHE_SYNC()
101
102 // Query the state of the cache
103 #define HAL_UCACHE_IS_ENABLED(_state_) \
104 CYG_MACRO_START \
105 cyg_uint32 syscfg; \
106 HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
107 (_state_) = (syscfg & E7T_SYSCFG_CE) ? 1 : 0; \
108 CYG_MACRO_END
109
110 // Purge contents of cache
111 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
112
113 // Set the cache refill burst size
114 //#define HAL_UCACHE_BURST_SIZE(_size_)
115
116 // Set the cache write mode
117 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
118
119 //#define HAL_UCACHE_WRITETHRU_MODE 0
120 //#define HAL_UCACHE_WRITEBACK_MODE 1
121
122 // Load the contents of the given address range into the cache
123 // and then lock the cache so that it stays there.
124 //#define HAL_UCACHE_LOCK(_base_, _size_)
125
126 // Undo a previous lock operation
127 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
128
129 // Unlock entire cache
130 //#define HAL_UCACHE_UNLOCK_ALL()
131
132 //-----------------------------------------------------------------------------
133 // Cache line control
134
135 // Allocate cache lines for the given address range without reading its
136 // contents from memory.
137 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
138
139 // Write dirty cache lines to memory and invalidate the cache entries
140 // for the given address range.
141 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
142
143 // Invalidate cache lines in the given range without writing to memory.
144 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
145
146 // Write dirty cache lines to memory for the given address range.
147 //#define HAL_UCACHE_STORE( _base_ , _size_ )
148
149 // Preread the given range into the cache with the intention of reading
150 // from it later.
151 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
152
153 // Preread the given range into the cache with the intention of writing
154 // to it later.
155 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
156
157 // Allocate and zero the cache lines associated with the given range.
158 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
159
160 //-----------------------------------------------------------------------------
161
162 //-----------------------------------------------------------------------------
163 // Data and instruction cache macros map onto the both-cache macros
164
165 //-----------------------------------------------------------------------------
166 // Global control of data cache
167
168 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
169 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
170 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
171 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
172
173 // Enable the data cache
174 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
175
176 // Disable the data cache
177 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
178
179 // Invalidate the entire cache
180 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
181
182 // Synchronize the contents of the cache with memory.
183 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
184
185 // Query the state of the data cache
186 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
187
188 // Set the data cache refill burst size
189 //#define HAL_DCACHE_BURST_SIZE(_size_)
190
191 // Set the data cache write mode
192 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
193
194 //#define HAL_DCACHE_WRITETHRU_MODE 0
195 //#define HAL_DCACHE_WRITEBACK_MODE 1
196
197 // Load the contents of the given address range into the data cache
198 // and then lock the cache so that it stays there.
199 //#define HAL_DCACHE_LOCK(_base_, _size_)
200
201 // Undo a previous lock operation
202 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
203
204 // Unlock entire cache
205 //#define HAL_DCACHE_UNLOCK_ALL()
206
207 //-----------------------------------------------------------------------------
208 // Data cache line control
209
210 // Allocate cache lines for the given address range without reading its
211 // contents from memory.
212 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
213
214 // Write dirty cache lines to memory and invalidate the cache entries
215 // for the given address range.
216 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
217
218 // Invalidate cache lines in the given range without writing to memory.
219 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
220
221 // Write dirty cache lines to memory for the given address range.
222 //#define HAL_DCACHE_STORE( _base_ , _size_ )
223
224 // Preread the given range into the cache with the intention of reading
225 // from it later.
226 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
227
228 // Preread the given range into the cache with the intention of writing
229 // to it later.
230 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
231
232 // Allocate and zero the cache lines associated with the given range.
233 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
234
235 //-----------------------------------------------------------------------------
236 // Global control of Instruction cache
237
238 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
239 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
240 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
241 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
242
243 // Enable the instruction cache
244 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
245
246 // Disable the instruction cache
247 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
248
249 // Invalidate the entire cache
250 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
251
252
253 // Synchronize the contents of the cache with memory.
254 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
255
256 // Query the state of the instruction cache
257 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
258
259 // Set the instruction cache refill burst size
260 //#define HAL_ICACHE_BURST_SIZE(_size_)
261
262 // Load the contents of the given address range into the instruction cache
263 // and then lock the cache so that it stays there.
264
265 //#define HAL_ICACHE_LOCK(_base_, _size_)
266
267 // Undo a previous lock operation
268 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
269
270 // Unlock entire cache
271 //#define HAL_ICACHE_UNLOCK_ALL()
272
273 //-----------------------------------------------------------------------------
274 // Instruction cache line control
275
276 // Invalidate cache lines in the given range without writing to memory.
277 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
278
279 #endif // ifndef CYGONCE_HAL_CACHE_H
280 // End of hal_cache.h