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comparison packages/hal/powerpc/ppc60x/current/include/var_regs.h @ 70:c5536bad4c24 ecos-sw-2000-02-11

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Merge from eCos master repository on 2000-02-11-15:46:40-GMT
author jlarmour
date Fri, 11 Feb 2000 16:47:32 +0000
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children e0c0827131d1
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69:9a9babddf7e7 70:c5536bad4c24
1 #ifndef CYGONCE_HAL_VAR_REGS_H
2 #define CYGONCE_HAL_VAR_REGS_H
3
4 //==========================================================================
5 //
6 // var_regs.h
7 //
8 // PowerPC 60x variant CPU definitions
9 //
10 //==========================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 //==========================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): jskov
38 // Contributors: jskov
39 // Date: 2000-02-04
40 // Purpose: Provide PPC60x register definitions
41 // Description: Provide PPC60x register definitions
42 // The short difinitions (sans CYGARC_REG_) are exported only
43 // if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
44 // Usage: Included via the acrhitecture register header:
45 // #include <cyg/hal/ppc_regs.h>
46 // ...
47 //
48 //
49 //####DESCRIPTIONEND####
50 //
51 //==========================================================================
52
53 //--------------------------------------------------------------------------
54 // Cache
55 #define CYGARC_REG_HID0 1008
56
57 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
58 #define HID0 CYGARC_REG_HID0
59 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
60
61 //--------------------------------------------------------------------------
62 // BATs
63 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
64 #define IBAT0U 528
65 #define IBAT0L 529
66 #define IBAT1U 530
67 #define IBAT1L 531
68 #define IBAT2U 532
69 #define IBAT2L 533
70 #define IBAT3U 534
71 #define IBAT3L 535
72
73 #define DBAT0U 536
74 #define DBAT0L 537
75 #define DBAT1U 538
76 #define DBAT1L 539
77 #define DBAT2U 540
78 #define DBAT2L 541
79 #define DBAT3U 542
80 #define DBAT3L 543
81
82 #define UBAT_BEPIMASK 0xfffe0000 // effective address mask
83 #define UBAT_BLMASK 0x00001ffc // block length mask
84 #define UBAT_VS 0x00000002 // supervisor mode valid bit
85 #define UBAT_VP 0x00000001 // problem mode valid bit
86
87 #define LBAT_BRPNMASK 0xfffe0000 // real address mask
88 #define LBAT_W 0x00000040 // write-through
89 #define LBAT_I 0x00000020 // caching-inhibited
90 #define LBAT_M 0x00000010 // memory coherence
91 #define LBAT_G 0x00000008 // guarded
92
93 #define LBAT_PP_NA 0x00000000 // no access
94 #define LBAT_PP_RO 0x00000001 // read-only
95 #define LBAT_PP_RW 0x00000002 // read/write
96 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
97
98 //-----------------------------------------------------------------------------
99 #endif // ifdef CYGONCE_HAL_VAR_REGS_H
100 // End of var_regs.h