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comparison packages/hal/arm/sa11x0/sa1100mm/current/src/sa1100mm_misc.c @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 450e4e1f1e80
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133:98d71f4d8243 134:d2f49caf9e38
1 //==========================================================================
2 //
3 // sa1100mm_misc.c
4 //
5 // HAL misc board support code for StrongARM SA1110/Multimedia
6 //
7 //==========================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //==========================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): gthomas
35 // Contributors: hmt, dmoseley
36 // Travis C. Furrer <furrer@mit.edu>
37 // Date: 2000-05-21
38 // Purpose: HAL board support
39 // Description: Implementations of HAL board interfaces
40 //
41 //####DESCRIPTIONEND####
42 //
43 //========================================================================*/
44
45 #include <pkgconf/hal.h>
46 #include <pkgconf/system.h>
47 #include CYGBLD_HAL_PLATFORM_H
48
49 #include <cyg/infra/cyg_type.h> // base types
50 #include <cyg/infra/cyg_trac.h> // tracing macros
51 #include <cyg/infra/cyg_ass.h> // assertion macros
52
53 #include <cyg/hal/hal_io.h> // IO macros
54 #include <cyg/hal/hal_arch.h> // Register state info
55 #include <cyg/hal/hal_diag.h>
56 #include <cyg/hal/hal_intr.h> // Interrupt names
57 #include <cyg/hal/hal_cache.h>
58 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions
59 #include <cyg/hal/sa1100mm.h> // Platform specifics
60
61 #include <cyg/infra/diag.h> // diag_printf
62
63 // -------------------------------------------------------------------------
64 // MMU initialization:
65 //
66 // These structures are laid down in memory to define the translation
67 // table.
68 //
69
70 /*
71 * SA-1100 Translation Table Base Bit Masks */
72 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
73
74 /*
75 * SA-1100 Domain Access Control Bit Masks
76 */
77 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
78 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
79 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
80
81 struct ARM_MMU_FIRST_LEVEL_FAULT {
82 int id : 2;
83 int sbz : 30;
84 };
85 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
86
87 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
88 int id : 2;
89 int imp : 2;
90 int domain : 4;
91 int sbz : 1;
92 int base_address : 23;
93 };
94 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
95
96 struct ARM_MMU_FIRST_LEVEL_SECTION {
97 int id : 2;
98 int b : 1;
99 int c : 1;
100 int imp : 1;
101 int domain : 4;
102 int sbz0 : 1;
103 int ap : 2;
104 int sbz1 : 8;
105 int base_address : 12;
106 };
107 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
108
109 struct ARM_MMU_FIRST_LEVEL_RESERVED {
110 int id : 2;
111 int sbz : 30;
112 };
113 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
114
115 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
116 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
117
118 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
119
120 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
121 cacheable, bufferable, perm) \
122 CYG_MACRO_START \
123 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
124 \
125 desc.word = 0; \
126 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
127 desc.section.domain = 0; \
128 desc.section.c = (cacheable); \
129 desc.section.b = (bufferable); \
130 desc.section.ap = (perm); \
131 desc.section.base_address = (actual_base); \
132 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
133 = desc.word; \
134 CYG_MACRO_END
135
136 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
137 { int i; int j = abase; int k = vbase; \
138 for (i = size; i > 0 ; i--,j++,k++) \
139 { \
140 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
141 } \
142 }
143
144 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
145 unsigned long word;
146 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
147 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
148 struct ARM_MMU_FIRST_LEVEL_SECTION section;
149 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
150 };
151
152 #define ARM_UNCACHEABLE 0
153 #define ARM_CACHEABLE 1
154 #define ARM_UNBUFFERABLE 0
155 #define ARM_BUFFERABLE 1
156
157 #define ARM_ACCESS_PERM_NONE_NONE 0
158 #define ARM_ACCESS_PERM_RO_NONE 0
159 #define ARM_ACCESS_PERM_RO_RO 0
160 #define ARM_ACCESS_PERM_RW_NONE 1
161 #define ARM_ACCESS_PERM_RW_RO 2
162 #define ARM_ACCESS_PERM_RW_RW 3
163
164 void
165 hal_mmu_init(void)
166 {
167 unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
168 unsigned long i;
169
170 /*
171 * Set the TTB register
172 */
173 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
174
175 /*
176 * Set the Domain Access Control Register
177 */
178 i = ARM_ACCESS_TYPE_MANAGER(0) |
179 ARM_ACCESS_TYPE_NO_ACCESS(1) |
180 ARM_ACCESS_TYPE_NO_ACCESS(2) |
181 ARM_ACCESS_TYPE_NO_ACCESS(3) |
182 ARM_ACCESS_TYPE_NO_ACCESS(4) |
183 ARM_ACCESS_TYPE_NO_ACCESS(5) |
184 ARM_ACCESS_TYPE_NO_ACCESS(6) |
185 ARM_ACCESS_TYPE_NO_ACCESS(7) |
186 ARM_ACCESS_TYPE_NO_ACCESS(8) |
187 ARM_ACCESS_TYPE_NO_ACCESS(9) |
188 ARM_ACCESS_TYPE_NO_ACCESS(10) |
189 ARM_ACCESS_TYPE_NO_ACCESS(11) |
190 ARM_ACCESS_TYPE_NO_ACCESS(12) |
191 ARM_ACCESS_TYPE_NO_ACCESS(13) |
192 ARM_ACCESS_TYPE_NO_ACCESS(14) |
193 ARM_ACCESS_TYPE_NO_ACCESS(15);
194 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
195
196 /*
197 * First clear all TT entries - ie Set them to Faulting
198 */
199 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
200
201 /* Actual Virtual Size Attributes Function */
202 /* Base Base MB cached? buffered? access permissions */
203 /* xxx00000 xxx00000 */
204 X_ARM_MMU_SECTION(0x000, 0x500, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
205 X_ARM_MMU_SECTION(0x080, 0x080, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
206 X_ARM_MMU_SECTION(0x100, 0x100, 128, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SA-1101 Development Board Registers */
207 X_ARM_MMU_SECTION(0x180, 0x180, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Ct8020 DSP */
208 X_ARM_MMU_SECTION(0x184, 0x184, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* XBusReg */
209 X_ARM_MMU_SECTION(0x188, 0x188, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegA */
210 X_ARM_MMU_SECTION(0x18C, 0x18C, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SysRegB */
211 X_ARM_MMU_SECTION(0x190, 0x190, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD A */
212 X_ARM_MMU_SECTION(0x194, 0x194, 4, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CPLD B */
213 X_ARM_MMU_SECTION(0x200, 0x200, 512, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets */
214 X_ARM_MMU_SECTION(0xC00, 0, 8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
215 X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
216 X_ARM_MMU_SECTION(0x800, 0x800, 1024, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
217
218 }
219
220 //
221 // Platform specific initialization
222 //
223
224 void
225 plf_hardware_init(void)
226 {
227 }