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comparison packages/hal/mips/tx49/current/include/var_cache.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 6b5f480c6929
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133:98d71f4d8243 134:d2f49caf9e38
1 #ifndef CYGONCE_VAR_CACHE_H
2 #define CYGONCE_VAR_CACHE_H
3
4 //=============================================================================
5 //
6 // var_cache.h
7 //
8 // HAL cache control API
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Red Hat eCos Public License
15 // Version 1.1 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://www.redhat.com/
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Configurable Operating System,
25 // released September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Red Hat.
28 // Portions created by Red Hat are
29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
30 // All Rights Reserved.
31 // -------------------------------------------
32 //
33 //####COPYRIGHTEND####
34 //=============================================================================
35 //#####DESCRIPTIONBEGIN####
36 //
37 // Author(s): nickg
38 // Contributors:nickg, jskov
39 // Date: 2000-05-09
40 // Purpose: Cache control API
41 // Description: The macros defined here provide the HAL APIs for handling
42 // cache control operations.
43 // Usage:
44 // #include <cyg/hal/imp_cache.h>
45 // ...
46 //
47 //
48 //####DESCRIPTIONEND####
49 //
50 //=============================================================================
51
52 #include <pkgconf/hal.h>
53 #include <cyg/infra/cyg_type.h>
54
55 #include <cyg/hal/mips-regs.h>
56
57 #include <cyg/hal/plf_cache.h>
58
59 //=============================================================================
60 // Toshiba TX4955
61
62 #ifdef CYGPKG_HAL_MIPS_TX4955
63
64 //-----------------------------------------------------------------------------
65 // Cache dimensions
66
67 // Data cache
68 #define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes
69 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
70 #define HAL_DCACHE_WAYS 4 // Associativity of the cache
71
72 // Instruction cache
73 #define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes
74 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
75 #define HAL_ICACHE_WAYS 4 // Associativity of the cache
76
77 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
78 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
79
80 //-----------------------------------------------------------------------------
81 // Cache controls
82
83 // Register $16 is Config register (controls cache state)
84
85 // Config Register fields
86 #define CYGARC_REG_CONFIG_ICE 0x00020000 // Instruction cache enable
87 #define CYGARC_REG_CONFIG_DCE 0x00010000 // Data cache enable
88
89
90 //-----------------------------------------------------------------------------
91 // Global control of data cache
92
93 // Enable the data cache
94 // This uses a bit in the config register, which is TX49 specific.
95 #define HAL_DCACHE_ENABLE_DEFINED
96 #define HAL_DCACHE_ENABLE() \
97 CYG_MACRO_START \
98 cyg_uint32 tmp; \
99 asm volatile ("mfc0 %0,$16;" \
100 "and %0,%0,%1;" \
101 "mtc0 %0,$16;" \
102 : "=&r" (tmp) \
103 : "r" (~CYGARC_REG_CONFIG_DCE) \
104 ); \
105 CYG_MACRO_END
106
107 // Disable the data cache
108 #define HAL_DCACHE_DISABLE_DEFINED
109 #define HAL_DCACHE_DISABLE() \
110 CYG_MACRO_START \
111 cyg_uint32 tmp; \
112 asm volatile ("mfc0 %0,$16;" \
113 "or %0,%0,%1;" \
114 "mtc0 %0,$16;" \
115 : "=&r" (tmp) \
116 : "r" (CYGARC_REG_CONFIG_DCE) \
117 ); \
118 CYG_MACRO_END
119
120 #define HAL_DCACHE_IS_ENABLED_DEFINED
121 #define HAL_DCACHE_IS_ENABLED(_state_) \
122 CYG_MACRO_START \
123 cyg_uint32 _cstate_; \
124 asm volatile ( "mfc0 %0,$16\n" \
125 : "=r"(_cstate_) \
126 ); \
127 if( _cstate_ & CYGARC_REG_CONFIG_DCE) \
128 _state_ = 0; \
129 else \
130 _state_ = 1; \
131 CYG_MACRO_END
132
133 // Architecture HAL defines other operations
134
135
136 //-----------------------------------------------------------------------------
137 // Global control of Instruction cache
138
139 // Enable the instruction cache
140 #define HAL_ICACHE_ENABLE_DEFINED
141 #define HAL_ICACHE_ENABLE() \
142 CYG_MACRO_START \
143 cyg_uint32 tmp; \
144 asm volatile ("mfc0 %0,$16;" \
145 "and %0,%0,%1;" \
146 "mtc0 %0,$16;" \
147 : "=&r" (tmp) \
148 : "r" (~CYGARC_REG_CONFIG_ICE) \
149 ); \
150 CYG_MACRO_END
151
152 // Disable the instruction cache
153 #define HAL_ICACHE_DISABLE_DEFINED
154 #define HAL_ICACHE_DISABLE() \
155 CYG_MACRO_START \
156 cyg_uint32 tmp; \
157 asm volatile ("mfc0 %0,$16;" \
158 "or %0,%0,%1;" \
159 "mtc0 %0,$16;" \
160 : "=&r" (tmp) \
161 : "r" (CYGARC_REG_CONFIG_ICE) \
162 ); \
163 CYG_MACRO_END
164
165 #define HAL_ICACHE_IS_ENABLED_DEFINED
166 #define HAL_ICACHE_IS_ENABLED(_state_) \
167 CYG_MACRO_START \
168 cyg_uint32 _cstate_; \
169 asm volatile ( "mfc0 %0,$16\n" \
170 : "=r"(_cstate_) \
171 ); \
172 if( _cstate_ & CYGARC_REG_CONFIG_ICE) \
173 _state_ = 0; \
174 else \
175 _state_ = 1; \
176 CYG_MACRO_END
177
178 // TX49 cache instruction must not affect the line it executes out of,
179 // so disable instruction cache before invalidating it.
180 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
181 #define HAL_ICACHE_INVALIDATE_ALL() \
182 CYG_MACRO_START \
183 register CYG_ADDRESS _baddr_ = 0x80000000; \
184 register CYG_ADDRESS _addr_ = 0x80000000; \
185 register CYG_WORD _state_; \
186 _HAL_ASM_SET_MIPS_ISA(3); \
187 HAL_ICACHE_IS_ENABLED( _state_ ); \
188 HAL_ICACHE_DISABLE(); \
189 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
190 { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
191 if( _state_ ) HAL_ICACHE_ENABLE(); \
192 _HAL_ASM_SET_MIPS_ISA(0); \
193 CYG_MACRO_END
194
195 // Architecture HAL defines other operations
196
197 #endif // CYGPKG_HAL_MIPS_TX4955
198
199
200 //-----------------------------------------------------------------------------
201 #endif // ifndef CYGONCE_VAR_CACHE_H
202 // End of var_cache.h