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comparison packages/hal/sh/sh3/current/include/mod_regs_bsc.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children e0c0827131d1
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133:98d71f4d8243 134:d2f49caf9e38
1 //=============================================================================
2 //
3 // mod_regs_bsc.h
4 //
5 // BSC (bus state controller) Module register definitions
6 //
7 //=============================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //=============================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors:jskov
36 // Date: 2000-10-30
37 //
38 //####DESCRIPTIONEND####
39 //
40 //=============================================================================
41
42 //--------------------------------------------------------------------------
43 // Register definitions
44 #define CYGARC_REG_BCR1 0xffffff60
45 #define CYGARC_REG_BCR2 0xffffff62
46 #define CYGARC_REG_WCR1 0xffffff64
47 #define CYGARC_REG_WCR2 0xffffff66
48 #define CYGARC_REG_MCR 0xffffff68
49 #define CYGARC_REG_DCR 0xffffff6a
50 #define CYGARC_REG_PCR 0xffffff6c
51 #define CYGARC_REG_RTCSR 0xffffff6e
52 #define CYGARC_REG_RTCNT 0xffffff70
53 #define CYGARC_REG_RTCOR 0xffffff72
54 #define CYGARC_REG_RFCR 0xffffff74
55
56 #define CYGARC_REG_SDMR_AREA2_BASE 0xffffd000
57 #define CYGARC_REG_SDMR_AREA3_BASE 0xffffe000
58
59 #define CYGARC_REG_BCR1_DRAMTP2 0x0010
60 #define CYGARC_REG_BCR1_DRAMTP1 0x0008
61 #define CYGARC_REG_BCR1_DRAMTP0 0x0004
62
63 // Bus widths for areas
64 #define CYGARC_REG_BCR2_A6_8 0x1000
65 #define CYGARC_REG_BCR2_A6_16 0x2000
66 #define CYGARC_REG_BCR2_A6_32 0x3000
67 #define CYGARC_REG_BCR2_A5_8 0x0400
68 #define CYGARC_REG_BCR2_A5_16 0x0800
69 #define CYGARC_REG_BCR2_A5_32 0x0c00
70 #define CYGARC_REG_BCR2_A4_8 0x0100
71 #define CYGARC_REG_BCR2_A4_16 0x0200
72 #define CYGARC_REG_BCR2_A4_32 0x0300
73 #define CYGARC_REG_BCR2_A3_8 0x0040
74 #define CYGARC_REG_BCR2_A3_16 0x0080
75 #define CYGARC_REG_BCR2_A3_32 0x00c0
76 #define CYGARC_REG_BCR2_A2_8 0x0010
77 #define CYGARC_REG_BCR2_A2_16 0x0020
78 #define CYGARC_REG_BCR2_A2_32 0x0030
79
80 // Memory type selection and other IO behavior controls
81 #define CYGARC_REG_BCR1_PULA 0x8000 // Pin A25 to A0 Pull-Up
82 #define CYGARC_REG_BCR1_PULD 0x4000 // Pin D31 to D0 Pull-Up
83 #define CYGARC_REG_BCR1_HIZMEM 0x2000 // Hi-Z memory control
84 #define CYGARC_REG_BCR1_HIZCNT 0x1000 // High-Z Control
85 #define CYGARC_REG_BCR1_ENDIAN 0x0800 // Endian Flag
86 #define CYGARC_REG_BCR1_A0_BST_MASK 0x0600 // Area 0 Burst ROM Control
87 #define CYGARC_REG_BCR1_A0_BST_4 0x0200
88 #define CYGARC_REG_BCR1_A0_BST_8 0x0400
89 #define CYGARC_REG_BCR1_A0_BST_16 0x0600
90 #define CYGARC_REG_BCR1_A5_BST_MASK 0x0180 // Area 5 Burst ROM Control
91 #define CYGARC_REG_BCR1_A5_BST_4 0x0080
92 #define CYGARC_REG_BCR1_A5_BST_8 0x0100
93 #define CYGARC_REG_BCR1_A5_BST_16 0x0180
94 #define CYGARC_REG_BCR1_A6_BST_MASK 0x0060 // Area 6 Burst ROM Control
95 #define CYGARC_REG_BCR1_A6_BST_4 0x0020
96 #define CYGARC_REG_BCR1_A6_BST_8 0x0040
97 #define CYGARC_REG_BCR1_A6_BST_16 0x0060
98 #define CYGARC_REG_BCR1_DRAMTP_MASK 0x001c // Area 2, Area 3 Memory Type
99 #define CYGARC_REG_BCR1_A5PCM 0x0002 // Area 5 Bus Type
100 #define CYGARC_REG_BCR1_A6PCM 0x0001 // Area 6 Bus Type
101
102 // Intercycle wait states
103 #define CYGARC_REG_WCR1_WAITSEL 0x8000 // WAIT Sampling Timing Select
104 #define CYGARC_REG_WCR1_A6I_MASK 0x3000 // Intercycle Idle Specification
105 #define CYGARC_REG_WCR1_A6I_SHIFT 12
106 #define CYGARC_REG_WCR1_A5I_MASK 0x0c00
107 #define CYGARC_REG_WCR1_A5I_SHIFT 10
108 #define CYGARC_REG_WCR1_A4I_MASK 0x0300
109 #define CYGARC_REG_WCR1_A4I_SHIFT 8
110 #define CYGARC_REG_WCR1_A3I_MASK 0x00c0
111 #define CYGARC_REG_WCR1_A3I_SHIFT 6
112 #define CYGARC_REG_WCR1_A2I_MASK 0x0030
113 #define CYGARC_REG_WCR1_A2I_SHIFT 4
114 #define CYGARC_REG_WCR1_A0I_MASK 0x0003
115 #define CYGARC_REG_WCR1_A0I_SHIFT 0
116
117 #define CYGARC_REG_WCR1_0WS 0
118 #define CYGARC_REG_WCR1_1WS 1
119 #define CYGARC_REG_WCR1_2WS 2
120 #define CYGARC_REG_WCR1_3WS 3
121
122
123 // Wait states
124 #define CYGARC_REG_WCR2_A6_MASK 0xe000 // Wait states + burst pitch
125 #define CYGARC_REG_WCR2_A6_SHIFT 13
126 #define CYGARC_REG_WCR2_A5_MASK 0x1c00 // Wait states + burst pitch
127 #define CYGARC_REG_WCR2_A5_SHIFT 10
128 #define CYGARC_REG_WCR2_A4_MASK 0x0380 // Wait states
129 #define CYGARC_REG_WCR2_A4_SHIFT 7
130 #define CYGARC_REG_WCR2_A3_MASK 0x0060 // Wait states / CAS latency
131 #define CYGARC_REG_WCR2_A3_SHIFT 5
132 #define CYGARC_REG_WCR2_A2_MASK 0x0018 // Wait states / CAS latency
133 #define CYGARC_REG_WCR2_A2_SHIFT 3
134 #define CYGARC_REG_WCR2_A0_MASK 0x0007 // Wait states + burst pitch
135 #define CYGARC_REG_WCR2_A0_SHIFT 0
136
137 #define CYGARC_REG_WCR2_0WS 0
138 #define CYGARC_REG_WCR2_1WS 1
139 #define CYGARC_REG_WCR2_2WS 2
140 #define CYGARC_REG_WCR2_3WS 3
141 #define CYGARC_REG_WCR2_4WS 4
142 #define CYGARC_REG_WCR2_6WS 5
143 #define CYGARC_REG_WCR2_8WS 6
144 #define CYGARC_REG_WCR2_10WS 7
145
146 //--------------------------------------------------------------------------
147 // Additional type definitions
148 #if (CYGARC_SH_MOD_BCN > 1)
149 # define CYGARC_REG_BCR3 0xffffff7e
150 #endif
151
152
153
154 //-----------------------------------------------------------------------------
155 // Calculate constants needed to drive the proper SDRAM refresh rate. Argument
156 // is delay between required refresh events in microseconds (us). Should be
157 // available off the SDRAM spec sheet.
158 // These should be a part of a fully CDLicized memory controller setup.
159 #define CYGARC_RTCSR_PRESCALE(_r_) \
160 (((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \
161 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \
162 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \
163 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \
164 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \
165 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096)
166
167 // These two macros provide the static values we need to stuff into the
168 // registers.
169 #define CYGARC_RTCSR_CKSx(_r_) \
170 (( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \
171 ( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \
172 ( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \
173 ( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \
174 (1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \
175 (2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 )
176
177 #define CYGARC_RTCSR_N(_r_) \
178 (CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000))
179
180