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comparison packages/hal/sh/sh3/current/src/var_misc.c @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children a9ac27ec7abc
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133:98d71f4d8243 134:d2f49caf9e38
1 //==========================================================================
2 //
3 // var_misc.c
4 //
5 // HAL miscellaneous functions
6 //
7 //==========================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //==========================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors: jskov, jlarmour, nickg
36 // Date: 1999-04-03
37 // Purpose: HAL miscellaneous functions
38 // Description: This file contains miscellaneous functions provided by the
39 // HAL.
40 //
41 //####DESCRIPTIONEND####
42 //
43 //===========================================================================
44
45 #include <pkgconf/hal.h>
46
47 #include <cyg/infra/cyg_type.h>
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
50 #include <cyg/infra/diag.h> // diag_printf
51
52 #include <cyg/hal/hal_arch.h> // HAL header
53 #include <cyg/hal/hal_cache.h> // HAL cache
54 #include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions
55
56 //---------------------------------------------------------------------------
57 // Initial cache enabling
58
59 #ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK
60 # define CACHE_MODE_P0 0
61 #else
62 # define CACHE_MODE_P0 CYGARC_REG_CCR_WT
63 #endif
64
65 #ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK
66 # define CACHE_MODE_P1 CYGARC_REG_CCR_CB
67 #else
68 # define CACHE_MODE_P1 0
69 #endif
70
71 externC void
72 cyg_var_enable_caches(void)
73 {
74 // Initialize cache.
75 HAL_UCACHE_INVALIDATE_ALL();
76
77 // Set cache modes
78 HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1);
79
80 #ifdef CYGHWR_HAL_SH_CACHE_ENABLE
81 // Enable cache.
82 HAL_UCACHE_ENABLE();
83 #endif
84 }
85
86 //---------------------------------------------------------------------------
87 void
88 hal_variant_init(void)
89 {
90 }
91
92 //---------------------------------------------------------------------------
93 // Interrupt function support
94
95 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
96 externC cyg_uint8 cyg_hal_ILVL_table[];
97 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_) \
98 /* Update the ILVL table, so it is easy for the interrupt entry */ \
99 /* code to find out the level of a given interrupt source. */ \
100 cyg_hal_ILVL_table[(_vector_)] = (_level_)
101 #else
102 #define HAL_UPDATE_ILVL_TABLE(_vector_, _level_)
103 #endif
104
105 void
106 hal_interrupt_set_level(int vector, int level)
107 {
108 cyg_uint16 iprX;
109
110 CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");
111 CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
112 && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");
113
114 HAL_UPDATE_ILVL_TABLE(vector, level);
115
116 switch( (vector) ) {
117 case CYGNUM_HAL_INTERRUPT_NMI:
118 /* fall through */
119 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:
120 /* Cannot change levels */
121 break;
122
123 /* IPRA */
124 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0:
125 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
126 iprX &= ~CYGARC_REG_IPRA_TMU0_MASK;
127 iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1;
128 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
129 break;
130 case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1:
131 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
132 iprX &= ~CYGARC_REG_IPRA_TMU1_MASK;
133 iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1;
134 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
135 break;
136 case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2:
137 case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2:
138 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
139 iprX &= ~CYGARC_REG_IPRA_TMU2_MASK;
140 iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1;
141 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
142 break;
143 case CYGNUM_HAL_INTERRUPT_RTC_ATI:
144 case CYGNUM_HAL_INTERRUPT_RTC_PRI:
145 case CYGNUM_HAL_INTERRUPT_RTC_CUI:
146 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
147 iprX &= ~CYGARC_REG_IPRA_RTC_MASK;
148 iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1;
149 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
150 break;
151
152 /* IPRB */
153 case CYGNUM_HAL_INTERRUPT_SCI_ERI:
154 case CYGNUM_HAL_INTERRUPT_SCI_RXI:
155 case CYGNUM_HAL_INTERRUPT_SCI_TXI:
156 case CYGNUM_HAL_INTERRUPT_SCI_TEI:
157 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
158 iprX &= ~CYGARC_REG_IPRB_SCI_MASK;
159 iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1;
160 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
161 break;
162 case CYGNUM_HAL_INTERRUPT_WDT_ITI:
163 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
164 iprX &= ~CYGARC_REG_IPRB_WDT_MASK;
165 iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1;
166 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
167 break;
168 case CYGNUM_HAL_INTERRUPT_REF_RCMI:
169 case CYGNUM_HAL_INTERRUPT_REF_ROVI:
170 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
171 iprX &= ~CYGARC_REG_IPRB_REF_MASK;
172 iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1;
173 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
174 break;
175
176 #if (CYGARC_SH_MOD_INTC >= 2)
177 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
178 /* IPRC */
179 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
180 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
181 iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK;
182 iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1;
183 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
184 break;
185 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
186 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
187 iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK;
188 iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1;
189 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
190 break;
191 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
192 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
193 iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK;
194 iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1;
195 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
196 break;
197 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
198 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
199 iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK;
200 iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1;
201 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
202 break;
203 #endif
204 /* IPRD */
205 case CYGNUM_HAL_INTERRUPT_PINT_PINT07:
206 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
207 iprX &= ~CYGARC_REG_IPRD_PINT07_MASK;
208 iprX |= (level)*CYGARC_REG_IPRD_PINT07_PRI1;
209 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
210 break;
211 case CYGNUM_HAL_INTERRUPT_PINT_PINT8F:
212 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
213 iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK;
214 iprX |= (level)*CYGARC_REG_IPRD_PINT8F_PRI1;
215 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
216 break;
217 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
218 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
219 iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK;
220 iprX |= (level)*CYGARC_REG_IPRD_IRQ5_PRI1;
221 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
222 break;
223 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
224 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
225 iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK;
226 iprX |= (level)*CYGARC_REG_IPRD_IRQ4_PRI1;
227 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
228 break;
229
230 /* IPRE */
231 case CYGNUM_HAL_INTERRUPT_DMAC_DEI0:
232 case CYGNUM_HAL_INTERRUPT_DMAC_DEI1:
233 case CYGNUM_HAL_INTERRUPT_DMAC_DEI2:
234 case CYGNUM_HAL_INTERRUPT_DMAC_DEI3:
235 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
236 iprX &= ~CYGARC_REG_IPRE_DMAC_MASK;
237 iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1;
238 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
239 break;
240 case CYGNUM_HAL_INTERRUPT_IRDA_ERI1:
241 case CYGNUM_HAL_INTERRUPT_IRDA_RXI1:
242 case CYGNUM_HAL_INTERRUPT_IRDA_BRI1:
243 case CYGNUM_HAL_INTERRUPT_IRDA_TXI1:
244 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
245 iprX &= ~CYGARC_REG_IPRE_IRDA_MASK;
246 iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1;
247 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
248 break;
249 case CYGNUM_HAL_INTERRUPT_SCIF_ERI2:
250 case CYGNUM_HAL_INTERRUPT_SCIF_RXI2:
251 case CYGNUM_HAL_INTERRUPT_SCIF_BRI2:
252 case CYGNUM_HAL_INTERRUPT_SCIF_TXI2:
253 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
254 iprX &= ~CYGARC_REG_IPRE_SCIF_MASK;
255 iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1;
256 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
257 break;
258 case CYGNUM_HAL_INTERRUPT_ADC_ADI:
259 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
260 iprX &= ~CYGARC_REG_IPRE_ADC_MASK;
261 iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1;
262 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
263 break;
264 #endif // (CYGARC_SH_MOD_INTC >= 2)
265
266 #if (CYGARC_SH_MOD_INTC >= 3)
267 /* IPRF */
268 case CYGNUM_HAL_INTERRUPT_LCDC_LCDI:
269 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
270 iprX &= ~CYGARC_REG_IPRF_LCDI_MASK;
271 iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1;
272 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
273 break;
274 case CYGNUM_HAL_INTERRUPT_PCC_PCC0:
275 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
276 iprX &= ~CYGARC_REG_IPRF_PCC0_MASK;
277 iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1;
278 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
279 break;
280 case CYGNUM_HAL_INTERRUPT_PCC_PCC1:
281 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
282 iprX &= ~CYGARC_REG_IPRF_PCC1_MASK;
283 iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1;
284 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
285 break;
286 #endif // (CYGARC_SH_MOD_INTC >= 3)
287
288 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
289 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
290 /* Do nothing for these reserved vectors. */
291 break;
292
293 default:
294 CYG_FAIL("Unknown interrupt vector");
295 break;
296 }
297 }
298
299 void
300 hal_interrupt_mask(int vector)
301 {
302 switch( (vector) ) {
303 case CYGNUM_HAL_INTERRUPT_NMI:
304 /* fall through */
305 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:
306 /* Can only be masked by fiddling Imask in SR. */
307 break;
308 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX:
309 HAL_INTERRUPT_SET_LEVEL((vector), 0);
310 break;
311 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
312 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
313 /* Do nothing for these reserved vectors. */
314 break;
315 default:
316 CYG_FAIL("Unknown interrupt vector");
317 break;
318 }
319 }
320
321 void
322 hal_interrupt_unmask(int vector)
323 {
324 switch( (vector) ) {
325 case CYGNUM_HAL_INTERRUPT_NMI:
326 /* fall through */
327 case CYGNUM_HAL_INTERRUPT_LVL0...CYGNUM_HAL_INTERRUPT_LVL14:
328 /* Can only be unmasked by fiddling Imask in SR. */
329 break;
330 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0...CYGNUM_HAL_ISR_MAX:
331 HAL_INTERRUPT_SET_LEVEL((vector), 1);
332 break;
333 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
334 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
335 /* Do nothing for these reserved vectors. */
336 break;
337 default:
338 CYG_FAIL("Unknown interrupt vector");
339 break;
340 }
341 }
342
343 void
344 hal_interrupt_acknowledge(int vector)
345 {
346 #if (CYGARC_SH_MOD_INTC >= 2)
347 if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
348 && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
349
350 cyg_uint8 irr0;
351
352 HAL_READ_UINT8(CYGARC_REG_IRR0, irr0);
353 switch ( vector ) {
354 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
355 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
356 irr0 &= ~CYGARC_REG_IRR0_IRQ0;
357 break;
358 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
359 irr0 &= ~CYGARC_REG_IRR0_IRQ1;
360 break;
361 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
362 irr0 &= ~CYGARC_REG_IRR0_IRQ2;
363 break;
364 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
365 irr0 &= ~CYGARC_REG_IRR0_IRQ3;
366 break;
367 #endif
368 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
369 irr0 &= ~CYGARC_REG_IRR0_IRQ4;
370 break;
371 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
372 irr0 &= ~CYGARC_REG_IRR0_IRQ5;
373 break;
374 default:
375 CYG_FAIL("Unhandled interrupt vector");
376 }
377 HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0);
378 }
379 #endif
380 }
381
382 // Note: The PINTs can be masked and configured individually, even
383 // though there are only two vectors. Maybe add some fake vectors just
384 // for masking/configuring?
385 void
386 hal_interrupt_configure(int vector, int level, int up)
387 {
388 #if (CYGARC_SH_MOD_INTC >= 2)
389 if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
390 && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
391
392 cyg_uint16 icr1, ss, mask;
393 ss = 0;
394 mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;
395 if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;
396 if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;
397 CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
398
399 switch( (vector) ) {
400 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
401 ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
402 mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
403 break;
404 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
405 ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
406 mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
407 break;
408 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
409 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
410 ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
411 mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
412 break;
413 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
414 ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
415 mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
416 break;
417 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
418 ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
419 mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
420 break;
421 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
422 ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
423 mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
424 break;
425 #endif
426 default:
427 CYG_FAIL("Unhandled interrupt vector");
428 }
429
430 HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);
431 icr1 &= ~mask;
432 icr1 |= ss;
433 HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);
434 }
435 #endif
436 }
437
438 //---------------------------------------------------------------------------
439 // End of hal_misc.c