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comparison packages/hal/sh/sh4/current/include/mod_regs_bsc.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 42f843b391aa
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133:98d71f4d8243 134:d2f49caf9e38
1 //=============================================================================
2 //
3 // mod_regs_bsc.h
4 //
5 // BSC (bus state controller) Module register definitions
6 //
7 //=============================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //=============================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors:jskov
36 // Date: 2000-10-30
37 //
38 //####DESCRIPTIONEND####
39 //
40 //=============================================================================
41
42 //--------------------------------------------------------------------------
43 // Register definitions
44 #define CYGARC_REG_BCR1 0xFF800000
45 #define CYGARC_REG_BCR2 0xFF800004
46 #define CYGARC_REG_WCR1 0xFF800008
47 #define CYGARC_REG_WCR2 0xFF80000C
48 #define CYGARC_REG_WCR3 0xFF800010
49 #define CYGARC_REG_MCR 0xFF800014
50 #define CYGARC_REG_PCR 0xFF800018
51 #define CYGARC_REG_RTCSR 0xFF80001C
52 #define CYGARC_REG_RTCNT 0xFF800020
53 #define CYGARC_REG_RTCOR 0xFF800024
54 #define CYGARC_REG_RFCR 0xFF800028
55
56 #define CYGARC_REG_SDMR2 0xFF90008c
57
58 #define CYGARC_REG_SDMR_AREA2_BASE 0xff900000
59 #define CYGARC_REG_SDMR_AREA3_BASE 0xff940000
60
61 #define CYGARC_REG_BCR1_DRAMTP2 0x0010
62 #define CYGARC_REG_BCR1_DRAMTP1 0x0008
63 #define CYGARC_REG_BCR1_DRAMTP0 0x0004
64
65 // Bus widths for areas
66 #define CYGARC_REG_BCR2_A6_8 0x1000
67 #define CYGARC_REG_BCR2_A6_16 0x2000
68 #define CYGARC_REG_BCR2_A6_32 0x3000
69 #define CYGARC_REG_BCR2_A5_8 0x0400
70 #define CYGARC_REG_BCR2_A5_16 0x0800
71 #define CYGARC_REG_BCR2_A5_32 0x0c00
72 #define CYGARC_REG_BCR2_A4_8 0x0100
73 #define CYGARC_REG_BCR2_A4_16 0x0200
74 #define CYGARC_REG_BCR2_A4_32 0x0300
75 #define CYGARC_REG_BCR2_A3_8 0x0040
76 #define CYGARC_REG_BCR2_A3_16 0x0080
77 #define CYGARC_REG_BCR2_A3_32 0x00c0
78 #define CYGARC_REG_BCR2_A2_8 0x0010
79 #define CYGARC_REG_BCR2_A2_16 0x0020
80 #define CYGARC_REG_BCR2_A2_32 0x0030
81
82 // Memory type selection and other IO behavior controls
83 #define CYGARC_REG_BCR1_PULA 0x8000 // Pin A25 to A0 Pull-Up
84 #define CYGARC_REG_BCR1_PULD 0x4000 // Pin D31 to D0 Pull-Up
85 #define CYGARC_REG_BCR1_HIZMEM 0x2000 // Hi-Z memory control
86 #define CYGARC_REG_BCR1_HIZCNT 0x1000 // High-Z Control
87 #define CYGARC_REG_BCR1_ENDIAN 0x0800 // Endian Flag
88 #define CYGARC_REG_BCR1_A0_BST_MASK 0x0600 // Area 0 Burst ROM Control
89 #define CYGARC_REG_BCR1_A0_BST_4 0x0200
90 #define CYGARC_REG_BCR1_A0_BST_8 0x0400
91 #define CYGARC_REG_BCR1_A0_BST_16 0x0600
92 #define CYGARC_REG_BCR1_A5_BST_MASK 0x0180 // Area 5 Burst ROM Control
93 #define CYGARC_REG_BCR1_A5_BST_4 0x0080
94 #define CYGARC_REG_BCR1_A5_BST_8 0x0100
95 #define CYGARC_REG_BCR1_A5_BST_16 0x0180
96 #define CYGARC_REG_BCR1_A6_BST_MASK 0x0060 // Area 6 Burst ROM Control
97 #define CYGARC_REG_BCR1_A6_BST_4 0x0020
98 #define CYGARC_REG_BCR1_A6_BST_8 0x0040
99 #define CYGARC_REG_BCR1_A6_BST_16 0x0060
100 #define CYGARC_REG_BCR1_DRAMTP_MASK 0x001c // Area 2, Area 3 Memory Type
101 #define CYGARC_REG_BCR1_A5PCM 0x0002 // Area 5 Bus Type
102 #define CYGARC_REG_BCR1_A6PCM 0x0001 // Area 6 Bus Type
103
104 // Intercycle wait states
105 #define CYGARC_REG_WCR1_WAITSEL 0x8000 // WAIT Sampling Timing Select
106 #define CYGARC_REG_WCR1_A6I_MASK 0x3000 // Intercycle Idle Specification
107 #define CYGARC_REG_WCR1_A6I_SHIFT 12
108 #define CYGARC_REG_WCR1_A5I_MASK 0x0c00
109 #define CYGARC_REG_WCR1_A5I_SHIFT 10
110 #define CYGARC_REG_WCR1_A4I_MASK 0x0300
111 #define CYGARC_REG_WCR1_A4I_SHIFT 8
112 #define CYGARC_REG_WCR1_A3I_MASK 0x00c0
113 #define CYGARC_REG_WCR1_A3I_SHIFT 6
114 #define CYGARC_REG_WCR1_A2I_MASK 0x0030
115 #define CYGARC_REG_WCR1_A2I_SHIFT 4
116 #define CYGARC_REG_WCR1_A0I_MASK 0x0003
117 #define CYGARC_REG_WCR1_A0I_SHIFT 0
118
119 #define CYGARC_REG_WCR1_0WS 0
120 #define CYGARC_REG_WCR1_1WS 1
121 #define CYGARC_REG_WCR1_2WS 2
122 #define CYGARC_REG_WCR1_3WS 3
123
124
125 // Wait states
126 #define CYGARC_REG_WCR2_A6_MASK 0xe000 // Wait states + burst pitch
127 #define CYGARC_REG_WCR2_A6_SHIFT 13
128 #define CYGARC_REG_WCR2_A5_MASK 0x1c00 // Wait states + burst pitch
129 #define CYGARC_REG_WCR2_A5_SHIFT 10
130 #define CYGARC_REG_WCR2_A4_MASK 0x0380 // Wait states
131 #define CYGARC_REG_WCR2_A4_SHIFT 7
132 #define CYGARC_REG_WCR2_A3_MASK 0x0060 // Wait states / CAS latency
133 #define CYGARC_REG_WCR2_A3_SHIFT 5
134 #define CYGARC_REG_WCR2_A2_MASK 0x0018 // Wait states / CAS latency
135 #define CYGARC_REG_WCR2_A2_SHIFT 3
136 #define CYGARC_REG_WCR2_A0_MASK 0x0007 // Wait states + burst pitch
137 #define CYGARC_REG_WCR2_A0_SHIFT 0
138
139 #define CYGARC_REG_WCR2_0WS 0
140 #define CYGARC_REG_WCR2_1WS 1
141 #define CYGARC_REG_WCR2_2WS 2
142 #define CYGARC_REG_WCR2_3WS 3
143 #define CYGARC_REG_WCR2_4WS 4
144 #define CYGARC_REG_WCR2_6WS 5
145 #define CYGARC_REG_WCR2_8WS 6
146 #define CYGARC_REG_WCR2_10WS 7
147
148
149
150 //-----------------------------------------------------------------------------
151 // Calculate constants needed to drive the proper SDRAM refresh rate. Argument
152 // is delay between required refresh events in microseconds (us). Should be
153 // available off the SDRAM spec sheet.
154 // These should be a part of a fully CDLicized memory controller setup.
155 #define CYGARC_RTCSR_PRESCALE(_r_) \
156 (((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \
157 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \
158 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \
159 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \
160 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \
161 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096)
162
163 // These two macros provide the static values we need to stuff into the
164 // registers.
165 #define CYGARC_RTCSR_CKSx(_r_) \
166 (( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \
167 ( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \
168 ( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \
169 ( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \
170 (1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \
171 (2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 )
172
173 #define CYGARC_RTCSR_N(_r_) \
174 (CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000))
175
176