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diff packages/hal/powerpc/arch/current/src/vectors.S @ 34:29bc183297e1 ecos-sw-1999-09-02

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Merge from eCos master repository on 1999-09-02-16:26:10-BST
author jlarmour
date Thu, 02 Sep 1999 16:11:22 +0000
parents 5af43b635655
children e97d78785e2d
line wrap: on
line diff
--- a/packages/hal/powerpc/arch/current/src/vectors.S
+++ b/packages/hal/powerpc/arch/current/src/vectors.S
@@ -92,6 +92,8 @@
 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR))
 #endif
 
+#define CYG_MSR_NO_INTS (CYG_MSR & ~MSR_ME)        
+
 #===========================================================================
 # If the following option is enabled, we only save registers up to R12.
 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
@@ -383,7 +385,7 @@ 2:
         bl      hal_MMU_init
 
         # Enable MMU it so we can safely enable caches.
-        lwi     r3,CYG_MSR
+        lwi     r3,CYG_MSR_NO_INTS              # interrupts enabled later
         sync
         mtmsr   r3
         sync
@@ -444,7 +446,7 @@ 9:
         stw     r5,ppcreg_lr(r1)        # stash LR
 
         # Enable MMU.
-        lwi     r3,CYG_MSR
+        lwi     r3,CYG_MSR_NO_INTS
         sync
         mtmsr   r3
         sync
@@ -588,7 +590,7 @@ 0:      stw     \dreg,ppcreg_vector(\sta
         stw     r5,ppcreg_lr(r1)        # stash LR
 
         # Enable MMU.
-        lwi     r3,CYG_MSR
+        lwi     r3,CYG_MSR_NO_INTS
         sync
         mtmsr   r3
         sync
@@ -821,7 +823,7 @@ restore_state:
 
         mtcr    r3                      # set ccr
         
-        lwi     r3,CYG_MSR              # do rest with ints disabled
+        lwi     r3,CYG_MSR_NO_INTS      # do rest with ints disabled
         sync
         mtmsr   r3
         sync