Mercurial > flash_v2
diff packages/hal/mips/arch/current/include/arch.inc @ 24:306eee292492 ecos-sw-1999-07-16
Merge from eCos master repository on 1999-07-16-05:47:06-BST
| author | jlarmour |
|---|---|
| date | Fri, 16 Jul 1999 21:54:32 +0000 |
| parents | 7253dcc42a09 |
| children | 4741a3c3496a |
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--- a/packages/hal/mips/arch/current/include/arch.inc +++ b/packages/hal/mips/arch/current/include/arch.inc @@ -111,8 +111,8 @@ #endif #define mipsreg_pc (mipsreg_vector+mips_regsize) #define mipsreg_sr (mipsreg_pc+mips_regsize) -#define mipsreg_cache (mipsreg_sr+mips_regsize) -#define mipsreg_cause (mipsreg_cache+mips_regsize) +#define mipsreg_cachectrl (mipsreg_sr+mips_regsize) +#define mipsreg_cause (mipsreg_cachectrl+mips_regsize) #define mipsreg_badvr (mipsreg_cause+mips_regsize) #define mipsreg_prid (mipsreg_badvr+mips_regsize) #define mipsreg_config (mipsreg_prid+mips_regsize) @@ -536,6 +536,33 @@ hal_intc_translation_table: nop nop nop + + .set mips3 # Set ISA to MIPS 3 to allow cache insns + + # Now ensure the caches are invalidated - may be applicable if the + # target has soft-reset + # D-cache: + la a0,0x80000000 + addi a1,a0,0x2000 +1: + cache 0x01,0(a0) + addi a0,a0,0x10 + sub v0,a1,a0 + bgez v0,1b + nop # delay slot + + # I-cache: + la a0,0x80000000 + addi a1,a0,0x4000 +1: + cache 0x00,0(a0) + addi a0,a0,0x20 + sub v0,a1,a0 + bgez v0,1b + nop # delay slot + + .set mips0 # reset ISA to default + .endm #endif