new file mode 100644
--- /dev/null
+++ b/packages/devs/serial/powerpc/cogent/current/src/cogent_serial.h
@@ -0,0 +1,204 @@
+//==========================================================================
+//
+//      io/serial/powerpc/cogent_serial.h
+//
+//      PowerPC Cogent Serial I/O definitions.
+//
+//==========================================================================
+//####COPYRIGHTBEGIN####
+//                                                                          
+// -------------------------------------------                              
+// The contents of this file are subject to the Red Hat eCos Public License 
+// Version 1.1 (the "License"); you may not use this file except in         
+// compliance with the License.  You may obtain a copy of the License at    
+// http://www.redhat.com/                                                   
+//                                                                          
+// Software distributed under the License is distributed on an "AS IS"      
+// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
+// License for the specific language governing rights and limitations under 
+// the License.                                                             
+//                                                                          
+// The Original Code is eCos - Embedded Configurable Operating System,      
+// released September 30, 1998.                                             
+//                                                                          
+// The Initial Developer of the Original Code is Red Hat.                   
+// Portions created by Red Hat are                                          
+// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
+// All Rights Reserved.                                                     
+// -------------------------------------------                              
+//                                                                          
+//####COPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   jskov, based on ARM driver by gthomas
+// Contributors:gthomas, jskov
+// Date:        1999-03-02
+// Purpose:     Cogent Serial definitions
+//####DESCRIPTIONEND####
+//==========================================================================
+
+// Description of serial ports on Cogent board
+
+// Interrupt Enable Register
+#define IER_RCV 0x01
+#define IER_XMT 0x02
+#define IER_LS  0x04
+#define IER_MS  0x08
+
+// Line Control Register
+#define LCR_WL5 0x00    // Word length
+#define LCR_WL6 0x01
+#define LCR_WL7 0x02
+#define LCR_WL8 0x03
+#define LCR_SB1 0x00    // Number of stop bits
+#define LCR_SB1_5 0x04  // 1.5 -> only valid with 5 bit words
+#define LCR_SB2 0x04
+#define LCR_PN  0x00    // Parity mode - none
+#define LCR_PE  0x0C    // Parity mode - even
+#define LCR_PO  0x08    // Parity mode - odd
+#define LCR_PM  0x28    // Forced "mark" parity
+#define LCR_PS  0x38    // Forced "space" parity
+#define LCR_DL  0x80    // Enable baud rate latch
+
+// Line Status Register
+#define LSR_RSR 0x01
+#define LSR_THE 0x20
+
+// Modem Control Register
+#define MCR_DTR 0x01
+#define MCR_RTS 0x02
+#define MCR_INT 0x08   // Enable interrupts
+
+// Interrupt status register
+#define ISR_Tx  0x02
+#define ISR_Rx  0x04
+
+// FIFO control register
+#define FCR_ENABLE     0x01
+#define FCR_CLEAR_RCVR 0x02
+#define FCR_CLEAR_XMIT 0x04
+
+
+////////////////////////////////////////////////////////////
+// Clean this up.
+
+//-----------------------------------------------------------------------------
+// There are two serial ports.
+#define CMA_SER_16550_BASE_A    0xe900047 // port A
+#define CMA_SER_16550_BASE_B    0xe900007 // port B
+#define SER_16550_BASE CMA_SER_16550_BASE_B
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The Cogent board is equipped with a 16552
+// serial chip.
+#define SER_16550_RBR 0x00   // receiver buffer register, read, dlab = 0
+#define SER_16550_THR 0x00   // transmitter holding register, write, dlab = 0
+#define SER_16550_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
+#define SER_16550_IER 0x08   // interrupt enable register, read/write, dlab = 0
+#define SER_16550_DLM 0x08   // divisor latch (MS), read/write, dlab = 1
+#define SER_16550_IIR 0x10   // interrupt identification reg, read, dlab = 0
+#define SER_16550_FCR 0x10   // fifo control register, write, dlab = 0
+#define SER_16550_AFR 0x10   // alternate function reg, read/write, dlab = 1
+#define SER_16550_LCR 0x18   // line control register, read/write
+#define SER_16550_MCR 0x20   // modem control register, read/write
+#define SER_16550_LSR 0x28   // line status register, read
+#define SER_16550_MSR 0x30   // modem status register, read
+#define SER_16550_SCR 0x38   // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI   0x01            // enable received data available irq
+#define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
+#define SIO_IER_ELSI    0x04            // enable receiver line status irq
+#define SIO_IER_EMSI    0x08            // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP      0x01            // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
+
+// The line status register bits.
+#define SIO_LSR_DR      0x01            // data ready
+#define SIO_LSR_OE      0x02            // overrun error
+#define SIO_LSR_PE      0x04            // parity error
+#define SIO_LSR_FE      0x08            // framing error
+#define SIO_LSR_BI      0x10            // break interrupt
+#define SIO_LSR_THRE    0x20            // transmitter holding register empty
+#define SIO_LSR_TEMT    0x40            // transmitter register empty
+#define SIO_LSR_ERR     0x80            // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS  0x01              // delta clear to send
+#define SIO_MSR_DDSR  0x02              // delta data set ready
+#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
+#define SIO_MSR_DDCD  0x08              // delta data carrier detect
+#define SIO_MSR_CTS   0x10              // clear to send
+#define SIO_MSR_DSR   0x20              // data set ready
+#define SIO_MSR_RI    0x40              // ring indicator
+#define SIO_MSR_DCD   0x80              // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0   0x01             // word length select bit 0
+#define SIO_LCR_WLS1   0x02             // word length select bit 1
+#define SIO_LCR_STB    0x04             // number of stop bits
+#define SIO_LCR_PEN    0x08             // parity enable
+#define SIO_LCR_EPS    0x10             // even parity select
+#define SIO_LCR_SP     0x20             // stick parity
+#define SIO_LCR_SB     0x40             // set break
+#define SIO_LCR_DLAB   0x80             // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
+#define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
+/////////////////////////////////////////
+
+
+static unsigned char select_word_length[] = {
+    LCR_WL5,    // 5 bits / word (char)
+    LCR_WL6,
+    LCR_WL7,
+    LCR_WL8
+};
+
+static unsigned char select_stop_bits[] = {
+    0,
+    LCR_SB1,    // 1 stop bit
+    LCR_SB1_5,  // 1.5 stop bit
+    LCR_SB2     // 2 stop bits
+};
+
+static unsigned char select_parity[] = {
+    LCR_PN,     // No parity
+    LCR_PE,     // Even parity
+    LCR_PO,     // Odd parity
+    LCR_PM,     // Mark parity
+    LCR_PS,     // Space parity
+};
+
+// FIXME: calc all properly
+// The Cogent board has a 3.6864 MHz crystal
+static unsigned short select_baud[] = {
+    0,    // Unused
+    4608, // 50
+    0,    // 75
+    2094, // 110
+    0,    // 134.5
+    1536, // 150
+    0,    // 200
+    768,  // 300
+    384,  // 600
+    182,  // 1200
+    0,    // 1800
+    96,   // 2400
+    0,    // 3600
+    48,   // 4800
+    32,   // 7200
+    24,   // 9600
+    16,   // 14400
+    12,   // 19200
+    6,    // 38400
+    4,    // 57600
+    2,    // 115200
+    0,    // 230400
+};
+