--- a/packages/hal/arm/integrator/current/include/plf_io.h
+++ b/packages/hal/arm/integrator/current/include/plf_io.h
@@ -8,29 +8,38 @@
 //      Platform specific IO support
 //
 //=============================================================================
-//####COPYRIGHTBEGIN####
-//                                                                          
-// -------------------------------------------                              
-// The contents of this file are subject to the Red Hat eCos Public License 
-// Version 1.1 (the "License"); you may not use this file except in         
-// compliance with the License.  You may obtain a copy of the License at    
-// http://www.redhat.com/                                                   
-//                                                                          
-// Software distributed under the License is distributed on an "AS IS"      
-// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
-// License for the specific language governing rights and limitations under 
-// the License.                                                             
-//                                                                          
-// The Original Code is eCos - Embedded Configurable Operating System,      
-// released September 30, 1998.                                             
-//                                                                          
-// The Initial Developer of the Original Code is Red Hat.                   
-// Portions created by Red Hat are                                          
-// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
-// All Rights Reserved.                                                     
-// -------------------------------------------                              
-//                                                                          
-//####COPYRIGHTEND####
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
@@ -49,138 +58,12 @@
 
 #include <cyg/hal/hal_integrator.h>
 
-#include <cyg/hal/hal_io.h>             // IO macros
 #include <cyg/hal/hal_platform_ints.h>  // Interrupt vectors
 
+__externC void cyg_plf_pci_init(void);
+
 // Initialization of the PCI bus.
-#define HAL_PCI_INIT()                                                  	\
-    CYG_MACRO_START                                                     	\
-    volatile int i, j;								\
-										\
-    /* setting this register will take the V3 out of reset */			\
-										\
-    *(cyg_uint32 *)(INTEGRATOR_SC_PCIENABLE) = 1;				\
-										\
-    /* wait a few usecs to settle the device and the PCI bus */			\
-										\
-    for (i = 0; i < 100 ; i++)							\
-	   j = i + 1;								\
-										\
-    /* Now write the Base I/O Address Word to V3_BASE + 0x6C */			\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_LB_IO_BASE) = (cyg_uint16)(V3_BASE >> 16);	\
-										\
-    do {									\
-        *(cyg_uint8 *)(V3_BASE + V3_MAIL_DATA) = 0xAA;				\
-	*(cyg_uint8 *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55;			\
-    } while (*(cyg_uint8 *)(V3_BASE + V3_MAIL_DATA) != 0xAA ||			\
-	     *(cyg_uint8 *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55);		\
-										\
-    /* Make sure that V3 register access is not locked, if it is, unlock it */	\
-										\
-    if ((*(cyg_uint16 *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK)  		\
-				== V3_SYSTEM_M_LOCK)				\
-	*(cyg_uint16 *)(V3_BASE + V3_SYSTEM) = 0xA05F;				\
-										\
-    /* Ensure that the slave accesses from PCI are disabled while we */		\
-    /* setup windows */								\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_PCI_CMD) &= 					\
-				~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);	\
-										\
-    /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */	\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT;		\
-										\
-    /* Make all accesses from PCI space retry until we're ready for them */	\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN;		\
-										\
-    /* Set up any V3 PCI Configuration Registers that we absolutely have to */	\
-    /* LB_CFG controls Local Bus protocol. */					\
-    /* Enable LocalBus byte strobes for READ accesses too. */			\
-    /* set bit 7 BE_IMODE and bit 6 BE_OMODE */					\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_LB_CFG) |= 0x0C0;				\
-										\
-    /* PCI_CMD controls overall PCI operation. */				\
-    /* Enable PCI bus master. */						\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_PCI_CMD) |= 0x04;				\
-										\
-    /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/	\
-										\
-    *(cyg_uint32 *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) |	\
-					(V3_PCI_MAP_M_ADR_SIZE_512M |		\
-					V3_PCI_MAP_M_REG_EN |			\
-					V3_PCI_MAP_M_ENABLE);			\
-										\
-    /* PCI_BASE0 is the PCI address of the start of the window */		\
-										\
-    *(cyg_uint32 *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE;		\
-										\
-    /* PCI_MAP1 is LOCAL address of the start of the window */			\
-										\
-    *(cyg_uint32 *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) |	\
-			(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN |	\
-			 V3_PCI_MAP_M_ENABLE);					\
-										\
-    /* PCI_BASE1 is the PCI address of the start of the window */		\
-										\
-    *(cyg_uint32 *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE;	\
-										\
-    /* Set up the windows from local bus memory into PCI configuration, */	\
-    /* I/O and Memory. */							\
-    /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */		\
-										\
-    *(cyg_uint16 *)(V3_BASE +V3_LB_BASE2) = 					\
-			((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;	\
-    *(cyg_uint16 *)(V3_BASE + V3_LB_MAP2) = 0;					\
-										\
-    /* PCI Configuration, use LB_BASE1/LB_MAP1. */				\
-										\
-    /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */			\
-    /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */		\
-    /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */					\
-										\
-    *(cyg_uint32 *)(V3_BASE + V3_LB_BASE0) = 					\
-			INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);	\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_LB_MAP0) = 					\
-			((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;		\
-										\
-    /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */			\
-										\
-    *(cyg_uint32 *)(V3_BASE + V3_LB_BASE1) = 					\
-			INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);	\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_LB_MAP1) = 					\
-			(((INTEGRATOR_PCI_BASE + SZ_256M) >> 20) << 4) | 0x0006;\
-										\
-    /* Allow accesses to PCI Configuration space */				\
-    /* and set up A1, A0 for type 1 config cycles */				\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_PCI_CFG) = 					\
-			((*(cyg_uint16 *)(V3_BASE + V3_PCI_CFG)) &		\
-			   ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) |	\
-			   V3_PCI_CFG_M_AD_LOW0;				\
-										\
-    /* now we can allow in PCI MEMORY accesses */				\
-										\
-    *(cyg_uint16 *)(V3_BASE + V3_PCI_CMD) = 					\
-		(*(cyg_uint16 *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN;	\
-										\
-    /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */	\
-    /* initialise and lock the V3 system register so that no one else */	\
-    /* can play with it */							\
-										\
-   *(cyg_uint16 *)(V3_BASE + V3_SYSTEM) = 					\
-		(*(cyg_uint16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT;	\
-										\
-   *(cyg_uint16 *)(V3_BASE + V3_SYSTEM) = 					\
-		(*(cyg_uint16 *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK;	\
-                                                                         	\
-    CYG_MACRO_END
+#define HAL_PCI_INIT() cyg_plf_pci_init()
 
 
 // V3 access routines
@@ -267,22 +150,23 @@
 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )  		\
     {										\
     _V3OpenConfigWindow();							\
-    __val = *(cyg_uint8 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); 	\
+    __val = *(volatile cyg_uint8 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); 	\
     _V3CloseConfigWindow();							\
     }
 
 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val )  		\
     {										\
     _V3OpenConfigWindow();							\
-    __val = *(cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); 	\
+    __val = *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); 	\
     _V3CloseConfigWindow();							\
     }
 
-#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val )  		\
-    {										\
-    _V3OpenConfigWindow();							\
-    __val = *(cyg_uint32 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); 	\
-    _V3CloseConfigWindow();							\
+#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val )			\
+    {											\
+    _V3OpenConfigWindow();								\
+    __val = *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset);		\
+    __val |= (*(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, (__offset+2)))<<16;	\
+    _V3CloseConfigWindow();								\
     }
 
 // Write a value to the PCI configuration space of the appropriate
@@ -290,22 +174,23 @@
 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val )		\
     {										\
     _V3OpenConfigWindow();							\
-    *(cyg_uint8 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; 	\
+    *(volatile cyg_uint8 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; 	\
     _V3CloseConfigWindow();							\
     }
 
 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val )		\
     {										\
     _V3OpenConfigWindow();							\
-    *(cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; 	\
+    *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; 	\
     _V3CloseConfigWindow();							\
     }
 
-#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val )		\
-    {										\
-    _V3OpenConfigWindow();							\
-    *(cyg_uint32 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; 	\
-    _V3CloseConfigWindow();							\
+#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val )					  \
+    {													  \
+    _V3OpenConfigWindow();										  \
+    *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS((__bus), (__devfn), (__offset)) = ((__val) & 0xFFFF);		  \
+    *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS((__bus), (__devfn), ((__offset)+2)) = (((__val)>>16) & 0xFFFF); \
+    _V3CloseConfigWindow();										  \
     }
 
 //-----------------------------------------------------------------------------
@@ -358,5 +243,9 @@
     CYG_MACRO_END
 
 //-----------------------------------------------------------------------------
+
+#define CYGARC_PHYSICAL_ADDRESS(x) (x)
+
+//-----------------------------------------------------------------------------
 // end of plf_io.h
 #endif // CYGONCE_PLF_IO_H