--- a/packages/hal/mips/arch/current/include/hal_cache.h
+++ b/packages/hal/mips/arch/current/include/hal_cache.h
@@ -8,29 +8,38 @@
 //      HAL cache control API
 //
 //=============================================================================
-//####COPYRIGHTBEGIN####
-//                                                                          
-// -------------------------------------------                              
-// The contents of this file are subject to the Red Hat eCos Public License 
-// Version 1.1 (the "License"); you may not use this file except in         
-// compliance with the License.  You may obtain a copy of the License at    
-// http://www.redhat.com/                                                   
-//                                                                          
-// Software distributed under the License is distributed on an "AS IS"      
-// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
-// License for the specific language governing rights and limitations under 
-// the License.                                                             
-//                                                                          
-// The Original Code is eCos - Embedded Configurable Operating System,      
-// released September 30, 1998.                                             
-//                                                                          
-// The Initial Developer of the Original Code is Red Hat.                   
-// Portions created by Red Hat are                                          
-// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
-// All Rights Reserved.                                                     
-// -------------------------------------------                              
-//                                                                          
-//####COPYRIGHTEND####
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
@@ -153,6 +162,19 @@
 #endif
 
 //-----------------------------------------------------------------------------
+// Size adjustment
+// These macros adjust the size argument up to a whole multiple of the
+// cache line size. This ensures that we apply the cache operation to
+// all cache lines covered by the address[size] arguments in the
+// macros below.
+
+#define HAL_DCACHE_ADJUST_SIZE(_size_) \
+(((_size_)+HAL_DCACHE_LINE_SIZE-1) & ~(HAL_DCACHE_LINE_SIZE-1))
+
+#define HAL_ICACHE_ADJUST_SIZE(_size_) \
+(((_size_)+HAL_ICACHE_LINE_SIZE-1) & ~(HAL_ICACHE_LINE_SIZE-1))
+    
+//-----------------------------------------------------------------------------
 // Global control of data cache
 
 // Enable the data cache
@@ -210,7 +232,7 @@
     CYG_MACRO_START                                                       \
     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                 \
     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                  \
-    register CYG_WORD _size_ = (_asize_);                                 \
+    register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_);           \
     register CYG_WORD _state_;                                            \
     HAL_DCACHE_IS_ENABLED( _state_ );                                     \
     if( _state_ ) {                                                       \
@@ -250,7 +272,7 @@
     CYG_MACRO_START                                                       \
     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                 \
     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                  \
-    register CYG_WORD _size_ = (_asize_);                                 \
+    register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_);           \
     register CYG_WORD _state_;                                            \
     HAL_DCACHE_IS_ENABLED( _state_ );                                     \
     if( _state_ ) {                                                       \
@@ -269,7 +291,7 @@
     CYG_MACRO_START                                                     \
     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);               \
     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                \
-    register CYG_WORD _size_ = (_asize_);                               \
+    register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_);         \
     _HAL_ASM_SET_MIPS_ISA(3);                                           \
     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )   \
     { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); }                         \
@@ -284,7 +306,7 @@
     CYG_MACRO_START                                                       \
     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                 \
     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                  \
-    register CYG_WORD _size_ = (_asize_);                                 \
+    register CYG_WORD _size_ = HAL_DCACHE_ADJUST_SIZE(_asize_);           \
     register CYG_WORD _state_;                                            \
     HAL_DCACHE_IS_ENABLED( _state_ );                                     \
     if( _state_ ) {                                                       \
@@ -356,7 +378,7 @@
     CYG_MACRO_START                                                       \
     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                 \
     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                  \
-    register CYG_WORD _size_ = (_asize_);                                 \
+    register CYG_WORD _size_ = HAL_ICACHE_ADJUST_SIZE(_asize_);           \
     register CYG_WORD _state_;                                            \
     HAL_ICACHE_IS_ENABLED( _state_ );                                     \
     if( _state_ ) {                                                       \
@@ -388,7 +410,7 @@
     CYG_MACRO_START                                                     \
     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);               \
     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                \
-    register CYG_WORD _size_ = (_asize_);                               \
+    register CYG_WORD _size_ = HAL_ICACHE_ADJUST_SIZE(_asize_);         \
     _HAL_ASM_SET_MIPS_ISA(3);                                           \
     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )   \
     { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); }                         \