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+#ifndef CYGONCE_VAR_CACHE_H
+#define CYGONCE_VAR_CACHE_H
+//=============================================================================
+//
+//      var_cache.h
+//
+//      Variant HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   Bob Koninckx
+// Contributors:Bob Koninckx
+// Date:        2001-12-11
+// Purpose:     Variant cache control API
+// Description: The macros defined here provide the HAL APIs for handling
+//              cache control operations on the MPC8xx variant CPUs.
+// Usage:       Is included via the architecture cache header:
+//              #include <cyg/hal/hal_cache.h>
+//              ...
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+
+#include <cyg/hal/ppc_regs.h>
+
+#include <cyg/hal/plf_cache.h>
+
+
+//-----------------------------------------------------------------------------
+// MPC5xx has no data or instruction cache. This is going to be a relatively
+// simple file
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()                     \
+    CYG_MACRO_START                             \
+    CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()                    \
+    CYG_MACRO_START                             \
+    CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()             \
+    CYG_MACRO_START                             \
+    CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()                       \
+    CYG_MACRO_START                             \
+    CYG_MACRO_END
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    _state_ = 0;                                \
+    CYG_MACRO_END
+
+// Load the contents of the given address range into the data cache 
+// and then lock the cache so that it stays there.  
+
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+        
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+   
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()                                     \
+    CYG_MACRO_START                                             \
+    CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()                                    \
+    CYG_MACRO_START                                             \
+    CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()                             \
+    CYG_MACRO_START                                             \
+    CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()                                       \
+    CYG_MACRO_START                                             \
+    CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_)                          \
+    CYG_MACRO_START                                             \
+    _state_ = 0;                                                \
+    CYG_MACRO_END
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_VAR_CACHE_H
+// End of var_cache.h