--- a/packages/hal/sh/sh3/current/src/sh3_sci.c
+++ b/packages/hal/sh/sh3/current/src/sh3_sci.c
@@ -5,29 +5,38 @@
 //      Simple driver for the SH Serial Communication Interface (SCI)
 //
 //=============================================================================
-//####COPYRIGHTBEGIN####
-//                                                                          
-// -------------------------------------------                              
-// The contents of this file are subject to the Red Hat eCos Public License 
-// Version 1.1 (the "License"); you may not use this file except in         
-// compliance with the License.  You may obtain a copy of the License at    
-// http://www.redhat.com/                                                   
-//                                                                          
-// Software distributed under the License is distributed on an "AS IS"      
-// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
-// License for the specific language governing rights and limitations under 
-// the License.                                                             
-//                                                                          
-// The Original Code is eCos - Embedded Configurable Operating System,      
-// released September 30, 1998.                                             
-//                                                                          
-// The Initial Developer of the Original Code is Red Hat.                   
-// Portions created by Red Hat are                                          
-// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
-// All Rights Reserved.                                                     
-// -------------------------------------------                              
-//                                                                          
-//####COPYRIGHTEND####
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
 //=============================================================================
 //#####DESCRIPTIONBEGIN####
 //
@@ -67,14 +76,14 @@ cyg_hal_plf_sci_init_channel(const chann
 
     // Disable Tx/Rx interrupts, but enable Tx/Rx
     HAL_WRITE_UINT8(base+_REG_SCSCR,
-                    CYGARC_REG_SCSCR_TE|CYGARC_REG_SCSCR_RE);
+                    CYGARC_REG_SCI_SCSCR_TE|CYGARC_REG_SCI_SCSCR_RE);
 
     // 8-1-no parity.
     HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
 
     // Set speed to CYGNUM_HAL_SH_SH3_SCI_DEFAULT_BAUD_RATE
     HAL_READ_UINT8(base+_REG_SCSMR, tmp);
-    tmp &= ~CYGARC_REG_SCSMR_CKSx_MASK;
+    tmp &= ~CYGARC_REG_SCI_SCSMR_CKSx_MASK;
     tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE);
     HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
     HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE));
@@ -87,20 +96,20 @@ cyg_hal_plf_sci_getc_nonblock(void* __ch
     cyg_uint8 sr;
 
     HAL_READ_UINT8(base+_REG_SCSSR, sr);
-    if (sr & CYGARC_REG_SCSSR_ORER) {
+    if (sr & CYGARC_REG_SCI_SCSSR_ORER) {
         // Serial RX overrun. Clear error and let caller try again.
         HAL_WRITE_UINT8(base+_REG_SCSSR, 
-                        CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER);
+                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_ORER);
         return false;
     }
 
-    if ((sr & CYGARC_REG_SCSSR_RDRF) == 0)
+    if ((sr & CYGARC_REG_SCI_SCSSR_RDRF) == 0)
         return false;
 
     HAL_READ_UINT8(base+_REG_SCRDR, *ch);
 
     // Clear buffer full flag.
-    HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_RDRF);
+    HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCI_SCSSR_RDRF);
 
     return true;
 }
@@ -126,17 +135,17 @@ cyg_hal_plf_sci_putc(void* __ch_data, cy
 
     do {
         HAL_READ_UINT8(base+_REG_SCSSR, sr);
-    } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0);
+    } while ((sr & CYGARC_REG_SCI_SCSSR_TDRE) == 0);
 
     HAL_WRITE_UINT8(base+_REG_SCTDR, c);
 
     // Clear empty flag.
-    HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_TDRE);
+    HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCI_SCSSR_TDRE);
 
     // Hang around until the character has been safely sent.
     do {
         HAL_READ_UINT8(base+_REG_SCSSR, sr);
-    } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0);
+    } while ((sr & CYGARC_REG_SCI_SCSSR_TDRE) == 0);
 
     CYGARC_HAL_RESTORE_GP();
 }
@@ -203,7 +212,7 @@ cyg_hal_plf_sci_control(void *__ch_data,
         irq_state = 1;
         HAL_INTERRUPT_UNMASK(chan->isr_vector);
         HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
-        scr |= CYGARC_REG_SCSCR_RIE;
+        scr |= CYGARC_REG_SCI_SCSCR_RIE;
         HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
         break;
     case __COMMCTL_IRQ_DISABLE:
@@ -211,7 +220,7 @@ cyg_hal_plf_sci_control(void *__ch_data,
         irq_state = 0;
         HAL_INTERRUPT_UNMASK(chan->isr_vector);
         HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
-        scr &= ~CYGARC_REG_SCSCR_RIE;
+        scr &= ~CYGARC_REG_SCI_SCSCR_RIE;
         HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
         break;
     case __COMMCTL_DBG_ISR_VECTOR:
@@ -246,18 +255,18 @@ cyg_hal_plf_sci_isr(void *__ch_data, int
 
     *__ctrlc = 0;
     HAL_READ_UINT8(base+_REG_SCSSR, sr);
-    if (sr & CYGARC_REG_SCSSR_ORER) {
+    if (sr & CYGARC_REG_SCI_SCSSR_ORER) {
         // Serial RX overrun. Clear error and hope protocol recovers.
         HAL_WRITE_UINT8(base+_REG_SCSSR, 
-                        CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER);
+                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_ORER);
         res = CYG_ISR_HANDLED;
-    } else if (sr & CYGARC_REG_SCSSR_RDRF) {
+    } else if (sr & CYGARC_REG_SCI_SCSSR_RDRF) {
         // Received character
         HAL_READ_UINT8(base+_REG_SCRDR, c);
 
         // Clear buffer full flag.
         HAL_WRITE_UINT8(base+_REG_SCSSR, 
-                        CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
+                        CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);
 
         if( cyg_hal_is_break( &c , 1 ) )
             *__ctrlc = 1;