# HG changeset patch
# User gthomas
# Date 1069239500 0
# Node ID 1e45895acdfa9c51c16a306027a3b1d564537105
# Parent  19f40f995cc25e89bf1e1cdaa48306acfb084c8c
Clean up - from Jani Monoses

diff --git a/packages/hal/arm/sa11x0/cerfpda/current/ChangeLog b/packages/hal/arm/sa11x0/cerfpda/current/ChangeLog
--- a/packages/hal/arm/sa11x0/cerfpda/current/ChangeLog
+++ b/packages/hal/arm/sa11x0/cerfpda/current/ChangeLog
@@ -1,3 +1,9 @@
+2003-11-19  Jani Monoses  <jani@iv.ro>
+	
+	* src/cerfpda_misc.c: Map DRAM as cacheable, it increases performance.
+	* include/plf_mmap.h: Delete duplicate HAL_PHYS_TO_VIRT_ADDRESS
+	definition.
+	
 2003-02-13  Patrick Doyle  <wpd@delcomsys.com>
 	* src/cerfpda_misc.c: Replaced explicit prototype of memset with
 	#include <string.h>.
diff --git a/packages/hal/arm/sa11x0/cerfpda/current/include/plf_mmap.h b/packages/hal/arm/sa11x0/cerfpda/current/include/plf_mmap.h
--- a/packages/hal/arm/sa11x0/cerfpda/current/include/plf_mmap.h
+++ b/packages/hal/arm/sa11x0/cerfpda/current/include/plf_mmap.h
@@ -75,7 +75,6 @@
 #define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START      \
     (pagesize) = SZ_1M;                                         \
 CYG_MACRO_END
-
 // Get the physical address from a virtual address:
 
 // Only RAM and ROM are mapped; we just pass through all other values,
@@ -120,23 +119,6 @@ CYG_MACRO_END
     (vaddr) = _p_ ;                                                        \
 CYG_MACRO_END
 
-// Get the virtual address for a physical address:
-
-// Only RAM and ROM are mapped; we just pass through all other values,
-// rather than detecting nonexistent areas here.
-
-#define HAL_PHYS_TO_VIRT_ADDRESS( paddr, vaddr ) CYG_MACRO_START           \
-    cyg_uint32 _p_ = (cyg_uint32)(paddr);                                  \
-    if ( 32 * SZ_1M > _p_ )         /* 32Mb Boot ROM mapped to 0x500Mb */  \
-        _p_ += 0x500u * SZ_1M;                                             \
-    else if ( 0xc00u * SZ_1M > _p_ ) /* Space between ROM and SDRAM */     \
-        /* no change */ ;                                                  \
-    else if ( 0xc20u * SZ_1M > _p_ ) /* Raw RAM size 32Mb */               \
-        _p_ -= 0xc00u * SZ_1M;                                             \
-    else                            /* Rest of it */                       \
-        /* no change */ ;                                                  \
-    (vaddr) = _p_ ;                                                        \
-CYG_MACRO_END
 
 // Get a non-cacheable address for accessing the same store as a virtual
 // (assumed cachable) address:
@@ -152,7 +134,6 @@ CYG_MACRO_END
         /* no change */ ;                                                  \
     (uaddr) = _v_ ;                                                        \
 CYG_MACRO_END
-
 //---------------------------------------------------------------------------
 #endif // CYGONCE_HAL_SA11X0_PLATFORM_PLF_MMAP_H
 // EOF plf_mmap.h
diff --git a/packages/hal/arm/sa11x0/cerfpda/current/src/cerfpda_misc.c b/packages/hal/arm/sa11x0/cerfpda/current/src/cerfpda_misc.c
--- a/packages/hal/arm/sa11x0/cerfpda/current/src/cerfpda_misc.c
+++ b/packages/hal/arm/sa11x0/cerfpda/current/src/cerfpda_misc.c
@@ -105,7 +105,7 @@ hal_mmu_init(void)
     X_ARM_MMU_SECTION(0x200,  0x200,   512,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Socket A */
     X_ARM_MMU_SECTION(0x300,  0x300,   512,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets B */
     X_ARM_MMU_SECTION(0x800,  0x800, 0x400,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
-    X_ARM_MMU_SECTION(0xC00,  0x000,    64,  ARM_UNCACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
+    X_ARM_MMU_SECTION(0xC00,  0x000,    64,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
     X_ARM_MMU_SECTION(0xC00,  0xC00,    64,  ARM_UNCACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
     X_ARM_MMU_SECTION(0xE00,  0xE00,   128,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */