# HG changeset patch
# User gthomas
# Date 1047996207 0
# Node ID 68468dc734f49942db8c2bc28d7f3effd94a60a1
# Parent  d6cfbed66cf950ea2292a3e1ea2fa076ad2e6bf8
Update SCC2 initialization

diff --git a/packages/hal/powerpc/quicc/current/ChangeLog b/packages/hal/powerpc/quicc/current/ChangeLog
--- a/packages/hal/powerpc/quicc/current/ChangeLog
+++ b/packages/hal/powerpc/quicc/current/ChangeLog
@@ -1,3 +1,8 @@
+2003-03-18  Gary Thomas  <gary@mlbassoc.com>
+
+	* src/quicc_smc1.c (cyg_hal_sccx_init_channel): Update initialization
+	for SCC2 - *CAUTION* not tested on actual hardware.
+
 2003-03-06  Gary Thomas  <gary@mlbassoc.com>
 
 	* src/cpm.c: Handle case where DPRAM allocation is unknown.
diff --git a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
--- a/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
+++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c
@@ -620,26 +620,26 @@ cyg_hal_sccx_init_channel(struct port_in
 #if CYGNUM_HAL_QUICC_SCC2 > 0
     case QUICC_CPM_SCC2:
 #error FIXME
-        eppc->pio_papar |= 0x03;
-        eppc->pio_padir &= ~0x03;
-        eppc->pio_paodr &= ~0x03;
+        eppc->pio_papar |= 0x0C;
+        eppc->pio_padir &= ~0x0C;
+        eppc->pio_paodr &= ~0x0C;
 
         /* CTS on PortC.11 */
-        eppc->pio_pcdir &= 0x800;
-        eppc->pio_pcpar &= 0x800;
-        eppc->pio_pcso  |= 0x800;
+        eppc->pio_pcdir &= 0xC00;
+        eppc->pio_pcpar &= 0xC00;
+        eppc->pio_pcso  |= 0xC00;
 
         /* RTS on PortB.19 */
-        eppc->pip_pbpar |= 0x1000;
-        eppc->pip_pbdir |= 0x1000;
+        eppc->pip_pbpar |= 0x2000;
+        eppc->pip_pbdir |= 0x2000;
 
         /* Configure baud rate generator (Section 16.13.2) */
         eppc->brgc2 = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
 
         /*
-         *  NMSI mode, BRG2 to SCC1
+         *  NMSI mode, BRG2 to SCC2
          */
-        eppc->si_sicr |= (1<<3)|(1<<0);
+        eppc->si_sicr |= (1<<11)|(1<<8);
         break;
 #endif
 #if CYGNUM_HAL_QUICC_SCC3 > 0