# HG changeset patch
# User msalter
# Date 1049671180 0
# Node ID 97d8ec82826049619a91a16cec64e46d88f278dc
# Parent  97ac17e0e4deed56e4b5d995702f5cdecac9dc0d
ixp425 support for non-host mode

diff --git a/packages/hal/arm/xscale/ixp425/current/ChangeLog b/packages/hal/arm/xscale/ixp425/current/ChangeLog
--- a/packages/hal/arm/xscale/ixp425/current/ChangeLog
+++ b/packages/hal/arm/xscale/ixp425/current/ChangeLog
@@ -1,3 +1,7 @@
+2003-04-06  Mark Salter  <msalter@redhat.com>
+
+	* src/ixp425_pci.c (cyg_hal_plf_pci_init): Support non-host mode.
+
 2003-02-22  Mark Salter  <msalter@redhat.com>
 
 	* src/ixp425_pci.c (cyg_hal_plf_pci_init): Don't reinit PCI
diff --git a/packages/hal/arm/xscale/ixp425/current/src/ixp425_pci.c b/packages/hal/arm/xscale/ixp425/current/src/ixp425_pci.c
--- a/packages/hal/arm/xscale/ixp425/current/src/ixp425_pci.c
+++ b/packages/hal/arm/xscale/ixp425/current/src/ixp425_pci.c
@@ -394,6 +394,7 @@ void
 cyg_hal_plf_pci_init(void)
 {  
     static int inited = 0;
+    int  is_host = (*IXP425_PCI_CSR & PCI_CSR_HOST);
 
     if (inited)
 	return;
@@ -412,35 +413,45 @@ cyg_hal_plf_pci_init(void)
     // in 4 16MB BARs that begin at the physical memory start
     *IXP425_PCI_AHBMEMBASE = 0x00010203;
 
-    HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_0, 0x00000000);
-    HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_1, 0x01000000);
-    HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_2, 0x02000000);
-    HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_3, 0x03000000);
+    if (is_host) {
+
+	HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_0, 0x00000000);
+	HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_1, 0x01000000);
+	HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_2, 0x02000000);
+	HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_3, 0x03000000);
+
+	cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY);
+	cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
 
-    cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY);
-    cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
+	// This one should never get used, as we request the memory for
+	// work with PCI with GFP_DMA, which will return mem in the first 64 MB.
+	// But we still must initialize it so that it wont intersect with first 4
+	// BARs
+	// XXX: Should we initialize the BAR5 to some very large value, so that
+	// it also will not be hit?
+	//
+	HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_4, 0x80000000);
+	HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_5, 0x90000000);
 
-    // This one should never get used, as we request the memory for
-    // work with PCI with GFP_DMA, which will return mem in the first 64 MB.
-    // But we still must initialize it so that it wont intersect with first 4
-    // BARs
-    // XXX: Should we initialize the BAR5 to some very large value, so that
-    // it also will not be hit?
-    //
-    HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_4, 0x80000000);
-    HAL_PCI_CFG_WRITE_UINT32(0, 0, CYG_PCI_CFG_BAR_5, 0x90000000);
+	*IXP425_PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
 
-    *IXP425_PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE;
-
-    //
-    // Set Initialize Complete in PCI Control Register: allow IXP425 to
-    // respond to PCI configuration cycles. Specify that the AHB bus is
-    // operating in big endian mode. Set up byte lane swapping between 
-    // little-endian PCI and the big-endian AHB bus 
-    *IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
+	//
+	// Set Initialize Complete in PCI Control Register: allow IXP425 to
+	// respond to PCI configuration cycles. Specify that the AHB bus is
+	// operating in big endian mode. Set up byte lane swapping between 
+	// little-endian PCI and the big-endian AHB bus 
+	*IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
     
-    HAL_PCI_CFG_WRITE_UINT16(0, 0, CYG_PCI_CFG_COMMAND,
-		    CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_MEMORY);
+	HAL_PCI_CFG_WRITE_UINT16(0, 0, CYG_PCI_CFG_COMMAND,
+		 CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_MEMORY);
+    } else {
+	//
+	// Set Initialize Complete in PCI Control Register: allow IXP425 to
+	// respond to PCI configuration cycles. Specify that the AHB bus is
+	// operating in big endian mode. Set up byte lane swapping between 
+	// little-endian PCI and the big-endian AHB bus 
+	*IXP425_PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
+    }
 }
 
 #endif // CYGPKG_IO_PCI