# HG changeset patch # User jlarmour # Date 1048785997 0 # Node ID a9d5a0fc1ce82eed2c5a73c019e0334ce8722f3a # Parent 66392c0bb65620f861c47ef5c16040ed61ec131f * src/ics1890.c: Added configurable PHY MII address. * src/lxt970.c: Added configurable PHY MII address. * src/lxt972.c: Added configurable PHY MII address. * cdl/ks32c5000_eth.cdl: CDL to allow configuration of the PHY MII address. Documented support for ICS1893AF PHY. * src/ks5000_ether.c: Added configurable PHY MII address. Fixed local definition of eth_drv_init() macro (produces no code change). Fixed strncpy()s for the ETH_DRV_GET_IF_STATS IOCTL to leave room for the NUL termination character and use parenthesis with the 'sizeof' operator. Added ETH_DRV_SET_MAC_ADDRESS IOCTL support to allow setting the MAC (ESA) address from the application. Fixed to only attach the CYGNUM_HAL_INTERRUPT_EXT0 if the HavePHYinterrupt conditional is defined. This prevents unhandled interrupts from getting through when HavePHYinterrupt is not defined. diff --git a/packages/devs/eth/arm/ks32c5000/current/ChangeLog b/packages/devs/eth/arm/ks32c5000/current/ChangeLog --- a/packages/devs/eth/arm/ks32c5000/current/ChangeLog +++ b/packages/devs/eth/arm/ks32c5000/current/ChangeLog @@ -1,8 +1,25 @@ +2003-03-27 Jay Foster + + * src/ics1890.c: Added configurable PHY MII address. + * src/lxt970.c: Added configurable PHY MII address. + * src/lxt972.c: Added configurable PHY MII address. + * cdl/ks32c5000_eth.cdl: CDL to allow configuration of the PHY + MII address. Documented support for ICS1893AF PHY. + * src/ks5000_ether.c: Added configurable PHY MII address. + Fixed local definition of eth_drv_init() macro (produces no code + change). Fixed strncpy()s for the ETH_DRV_GET_IF_STATS IOCTL to + leave room for the NUL termination character and use parenthesis + with the 'sizeof' operator. Added ETH_DRV_SET_MAC_ADDRESS IOCTL + support to allow setting the MAC (ESA) address from the application. + Fixed to only attach the CYGNUM_HAL_INTERRUPT_EXT0 if the + HavePHYinterrupt conditional is defined. This prevents unhandled + interrupts from getting through when HavePHYinterrupt is not defined. + 2003-03-26 Chris Garry - * cdl/ks32c5000_eth.cdl - * src/ks5000_ether.c: Added CDL control for level of driver - debug output. + * cdl/ks32c5000_eth.cdl + * src/ks5000_ether.c: Added CDL control for level of driver + debug output. 2003-03-20 Chris Garry diff --git a/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl b/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl --- a/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl +++ b/packages/devs/eth/arm/ks32c5000/current/cdl/ks32c5000_eth.cdl @@ -96,9 +96,11 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 default_value 0 implements CYGINT_DEVS_ETH_ARM_KS32C5000_PHY compile -library=libextras.a ics1890.c + description "This component provides support for the ICS1890 and + ICS1893AF PHY" } - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT970 { display "LXT970 PHY support" flavor bool default_value 1 @@ -114,7 +116,7 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 compile -library=libextras.a lxt972.c no_define - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED1 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED1 { display "LED 1 mode" flavor data legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY" "COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS" @@ -124,7 +126,7 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 default_value {"LINK_STATUS"} } - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED2 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED2 { display "LED 2 mode" flavor data legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY" "COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS" @@ -134,7 +136,7 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 default_value {"LINK_SPEED"} } - cdl_component CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED3 { + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHY_LXT972_LED3 { display "LED 3 mode" flavor data legal_values {"LINK_SPEED" "TX_ACTIVITY" "RX_ACTIVITY" "COLLISION_STATUS" "LINK_STATUS" "DUPLEX_STATUS" @@ -145,6 +147,14 @@ cdl_package CYGPKG_DEVS_ETH_ARM_KS32C500 } } + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR { + display "PHY MII address" + flavor data + legal_values 0 to 31 + default_value 1 + description "This option specifies the MII address of the PHY" + } + cdl_option CYGPKG_DEVS_ETH_ARM_KS32C5000_MACADDR { display "Ethernet address for eth0" flavor data diff --git a/packages/devs/eth/arm/ks32c5000/current/src/ics1890.c b/packages/devs/eth/arm/ks32c5000/current/src/ics1890.c --- a/packages/devs/eth/arm/ks32c5000/current/src/ics1890.c +++ b/packages/devs/eth/arm/ks32c5000/current/src/ics1890.c @@ -67,7 +67,11 @@ #define PHY_10BOP_REG 0x12 #define PHY_ECNTL_REG2 0x13 -#define PHYHWADDR 0x20 +#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#define PHYHWADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#else +#define PHYHWADDR 1 +#endif #define Bit(n) (1<<(n)) diff --git a/packages/devs/eth/arm/ks32c5000/current/src/ks5000_ether.c b/packages/devs/eth/arm/ks32c5000/current/src/ks5000_ether.c --- a/packages/devs/eth/arm/ks32c5000/current/src/ks5000_ether.c +++ b/packages/devs/eth/arm/ks32c5000/current/src/ks5000_ether.c @@ -60,7 +60,7 @@ #include #include #else -// need to prvide fake values for errno +// need to provide fake values for errno #define EIO 1 #define EINVAL 2 #endif @@ -134,20 +134,20 @@ void MiiStationWrite(U32 RegAddr, U32 PhyAddr, U32 PhyWrData) { STADATA = PhyWrData ; - STACON = RegAddr | PhyAddr | MiiStart | PHYREGWRITE ; + STACON = RegAddr | (PhyAddr<<5) | MiiStart | PHYREGWRITE ; while (STACON & MiiStart) ; - //debug_printf("PHY Wr %x:%02x := %04x\n",PhyAddr, RegAddr, PhyWrData) ; + //debug1_printf("PHY Wr %x:%02x := %04x\n",PhyAddr, RegAddr, PhyWrData) ; } U32 MiiStationRead(U32 RegAddr, U32 PhyAddr) { U32 PhyRdData; - STACON = RegAddr | PhyAddr | MiiStart; + STACON = RegAddr | (PhyAddr<<5) | MiiStart; while (STACON & MiiStart) ; PhyRdData = STADATA; - //debug_printf("PHY Rd %x:%02x %04x\n",PhyAddr,RegAddr,PhyRdData) ; + //debug1_printf("PHY Rd %x:%02x %04x\n",PhyAddr,RegAddr,PhyRdData) ; return PhyRdData ; } #endif @@ -772,9 +772,9 @@ static cyg_uint32 MAC_Phy_isr(cyg_vector ++ks5000_MAC_Phy_Cnt; linkStatus = PhyStatus(); if (linkStatus & PhyStatus_FullDuplex) - MACConfigVar |= (1<<3); + MACConfigVar |= (MACON_FULL_DUP); else - MACConfigVar &= ~(1<<3); + MACConfigVar &= ~(MACON_FULL_DUP); #if defined(CYGPKG_NET) if (linkStatus & PhyStatus_FullDuplex) @@ -1102,8 +1102,10 @@ static void installInterrupts(void) cyg_drv_interrupt_attach(macRxIntrHandle); cyg_drv_interrupt_attach(macTxIntrHandle); +#if HavePHYinterrupt cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0); cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0); +#endif } //====================================================================== @@ -1120,7 +1122,7 @@ typedef struct ks32c5000_priv_data_t ks32c5000_priv_data; #define eth_drv_tx_done(sc,key,retval) (sc)->funs->eth_drv->tx_done(sc,key,retval) -#define eth_drv_init(sc,enaddr) ((sc)->funs->eth_drv->init)(sc, myMacAddr) +#define eth_drv_init(sc,enaddr) ((sc)->funs->eth_drv->init)(sc, enaddr) #define eth_drv_recv(sc,len) ((sc)->funs->eth_drv->recv)(sc, len) static unsigned char myMacAddr[6] = { CYGPKG_DEVS_ETH_ARM_KS32C5000_MACADDR }; @@ -1184,11 +1186,34 @@ static int ks32c5000_eth_control(struct { struct ether_drv_stats *p = (struct ether_drv_stats*)data; *p = ifStats; - strncpy(p->description,"description goes here",sizeof p->description); - strncpy(p->snmp_chipset,"chipset name",sizeof p->snmp_chipset); + strncpy(p->description,"description goes here",sizeof(p->description)-1); + p->description[sizeof(p->description)-1] = '\0'; + strncpy(p->snmp_chipset,"chipset name",sizeof(p->snmp_chipset)-1); + p->snmp_chipset[sizeof(p->snmp_chipset)-1] = '\0'; return 0; } #endif + case ETH_DRV_SET_MAC_ADDRESS: { + int act; + + if (ETHER_ADDR_LEN != len) + return -1; + debug1_printf("ks32c5000_eth_control: ETH_DRV_SET_MAC_ADDRESS.\n"); + act = ethernetRunning; + ks32c5000_eth_stop(sc); + ks32c5000_eth_start(sc, data, 0); + ethernetRunning = act; + return 0; + } +#ifdef ETH_DRV_GET_MAC_ADDRESS + case ETH_DRV_GET_MAC_ADDRESS: { + if (len < ETHER_ADDR_LEN) + return -1; + debug1_printf("ks32c5000_eth_control: ETH_DRV_GET_MAC_ADDRESS.\n"); + memcpy(data, (void *)CAM_BaseAddr, ETHER_ADDR_LEN); + return 0; + } +#endif default: return -1; } diff --git a/packages/devs/eth/arm/ks32c5000/current/src/lxt970.c b/packages/devs/eth/arm/ks32c5000/current/src/lxt970.c --- a/packages/devs/eth/arm/ks32c5000/current/src/lxt970.c +++ b/packages/devs/eth/arm/ks32c5000/current/src/lxt970.c @@ -55,7 +55,11 @@ #include "phy.h" // address of the LX970 phy -#define LX970_ADDR 0x20 +#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#define LX970_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#else +#define LX970_ADDR 1 +#endif // LX970 register offsets #define LX970_CNTL_REG 0x00 diff --git a/packages/devs/eth/arm/ks32c5000/current/src/lxt972.c b/packages/devs/eth/arm/ks32c5000/current/src/lxt972.c --- a/packages/devs/eth/arm/ks32c5000/current/src/lxt972.c +++ b/packages/devs/eth/arm/ks32c5000/current/src/lxt972.c @@ -59,7 +59,11 @@ #define Bit(n) (1<<(n)) // address of the LX972 phy -#define LX972_ADDR 0x00 +#ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#define LX972_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR +#else +#define LX972_ADDR 0 +#endif // LX972 register offsets #define LX972_CTRL_REG 0x00