Mercurial > flash_v2
changeset 52:7b011d1ab50f ecos-sw-1999-11-05
Merge from eCos master repository on 1999-11-05-17:34:28-GMT
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--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -60,6 +60,10 @@ 1999-08-16 Jonathan Larmour <jlarmour@ * targets: Rename all mentions of am32 to am31 +1999-08-12 Jesper Skov <jskov@cygnus.co.uk> + + * packages: Added entry for PCI package. + 1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> * packages, targets: Add support for the PowerPC target MBX860
--- a/packages/NEWS +++ b/packages/NEWS @@ -67,6 +67,7 @@ ** API additions +*** PCI library - providing an API to control the PCI buses of supported targets *** Debugging The file <cyg/kernel/test/stackmon.h> defines some functions @@ -89,6 +90,11 @@ The eCos idle loop will not load the host system anymore (except in special configurations, see linux_misc.c). +*** Sparclite + +Where supported by the targetted platform, it is now possible to use +Multiple Vector Trapping (MVT). + *** Common ** Other new features
--- a/packages/hal/arm/arch/current/ChangeLog +++ b/packages/hal/arm/arch/current/ChangeLog @@ -97,6 +97,10 @@ 1999-08-23 Jesper Skov <jskov@cygnus.c (target_ins): Check whether branches execute. (ins_will_execute): Fixed HI and LS. +1999-08-12 Jesper Skov <jskov@cygnus.co.uk> + + * include/hal_io.h: Include plf_io.h when appropriate. + 1999-08-06 Jesper Skov <jskov@cygnus.co.uk> CR 101032 * src/vectors.S (handle_IRQ_or_FIQ): Moved setup of register_frame
--- a/packages/hal/arm/arch/current/include/hal_io.h +++ b/packages/hal/arm/arch/current/include/hal_io.h @@ -196,6 +196,13 @@ typedef volatile CYG_ADDRWORD HAL_IO_REG // operations. #define HAL_IO_BARRIER() +//----------------------------------------------------------------------------- +// Include plf_io.h for platforms that define it. +// FIXME: It should be possible to handle this better with CDL; define +// CYGBLD_HAL_PLATFORM_IO or similar where appropriate. +#ifdef CYGPKG_HAL_ARM_EBSA285 +#include <cyg/hal/plf_io.h> +#endif //----------------------------------------------------------------------------- #endif // ifndef CYGONCE_HAL_IO_H
--- a/packages/hal/arm/cl7211/current/ChangeLog +++ b/packages/hal/arm/cl7211/current/ChangeLog @@ -1,3 +1,9 @@ +1999-11-03 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/hal_arm_cl7211.h: Change default clock speed + to 36MHz with no software DRAM refresh (hardware is stable with + this combo). + 1999-10-27 Gary Thomas <gthomas@cygnus.co.uk> * src/cl7211_misc.c (enable_FIQ): New function. Used to re-enable
--- a/packages/hal/arm/cl7211/current/include/pkgconf/hal_arm_cl7211.h +++ b/packages/hal/arm/cl7211/current/include/pkgconf/hal_arm_cl7211.h @@ -165,7 +165,7 @@ } }}CFG_DATA */ -#define CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK 73728 +#define CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK 36864 /* --------------------------------------------------------------------- {{CFG_DATA @@ -198,7 +198,7 @@ }}CFG_DATA */ -#define CYGHWR_HAL_ARM_CL7211_SOFTWARE_DRAM_REFRESH +#undef CYGHWR_HAL_ARM_CL7211_SOFTWARE_DRAM_REFRESH /* ---------------------------------------------------------------------------- {{CFG_DATA
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,11 @@ +1999-11-04 Nick Garnett <nickg@cygnus.co.uk> + + * src/vectors.S: Added code in reset vector to reset the config0 + register to a known state. This is because on some MIPS variants + the K0 field comes up in an undefined state. + [Later] Moved this code to just work in the case of a cold boot. + NMIs and warm boots should leave it as it was. + 1999-10-29 Nick Garnett <nickg@cygnus.co.uk> * include/pkgconf/hal_mips.h: Added condition to set a
--- a/packages/hal/mips/arch/current/src/vectors.S +++ b/packages/hal/mips/arch/current/src/vectors.S @@ -76,7 +76,7 @@ FUNC_START(reset_vector) lar k1,__nmi_entry # jump to ROM nmi code jalr k1 nop -1: +1: lui k1,0x0010 # isolate soft reset bit and k1,k1,k0 beqz k1,2f # skip if zero @@ -86,6 +86,8 @@ 1: jr k1 nop 2: + la k0,INITIAL_CONFIG0 # Set up config0 register + mtc0 k0,config0 # to disable cache #endif lar v0,_start # jump to start jr v0
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/ChangeLog @@ -0,0 +1,149 @@ +1999-09-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/pci2.c (pci_test): Replaced CYG_ASSERT with CYG_TEST_CHECK + +1999-09-10 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_pci.h: Reparent under CYGPKG_IO - this is used under + more than one target now and the library itself is generic. + +1999-08-25 Jesper Skov <jskov@cygnus.co.uk> + + * src/pci.c (cyg_pci_init): Made it idempotent. + + * tests/pci1.c: + * tests/pci2.c: + * src/pci.c: + * include/pci.h: + All functions that deal with addresses in PCI space now use PCI + ADDRESS types. + +1999-08-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/pci1.c: + * tests/pci2.c: + * include/pci.h: + * src/pci.c: + Handle requests for memory regions in 64bit space. + +1999-08-24 Jesper Skov <jskov@cygnus.co.uk> + + * tests/pci1.c: Added more output, resource allocation, debug help + (enable devices). + + * src/pci.c (cyg_pci_find_next): Handle multi-function devices. + + * include/pci_cfg.h (CYG_PCI_CFG_COMMAND_ACTIVE): Added MASTER. + Added HEADER_TYPE definitions. + +1999-08-23 Nick Garnett <nickg@cygnus.co.uk> + + * tests/pci1.c: Fixed a couple of bugs in the vendor/device/class + table search code. + +1999-08-23 Jesper Skov <jskov@cygnus.co.uk> + + * tests/pcihdr.h: [Added] + * tests/pci1.c: Added Vendor/Device ID description output. + + * include/pci_cfg.h: Added vendor and class IDs. + Also added Prog/IF IDs. + +1999-08-19 Nick Garnett <nickg@cygnus.co.uk> + + * tests/pci1.c (pci_test): Added printf() of class_rev code to + output of bus scan. + + * include/pci.h (CYG_PCI_MAX_FN): Increased to 8. + +1999-08-19 Jesper Skov <jskov@cygnus.co.uk> + + * src/pci.c (cyg_pci_allocate_memory, cyg_pci_allocate_io): + Check that device is inactive. Ensure that 1MB limits (IO/MEM1MB) + are observed. + + * tests/pci2.c (pci_test): Added tests of io/mem allocators. + +1999-08-17 Jesper Skov <jskov@cygnus.co.uk> + + * tests/pci2.c (pci_test): Added (empty for now) + * tests/pci1.c: Added API checks. + * include/pci.h: Fixed typo. + + * include/pci.h (CYG_PCI_NULL_DEVID): Changed initializer. + * src/pci.c (cyg_pci_find_next): Correct check for initializer. + + * tests/pci1.c: Added. + Fixed output. + + * include/pci_cfg.h: + * include/pci.h: + * include/pci_hw.h: + * src/pci_hw.c: + * src/pci.c: + Renamed cyg_pci_config_interrupt to cyg_pci_translate_interrupt. + Untabified. + +1999-08-16 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/io_pci.h: + + Parent PCI package under package on which it depends. + +1999-08-16 Jesper Skov <jskov@cygnus.co.uk> + + * include/pci.h: + * src/pci.c (cyg_pci_config_interrupt): + * include/pci_hw.h: + * src/pci_hw.c (cyg_pcihw_config_interrupt): + Added interrupt configuration functions. + +1999-08-13 Jesper Skov <jskov@cygnus.co.uk> + + * include/pci_cfg.h: + * include/pci.h: + * src/pci_hw.c: + * src/pci.c: + Extended cyg_pci_device and API. + Renamed HAL macros. + Put physical address in base_map. + + (cyg_pci_get_device_info): Fix switch. Clear base_size when device + enabled. + +1999-08-12 Jesper Skov <jskov@cygnus.co.uk> + + * include/pci_hw.h: + * include/pci_cfg.h: + * include/pci.h: + * src/pci_hw.c: + * src/pci.c: + Renamed some registers. Fixed some bad arguments. Added forgotten + externCs. + cyg_pci_configure_device fleshed out a bit. + + * First half-empty files checked in. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/include/pci.h @@ -0,0 +1,286 @@ +#ifndef CYGONCE_PCI_H +#define CYGONCE_PCI_H +//============================================================================= +// +// pci.h +// +// PCI library +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, from design by nickg +// Contributors: jskov +// Date: 1999-08-09 +// Purpose: PCI configuration access +// Usage: +// #include <cyg/io/pci.h> +// Description: +// This library provides a set of routines for accessing +// the PCI bus configuration space in a portable manner. +// This is provided by two APIs. The high level API (defined +// by this file) is used by device drivers, or other code, to +// access the PCI configuration space portably. The low level +// API (see pci_hw.h) is used by the PCI library itself +// to access the hardware in a platform-specific manner and +// may also be used by device drivers to access the PCI +// configuration space directly. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> +#include <cyg/io/pci_cfg.h> +#include <cyg/io/pci_hw.h> + +//------------------------------------------------------------------ +// The PCI memory space can span 64 bits, IO space only 32 bits +typedef CYG_WORD64 CYG_PCI_ADDRESS64; +typedef CYG_WORD32 CYG_PCI_ADDRESS32; + +//------------------------------------------------------------------ +// Macros for manufacturing and decomposing device ids +typedef CYG_WORD32 cyg_pci_device_id; // PCI device ID + +#define CYG_PCI_DEV_MAKE_ID(__bus,__devfn) (((__bus)<<16)|((__devfn)<<8)) +#define CYG_PCI_DEV_GET_BUS(__devid) ((__devid>>16)&0xFF) +#define CYG_PCI_DEV_GET_DEVFN(__devid) ((__devid>>8)&0xFF) + +#define CYG_PCI_NULL_DEVID 0xffffffff + +//------------------------------------------------------------------ +// PCI device data definitions and structures + +typedef enum { + CYG_PCI_HEADER_NORMAL = 0, + CYG_PCI_HEADER_BRIDGE = 1, + CYG_PCI_HEADER_CARDBUS_BRIDGE = 2 +} cyg_pci_header_type; + +typedef struct // PCI device data +{ + cyg_pci_device_id devid; // ID of this device + + // The following fields are read out of the + // config space for this device. + + cyg_uint16 vendor; // vendor ID + cyg_uint16 device; // device ID + cyg_uint16 command; // command register + cyg_uint16 status; // status register + cyg_uint32 class_rev; // class+revision + cyg_uint8 cache_line_size; // cache line size + cyg_uint8 latency_timer; // latency timer + cyg_pci_header_type header_type; // header type + cyg_uint8 bist; // Built-in Self-Test + cyg_uint32 base_address[6]; // Memory base address registers + + // The following fields are used by the resource allocation + // routines to keep track of allocated resources. + + cyg_uint32 base_size[6]; // Memory size for each base address + cyg_uint32 base_map[6]; // Physical address mapped + + CYG_ADDRWORD hal_vector; // HAL interrupt vector used by + // device if int_line!=0 + + // One of the following unions will be filled in according to + // the value of the header_type field. + + union + { + struct + { + cyg_uint32 cardbus_cis; // CardBus CIS Pointer + cyg_uint16 sub_vendor; // subsystem vendor id + cyg_uint16 sub_id; // subsystem id + cyg_uint32 rom_address; // ROM address register + cyg_uint8 cap_list; // capability list + cyg_uint8 reserved1[7]; + cyg_uint8 int_line; // interrupt line + cyg_uint8 int_pin; // interrupt pin + cyg_uint8 min_gnt; // timeslice request + cyg_uint8 max_lat; // priority-level request + } normal; + struct + { + // Not yet supported + } bridge; + struct + { + // Not yet supported + } cardbus_bridge; + } header; +} cyg_pci_device; + +//------------------------------------------------------------------------ +// Init +externC void cyg_pci_init( void ); + +//------------------------------------------------------------------------ +// Common device configuration access functions + +// This function gets the PCI configuration information for the +// device indicated in devid. The common fields of the cyg_pci_device +// structure, and the appropriate fields of the relevant header union +// member are filled in from the device's configuration space. If the +// device has not been enabled, then this function will also fetch +// the size and type information from the base address registers and +// place it in the base_size[] array. +externC void cyg_pci_get_device_info ( cyg_pci_device_id devid, + cyg_pci_device *dev_info ); + + +// This function sets the PCI configuration information for the +// device indicated in devid. Only the configuration space registers +// that are writable are actually written. Once all the fields have +// been written, the device info will be read back into *dev_info, so +// that it reflects the true state of the hardware. +externC void cyg_pci_set_device_info ( cyg_pci_device_id devid, + cyg_pci_device *dev_info ); + +//------------------------------------------------------------------------ +// Device find functions + +// Searches the PCI bus configuration space for a device with the +// given vendor and device ids. The search starts at the device +// pointed to by devid, or at the first slot if it contains +// CYG_PCI_NULL_DEVID. *devid will be updated with the ID of the next +// device found. Returns true if one is found and false if not. +externC cyg_bool cyg_pci_find_device( cyg_uint16 vendor, cyg_uint16 device, + cyg_pci_device_id *devid ); + + +// Searches the PCI bus configuration space for a device with the +// given class code. The search starts at the device pointed to by +// devid, or at the first slot if it contains CYG_PCI_NULL_DEVID. +// *devid will be updated with the ID of the next device found. +// Returns true if one is found and false if not. +externC cyg_bool cyg_pci_find_class( cyg_uint32 dev_class, + cyg_pci_device_id *devid ); + +// Searches the PCI configuration space for the next valid device +// after cur_devid. If cur_devid is given the value +// CYG_PCI_NULL_DEVID, then the search starts at the first slot. It +// is permitted for next_devid to point to the cur_devid. Returns +// true if another device is found and false if not. +externC cyg_bool cyg_pci_find_next( cyg_pci_device_id cur_devid, + cyg_pci_device_id *next_devid ); + +//------------------------------------------------------------------------ +// Resource Allocation +// These routines allocate memory and IO space to PCI devices. + +// Allocate memory and IO space to all base address registers using +// the current memory and IO base addresses in the library. If +// dev_info does not contain valid base_size[] entries, then the +// result is false. +externC cyg_bool cyg_pci_configure_device( cyg_pci_device *dev_info ); + +// These routines set the base addresses for memory and IO mappings +// to be used by the memory allocation routines. Normally these base +// addresses will be set to default values based on the platform, +// these routines allow those to be changed by application code if +// necessary. +externC void cyg_pci_set_memory_base( CYG_PCI_ADDRESS64 base ); +externC void cyg_pci_set_io_base( CYG_PCI_ADDRESS32 base ); + +// These routines allocate memory or IO space to the base address +// register indicated by bar. The base address in *base will be +// correctly aligned and the address of the next free location will +// be written back into it if the allocation succeeds. If the base +// address register is of the wrong type for this allocation, or +// dev_info does not contain valid base_size[] entries, the result is +// false. +externC cyg_bool cyg_pci_allocate_memory( cyg_pci_device *dev_info, + cyg_uint32 bar, + CYG_PCI_ADDRESS64 *base ); +externC cyg_bool cyg_pci_allocate_io( cyg_pci_device *dev_info, + cyg_uint32 bar, + CYG_PCI_ADDRESS32 *base ); + +// Translate the device's PCI interrupt (INTA#-INTD#) to the +// associated HAL vector. This may also depend on which slot the +// device occupies. If the device may generate interrupts, the +// translated vector number will be stored in vec and the result is +// true. Otherwise the result is false. +externC cyg_bool cyg_pci_translate_interrupt( cyg_pci_device *dev_info, + CYG_ADDRWORD *vec ); + + +//---------------------------------------------------------------------- +// Specific device configuration access functions + +// Read functions +// These functions read registers of the appropriate size from the +// configuration space of the given device. They should mainly be +// used to access registers that are device specific. General PCI +// registers are best accessed through cyg_pci_get_device_info(). +externC void cyg_pci_read_config_uint8( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint8 *val); +externC void cyg_pci_read_config_uint16( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint16 *val); +externC void cyg_pci_read_config_uint32( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint32 *val); + +// Write functions +// These functions write registers of the appropriate size to the +// configuration space of the given device. They should mainly be +// used to access registers that are device specific. General PCI +// registers are best accessed through +// cyg_pci_get_device_info(). Writing the general registers this way +// may render the contents of a cyg_pci_device structure invalid. +externC void cyg_pci_write_config_uint8( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint8 val); +externC void cyg_pci_write_config_uint16( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint16 val); +externC void cyg_pci_write_config_uint32( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint32 val); + + +//---------------------------------------------------------------------- +// Functions private to the PCI library. These should only be used by +// tests. +externC cyg_bool cyg_pci_allocate_memory_priv(cyg_pci_device *dev_info, + cyg_uint32 bar, + CYG_PCI_ADDRESS64 *base, + CYG_PCI_ADDRESS64 *assigned_addr); +externC cyg_bool cyg_pci_allocate_io_priv( cyg_pci_device *dev_info, + cyg_uint32 bar, + CYG_PCI_ADDRESS32 *base, + CYG_PCI_ADDRESS32 *assigned_addr); + + +//---------------------------------------------------------------------- +// Bus probing limits. +#define CYG_PCI_MAX_BUS 1 // FIXME: Just the one for now +#define CYG_PCI_MAX_DEV 32 +#define CYG_PCI_MAX_FN 8 +#define CYG_PCI_MAX_BAR 6 + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PCI_H +// End of pci.h
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/include/pci_cfg.h @@ -0,0 +1,1026 @@ +#ifndef CYGONCE_PCI_CFG_H +#define CYGONCE_PCI_CFG_H +//============================================================================= +// +// pci_cfg.h +// +// PCI configuration definitions +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 1999-08-09 +// Purpose: Provides PCI configuration information +// (common structure layout & defined vendor/class codes) +// Usage: +// #include <cyg/io/pci_cfg.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//---------------------------------------------------------------------- +// PCI Configuration structure offsets +#define CYG_PCI_CFG_VENDOR 0x00 +#define CYG_PCI_CFG_DEVICE 0x02 +#define CYG_PCI_CFG_COMMAND 0x04 +#define CYG_PCI_CFG_STATUS 0x06 +#define CYG_PCI_CFG_CLASS_REV 0x08 +#define CYG_PCI_CFG_CACHE_LINE_SIZE 0x0c +#define CYG_PCI_CFG_LATENCY_TIMER 0x0d +#define CYG_PCI_CFG_HEADER_TYPE 0x0e +#define CYG_PCI_CFG_BIST 0x0f +#define CYG_PCI_CFG_BAR_BASE 0x10 +#define CYG_PCI_CFG_BAR_0 0x10 +#define CYG_PCI_CFG_BAR_1 0x14 +#define CYG_PCI_CFG_BAR_2 0x18 +#define CYG_PCI_CFG_BAR_3 0x1c +#define CYG_PCI_CFG_BAR_4 0x20 +#define CYG_PCI_CFG_BAR_5 0x14 +#define CYG_PCI_CFG_CARDBUS_CIS 0x28 +#define CYG_PCI_CFG_SUB_VENDOR 0x2c +#define CYG_PCI_CFG_SUB_ID 0x2e +#define CYG_PCI_CFG_ROM_ADDRESS 0x30 +#define CYG_PCI_CFG_CAP_LIST 0x34 +#define CYG_PCI_CFG_INT_LINE 0x3c +#define CYG_PCI_CFG_INT_PIN 0x3d +#define CYG_PCI_CFG_MIN_GNT 0x3e +#define CYG_PCI_CFG_MAX_LAT 0x3f + +//----------------------------------------------------------------- +// PCI Control bits + +// Command +#define CYG_PCI_CFG_COMMAND_IO 0x0001 +#define CYG_PCI_CFG_COMMAND_MEMORY 0x0002 +#define CYG_PCI_CFG_COMMAND_MASTER 0x0004 +#define CYG_PCI_CFG_COMMAND_SPECIAL 0x0008 +#define CYG_PCI_CFG_COMMAND_INVALIDATE 0x0010 +#define CYG_PCI_CFG_COMMAND_VGA_SNOOP 0x0020 +#define CYG_PCI_CFG_COMMAND_PARITY 0x0040 +#define CYG_PCI_CFG_COMMAND_WAIT 0x0080 +#define CYG_PCI_CFG_COMMAND_SERR 0x0100 +#define CYG_PCI_CFG_COMMAND_FAST_BACK 0x0200 + +// Consider the device active if any of these bits are set. +#define CYG_PCI_CFG_COMMAND_ACTIVE \ + (CYG_PCI_CFG_COMMAND_IO \ + |CYG_PCI_CFG_COMMAND_MEMORY \ + |CYG_PCI_CFG_COMMAND_MASTER) + +// Header type +#define CYG_PCI_CFG_HEADER_TYPE_MASK 0x7f +#define CYG_PCI_CFG_HEADER_TYPE_MF 0x80 + +// BAR +#define CYG_PCI_CFG_BAR_SPACE_MASK 0x00000001 +#define CYG_PCI_CFG_BAR_SPACE_MEM 0x00000000 +#define CYG_PCI_CFG_BAR_SPACE_IO 0x00000001 + +#define CYG_PRI_CFG_BAR_MEM_TYPE_MASK 0x00000006 +#define CYG_PRI_CFG_BAR_MEM_TYPE_32 0x00000000 +#define CYG_PRI_CFG_BAR_MEM_TYPE_1M 0x00000002 +#define CYG_PRI_CFG_BAR_MEM_TYPE_64 0x00000004 + +#define CYG_PRI_CFG_BAR_MEM_PREFETCH 0x00000008 + +#define CYG_PRI_CFG_BAR_MEM_MASK 0xfffffff0 +#define CYG_PRI_CFG_BAR_IO_MASK 0xfffffffc + + +//---------------------------------------------------------------------- +// PCI Vendor IDs +/*********************************************************************** + Can be extracted from the PCICODE List at http://www.yourvote.com/pci + maintained by Jib Boemler. Use the below Perl script and fix any + bad vendor names by hand. + +#!/usr/bin/perl +while(<>) { + if (/PCI_VENTABLE/) { + %mvendors = {}; + @vendors = (); + @codes = (); + while(<>) { + # Collect vendor names and codes. + if (m!.*0x([0-9A-F]{4}), \"([^\"]*)\".*!) { + $c = lc($1); + $v = uc($2); + $v =~ tr/-+ \/&.!/______ /; + $v =~ s/__/_/g; + $v =~ s/_$//; + push @vendors, $v; + push @codes, $c; + # Count occurences of vendor name. + $mvendors{$v} += 1; + } + last if (/;/); + } + # Ouput definitions. + while ($#vendors >= 0) { + $v = shift @vendors; + $c = shift @codes; + + $o = "#define CYG_PCI_VENDOR_$v"; + # If a vendor name occurs more than once, append code + # to get unique definitions. + if ($mvendors{$v} > 1) { + $o .= "_0x$c"; + } + print $o . " " x (60-length($o)) . "0x$c\n"; + } + } +} +***********************************************************************/ + +//---------------------- AUTO GENERATED START -------------------------- +#define CYG_PCI_VENDOR_LOCKHEED_MARTIN 0x003d +#define CYG_PCI_VENDOR_COMPAQ_0x0e11 0x0e11 +#define CYG_PCI_VENDOR_SYM 0x1000 +#define CYG_PCI_VENDOR_ATI 0x1002 +#define CYG_PCI_VENDOR_ULSI 0x1003 +#define CYG_PCI_VENDOR_VLSI 0x1004 +#define CYG_PCI_VENDOR_AVANCE_0x1005 0x1005 +#define CYG_PCI_VENDOR_REPLY 0x1006 +#define CYG_PCI_VENDOR_NETFRAME 0x1007 +#define CYG_PCI_VENDOR_EPSON 0x1008 +#define CYG_PCI_VENDOR_PHOENIX 0x100a +#define CYG_PCI_VENDOR_NSC 0x100b +#define CYG_PCI_VENDOR_TSENG_0x100c 0x100c +#define CYG_PCI_VENDOR_AST 0x100d +#define CYG_PCI_VENDOR_WEITEK 0x100e +#define CYG_PCI_VENDOR_VLOGIC 0x1010 +#define CYG_PCI_VENDOR_DEC_0x1011 0x1011 +#define CYG_PCI_VENDOR_MICRONICS 0x1012 +#define CYG_PCI_VENDOR_CIRRUS 0x1013 +#define CYG_PCI_VENDOR_IBM 0x1014 +#define CYG_PCI_VENDOR_LSIL 0x1015 +#define CYG_PCI_VENDOR_FUJITSU_ICL 0x1016 +#define CYG_PCI_VENDOR_SPEA 0x1017 +#define CYG_PCI_VENDOR_UNISYS 0x1018 +#define CYG_PCI_VENDOR_ECS 0x1019 +#define CYG_PCI_VENDOR_NCR 0x101a +#define CYG_PCI_VENDOR_VITESSE 0x101b +#define CYG_PCI_VENDOR_WD 0x101c +#define CYG_PCI_VENDOR_AMI 0x101e +#define CYG_PCI_VENDOR_PICTURETEL 0x101f +#define CYG_PCI_VENDOR_HITACHI_0x1020 0x1020 +#define CYG_PCI_VENDOR_OKI 0x1021 +#define CYG_PCI_VENDOR_AMD 0x1022 +#define CYG_PCI_VENDOR_TRIDENT 0x1023 +#define CYG_PCI_VENDOR_ZENITH_0x1024 0x1024 +#define CYG_PCI_VENDOR_ACER 0x1025 +#define CYG_PCI_VENDOR_DELL 0x1028 +#define CYG_PCI_VENDOR_SIEM_NIX 0x1029 +#define CYG_PCI_VENDOR_LSI 0x102a +#define CYG_PCI_VENDOR_MATROX 0x102b +#define CYG_PCI_VENDOR_C_T 0x102c +#define CYG_PCI_VENDOR_WYSE 0x102d +#define CYG_PCI_VENDOR_OLIVETTI 0x102e +#define CYG_PCI_VENDOR_TOSHIBA_0x102f 0x102f +#define CYG_PCI_VENDOR_TMC_0x1030 0x1030 +#define CYG_PCI_VENDOR_MIRO 0x1031 +#define CYG_PCI_VENDOR_COMPAQ_0x1032 0x1032 +#define CYG_PCI_VENDOR_NEC_0x1033 0x1033 +#define CYG_PCI_VENDOR_BURNDY 0x1034 +#define CYG_PCI_VENDOR_C_CRL 0x1035 +#define CYG_PCI_VENDOR_FDOMAIN 0x1036 +#define CYG_PCI_VENDOR_HITACHI_0x1037 0x1037 +#define CYG_PCI_VENDOR_AMP 0x1038 +#define CYG_PCI_VENDOR_SIS 0x1039 +#define CYG_PCI_VENDOR_SEIKO 0x103a +#define CYG_PCI_VENDOR_TATUNG 0x103b +#define CYG_PCI_VENDOR_HP 0x103c +#define CYG_PCI_VENDOR_SOLLIDAY 0x103e +#define CYG_PCI_VENDOR_LOGIC_MOD 0x103f +#define CYG_PCI_VENDOR_KUBOTA 0x1040 +#define CYG_PCI_VENDOR_COMPUTREND 0x1041 +#define CYG_PCI_VENDOR_PC_TECH 0x1042 +#define CYG_PCI_VENDOR_ASUSTEK 0x1043 +#define CYG_PCI_VENDOR_DPT 0x1044 +#define CYG_PCI_VENDOR_OPTI 0x1045 +#define CYG_PCI_VENDOR_IPC 0x1046 +#define CYG_PCI_VENDOR_GENOA 0x1047 +#define CYG_PCI_VENDOR_ELSA 0x1048 +#define CYG_PCI_VENDOR_FOUNTAIN 0x1049 +#define CYG_PCI_VENDOR_STM 0x104a +#define CYG_PCI_VENDOR_BUSLOGOC 0x104b +#define CYG_PCI_VENDOR_TI 0x104c +#define CYG_PCI_VENDOR_SONY 0x104d +#define CYG_PCI_VENDOR_OAK 0x104e +#define CYG_PCI_VENDOR_CO_TIME 0x104f +#define CYG_PCI_VENDOR_WINBOND 0x1050 +#define CYG_PCI_VENDOR_ANIGMA 0x1051 +#define CYG_PCI_VENDOR_YOUNG 0x1052 +#define CYG_PCI_VENDOR_HITACHI_0x1054 0x1054 +#define CYG_PCI_VENDOR_EFAR 0x1055 +#define CYG_PCI_VENDOR_ICL 0x1056 +#define CYG_PCI_VENDOR_MOTOROLA_0x1057 0x1057 +#define CYG_PCI_VENDOR_E_TR 0x1058 +#define CYG_PCI_VENDOR_TEKNOR 0x1059 +#define CYG_PCI_VENDOR_PROMISE 0x105a +#define CYG_PCI_VENDOR_FOXCONN 0x105b +#define CYG_PCI_VENDOR_WIPRO 0x105c +#define CYG_PCI_VENDOR_NUMBER_NINE 0x105d +#define CYG_PCI_VENDOR_VTECH 0x105e +#define CYG_PCI_VENDOR_INFOTRONIC 0x105f +#define CYG_PCI_VENDOR_UMC 0x1060 +#define CYG_PCI_VENDOR_8X8 0x1061 +#define CYG_PCI_VENDOR_MASPAR 0x1062 +#define CYG_PCI_VENDOR_OOA 0x1063 +#define CYG_PCI_VENDOR_ALCATEL 0x1064 +#define CYG_PCI_VENDOR_TM 0x1065 +#define CYG_PCI_VENDOR_PICOPOWER 0x1066 +#define CYG_PCI_VENDOR_MITSUBISHI_0x1067 0x1067 +#define CYG_PCI_VENDOR_DIV_TECH 0x1068 +#define CYG_PCI_VENDOR_MYLEX 0x1069 +#define CYG_PCI_VENDOR_ATEN 0x106a +#define CYG_PCI_VENDOR_APPLE 0x106b +#define CYG_PCI_VENDOR_HYUNDAI 0x106c +#define CYG_PCI_VENDOR_SEQUENT 0x106d +#define CYG_PCI_VENDOR_DFI 0x106e +#define CYG_PCI_VENDOR_CITYGATE 0x106f +#define CYG_PCI_VENDOR_DAEWOO 0x1070 +#define CYG_PCI_VENDOR_MITAC 0x1071 +#define CYG_PCI_VENDOR_GIT 0x1072 +#define CYG_PCI_VENDOR_YAMAHA 0x1073 +#define CYG_PCI_VENDOR_NEXGEN 0x1074 +#define CYG_PCI_VENDOR_AIR 0x1075 +#define CYG_PCI_VENDOR_CHAINTECH_0x1076 0x1076 +#define CYG_PCI_VENDOR_Q_LOGIC 0x1077 +#define CYG_PCI_VENDOR_CYRIX 0x1078 +#define CYG_PCI_VENDOR_I_BUS 0x1079 +#define CYG_PCI_VENDOR_NETWORTH 0x107a +#define CYG_PCI_VENDOR_GATEWAY 0x107b +#define CYG_PCI_VENDOR_GOLDSTAR 0x107c +#define CYG_PCI_VENDOR_LEADTEK 0x107d +#define CYG_PCI_VENDOR_INTERPHASE 0x107e +#define CYG_PCI_VENDOR_DTC 0x107f +#define CYG_PCI_VENDOR_CONTAQ 0x1080 +#define CYG_PCI_VENDOR_SUPERMAC 0x1081 +#define CYG_PCI_VENDOR_EFA 0x1082 +#define CYG_PCI_VENDOR_FOREX 0x1083 +#define CYG_PCI_VENDOR_PARADOR 0x1084 +#define CYG_PCI_VENDOR_TULIP 0x1085 +#define CYG_PCI_VENDOR_J_BOND 0x1086 +#define CYG_PCI_VENDOR_CACHE 0x1087 +#define CYG_PCI_VENDOR_MS_SON 0x1088 +#define CYG_PCI_VENDOR_DG 0x1089 +#define CYG_PCI_VENDOR_BIT3 0x108a +#define CYG_PCI_VENDOR_ELONEX 0x108c +#define CYG_PCI_VENDOR_OLICOM 0x108d +#define CYG_PCI_VENDOR_SUN 0x108e +#define CYG_PCI_VENDOR_SYSTEMSOFT 0x108f +#define CYG_PCI_VENDOR_ENCORE 0x1090 +#define CYG_PCI_VENDOR_INTERGRAPH 0x1091 +#define CYG_PCI_VENDOR_DIAMOND 0x1092 +#define CYG_PCI_VENDOR_NAT_INST 0x1093 +#define CYG_PCI_VENDOR_FIC 0x1094 +#define CYG_PCI_VENDOR_CMD 0x1095 +#define CYG_PCI_VENDOR_ALACRON 0x1096 +#define CYG_PCI_VENDOR_APPIAN 0x1097 +#define CYG_PCI_VENDOR_QUANTUM_0x1098 0x1098 +#define CYG_PCI_VENDOR_SAMSUNG_0x1099 0x1099 +#define CYG_PCI_VENDOR_PACKARD_BELL 0x109a +#define CYG_PCI_VENDOR_GEMLIGHT 0x109b +#define CYG_PCI_VENDOR_MEGACHIPS 0x109c +#define CYG_PCI_VENDOR_ZIDA 0x109d +#define CYG_PCI_VENDOR_BROOKTREE 0x109e +#define CYG_PCI_VENDOR_TRIGEM_0x109f 0x109f +#define CYG_PCI_VENDOR_MEIDENSHA 0x10a0 +#define CYG_PCI_VENDOR_JUKO 0x10a1 +#define CYG_PCI_VENDOR_QUANTUM_0x10a2 0x10a2 +#define CYG_PCI_VENDOR_EVEREX 0x10a3 +#define CYG_PCI_VENDOR_GLOBE 0x10a4 +#define CYG_PCI_VENDOR_RACAL 0x10a5 +#define CYG_PCI_VENDOR_INFORMTECH 0x10a6 +#define CYG_PCI_VENDOR_BENCHMARQ 0x10a7 +#define CYG_PCI_VENDOR_SIERRA_0x10a8 0x10a8 +#define CYG_PCI_VENDOR_SG 0x10a9 +#define CYG_PCI_VENDOR_ACC 0x10aa +#define CYG_PCI_VENDOR_DIGICOM 0x10ab +#define CYG_PCI_VENDOR_HONEYWELL 0x10ac +#define CYG_PCI_VENDOR_SYMPHONY_0x10ad 0x10ad +#define CYG_PCI_VENDOR_CORNERSTONE 0x10ae +#define CYG_PCI_VENDOR_MCS_0x10af 0x10af +#define CYG_PCI_VENDOR_CARDEXPERT 0x10b0 +#define CYG_PCI_VENDOR_CABLETRON 0x10b1 +#define CYG_PCI_VENDOR_RAYTHEON 0x10b2 +#define CYG_PCI_VENDOR_DATABOOK 0x10b3 +#define CYG_PCI_VENDOR_STB 0x10b4 +#define CYG_PCI_VENDOR_PLX 0x10b5 +#define CYG_PCI_VENDOR_MADGE 0x10b6 +#define CYG_PCI_VENDOR_3COM 0x10b7 +#define CYG_PCI_VENDOR_STANDARD 0x10b8 +#define CYG_PCI_VENDOR_ALI 0x10b9 +#define CYG_PCI_VENDOR_MITSUBISHI_0x10ba 0x10ba +#define CYG_PCI_VENDOR_DAPHA 0x10bb +#define CYG_PCI_VENDOR_ALR 0x10bc +#define CYG_PCI_VENDOR_SURECOM 0x10bd +#define CYG_PCI_VENDOR_TSENG_0x10be 0x10be +#define CYG_PCI_VENDOR_MOST 0x10bf +#define CYG_PCI_VENDOR_BOCA 0x10c0 +#define CYG_PCI_VENDOR_ICM 0x10c1 +#define CYG_PCI_VENDOR_AUSPEX 0x10c2 +#define CYG_PCI_VENDOR_SAMSUNG_0x10c3 0x10c3 +#define CYG_PCI_VENDOR_AWARD 0x10c4 +#define CYG_PCI_VENDOR_XEROX 0x10c5 +#define CYG_PCI_VENDOR_RAMBUS 0x10c6 +#define CYG_PCI_VENDOR_MEDIA_VISION 0x10c7 +#define CYG_PCI_VENDOR_NEOMAGIC 0x10c8 +#define CYG_PCI_VENDOR_DATAEXPERT 0x10c9 +#define CYG_PCI_VENDOR_FUJITSU_0x10ca 0x10ca +#define CYG_PCI_VENDOR_OMRON 0x10cb +#define CYG_PCI_VENDOR_MENTOR 0x10cc +#define CYG_PCI_VENDOR_ADVANSYS 0x10cd +#define CYG_PCI_VENDOR_RADIUS 0x10ce +#define CYG_PCI_VENDOR_TTI 0x10cf +#define CYG_PCI_VENDOR_FUJITSU_0x10d0 0x10d0 +#define CYG_PCI_VENDOR_FUTURE 0x10d1 +#define CYG_PCI_VENDOR_MOLEX 0x10d2 +#define CYG_PCI_VENDOR_JABIL 0x10d3 +#define CYG_PCI_VENDOR_HUALON 0x10d4 +#define CYG_PCI_VENDOR_AUTOLOGIC 0x10d5 +#define CYG_PCI_VENDOR_CETIA 0x10d6 +#define CYG_PCI_VENDOR_BCM 0x10d7 +#define CYG_PCI_VENDOR_APL 0x10d8 +#define CYG_PCI_VENDOR_MACRONIX 0x10d9 +#define CYG_PCI_VENDOR_T_C 0x10da +#define CYG_PCI_VENDOR_ROHM 0x10db +#define CYG_PCI_VENDOR_CERN 0x10dc +#define CYG_PCI_VENDOR_E_S 0x10dd +#define CYG_PCI_VENDOR_NVIDIA_0x10de 0x10de +#define CYG_PCI_VENDOR_EMULEX 0x10df +#define CYG_PCI_VENDOR_IMS 0x10e0 +#define CYG_PCI_VENDOR_TEKRAM_0x10e1 0x10e1 +#define CYG_PCI_VENDOR_APTIX 0x10e2 +#define CYG_PCI_VENDOR_TUNDRA 0x10e3 +#define CYG_PCI_VENDOR_TANDEM 0x10e4 +#define CYG_PCI_VENDOR_MIC 0x10e5 +#define CYG_PCI_VENDOR_GAINBERY 0x10e6 +#define CYG_PCI_VENDOR_VADEM 0x10e7 +#define CYG_PCI_VENDOR_AMCC 0x10e8 +#define CYG_PCI_VENDOR_ALPS 0x10e9 +#define CYG_PCI_VENDOR_INTERGRAPHICS 0x10ea +#define CYG_PCI_VENDOR_ARTIST 0x10eb +#define CYG_PCI_VENDOR_REALTEK 0x10ec +#define CYG_PCI_VENDOR_ASCII 0x10ed +#define CYG_PCI_VENDOR_XILINX 0x10ee +#define CYG_PCI_VENDOR_RACORE 0x10ef +#define CYG_PCI_VENDOR_PERITEK 0x10f0 +#define CYG_PCI_VENDOR_TYAN 0x10f1 +#define CYG_PCI_VENDOR_ACHME 0x10f2 +#define CYG_PCI_VENDOR_ALARIS 0x10f3 +#define CYG_PCI_VENDOR_S_MOS 0x10f4 +#define CYG_PCI_VENDOR_NKK 0x10f5 +#define CYG_PCI_VENDOR_CREATIVE 0x10f6 +#define CYG_PCI_VENDOR_MATSUSHITA_0x10f7 0x10f7 +#define CYG_PCI_VENDOR_ALTOS 0x10f8 +#define CYG_PCI_VENDOR_PC_DIRECT 0x10f9 +#define CYG_PCI_VENDOR_TRUEVISION 0x10fa +#define CYG_PCI_VENDOR_THESYS 0x10fb +#define CYG_PCI_VENDOR_I_O 0x10fc +#define CYG_PCI_VENDOR_SOYO 0x10fd +#define CYG_PCI_VENDOR_FAST 0x10fe +#define CYG_PCI_VENDOR_NCUBE 0x10ff +#define CYG_PCI_VENDOR_JAZZ 0x1100 +#define CYG_PCI_VENDOR_INITIO 0x1101 +#define CYG_PCI_VENDOR_CREATIVE_LABS 0x1102 +#define CYG_PCI_VENDOR_TRIONES 0x1103 +#define CYG_PCI_VENDOR_RASTEROPS 0x1104 +#define CYG_PCI_VENDOR_SIGMA_0x1105 0x1105 +#define CYG_PCI_VENDOR_VIA 0x1106 +#define CYG_PCI_VENDOR_STRATUS 0x1107 +#define CYG_PCI_VENDOR_PROTEON 0x1108 +#define CYG_PCI_VENDOR_COGENT 0x1109 +#define CYG_PCI_VENDOR_SIEMENS 0x110a +#define CYG_PCI_VENDOR_CHROMATIC 0x110b +#define CYG_PCI_VENDOR_MINI_MAX 0x110c +#define CYG_PCI_VENDOR_ZNYX 0x110d +#define CYG_PCI_VENDOR_CPU_TECH 0x110e +#define CYG_PCI_VENDOR_ROSS 0x110f +#define CYG_PCI_VENDOR_POWERHOUSE 0x1110 +#define CYG_PCI_VENDOR_SCO 0x1111 +#define CYG_PCI_VENDOR_OSICOM 0x1112 +#define CYG_PCI_VENDOR_ACCTON 0x1113 +#define CYG_PCI_VENDOR_ATMEL 0x1114 +#define CYG_PCI_VENDOR_DUPONT 0x1115 +#define CYG_PCI_VENDOR_DATA_TRANS 0x1116 +#define CYG_PCI_VENDOR_DATACUBE 0x1117 +#define CYG_PCI_VENDOR_BERG 0x1118 +#define CYG_PCI_VENDOR_VORTEX 0x1119 +#define CYG_PCI_VENDOR_EFF_NET 0x111a +#define CYG_PCI_VENDOR_TELEDYNE 0x111b +#define CYG_PCI_VENDOR_TRICORD 0x111c +#define CYG_PCI_VENDOR_IDT 0x111d +#define CYG_PCI_VENDOR_ELDEC 0x111e +#define CYG_PCI_VENDOR_PDI 0x111f +#define CYG_PCI_VENDOR_EMC 0x1120 +#define CYG_PCI_VENDOR_ZILOG 0x1121 +#define CYG_PCI_VENDOR_MULTI_TECH 0x1122 +#define CYG_PCI_VENDOR_EDI 0x1123 +#define CYG_PCI_VENDOR_LEUTRON 0x1124 +#define CYG_PCI_VENDOR_EUROCORE 0x1125 +#define CYG_PCI_VENDOR_VIGRA 0x1126 +#define CYG_PCI_VENDOR_FORE 0x1127 +#define CYG_PCI_VENDOR_FIRMWORKS 0x1129 +#define CYG_PCI_VENDOR_HERMES 0x112a +#define CYG_PCI_VENDOR_LINOTYPE 0x112b +#define CYG_PCI_VENDOR_ZENITH_0x112c 0x112c +#define CYG_PCI_VENDOR_RAVICAD 0x112d +#define CYG_PCI_VENDOR_INFOMEDIA 0x112e +#define CYG_PCI_VENDOR_IMAGTECH 0x112f +#define CYG_PCI_VENDOR_COMPUTERVISION 0x1130 +#define CYG_PCI_VENDOR_PHILIPS 0x1131 +#define CYG_PCI_VENDOR_MITEL 0x1132 +#define CYG_PCI_VENDOR_EIC 0x1133 +#define CYG_PCI_VENDOR_MCS_0x1134 0x1134 +#define CYG_PCI_VENDOR_FUJI 0x1135 +#define CYG_PCI_VENDOR_MOMENTUM 0x1136 +#define CYG_PCI_VENDOR_CISCO 0x1137 +#define CYG_PCI_VENDOR_ZIATECH 0x1138 +#define CYG_PCI_VENDOR_DYN_PICT 0x1139 +#define CYG_PCI_VENDOR_FWB 0x113a +#define CYG_PCI_VENDOR_NCD 0x113b +#define CYG_PCI_VENDOR_CYCLONE 0x113c +#define CYG_PCI_VENDOR_LEADING_EDGE 0x113d +#define CYG_PCI_VENDOR_SANYO 0x113e +#define CYG_PCI_VENDOR_EQUINOX 0x113f +#define CYG_PCI_VENDOR_INTERVOICE 0x1140 +#define CYG_PCI_VENDOR_CREST 0x1141 +#define CYG_PCI_VENDOR_ALLIANCE 0x1142 +#define CYG_PCI_VENDOR_NETPOWER_0x1143 0x1143 +#define CYG_PCI_VENDOR_CINN_MIL 0x1144 +#define CYG_PCI_VENDOR_WORKBIT 0x1145 +#define CYG_PCI_VENDOR_FORCE 0x1146 +#define CYG_PCI_VENDOR_INTERFACE 0x1147 +#define CYG_PCI_VENDOR_S_K 0x1148 +#define CYG_PCI_VENDOR_WIN_SYSTEM 0x1149 +#define CYG_PCI_VENDOR_VMIC 0x114a +#define CYG_PCI_VENDOR_CANOPUS 0x114b +#define CYG_PCI_VENDOR_ANNABOOKS 0x114c +#define CYG_PCI_VENDOR_IC_CORP 0x114d +#define CYG_PCI_VENDOR_NIKON 0x114e +#define CYG_PCI_VENDOR_STARGATE 0x114f +#define CYG_PCI_VENDOR_TMC_0x1150 0x1150 +#define CYG_PCI_VENDOR_JAE 0x1151 +#define CYG_PCI_VENDOR_MEGATEK 0x1152 +#define CYG_PCI_VENDOR_LAND_WIN 0x1153 +#define CYG_PCI_VENDOR_MELCO 0x1154 +#define CYG_PCI_VENDOR_PINE 0x1155 +#define CYG_PCI_VENDOR_PERISCOPE 0x1156 +#define CYG_PCI_VENDOR_AVSYS 0x1157 +#define CYG_PCI_VENDOR_VOARX 0x1158 +#define CYG_PCI_VENDOR_MUTECH 0x1159 +#define CYG_PCI_VENDOR_HARLEQUIN 0x115a +#define CYG_PCI_VENDOR_PARALLAX 0x115b +#define CYG_PCI_VENDOR_PHOTRON 0x115c +#define CYG_PCI_VENDOR_XIRCOM 0x115d +#define CYG_PCI_VENDOR_PEER 0x115e +#define CYG_PCI_VENDOR_MAXTOR 0x115f +#define CYG_PCI_VENDOR_MEGASOFT 0x1160 +#define CYG_PCI_VENDOR_PFU 0x1161 +#define CYG_PCI_VENDOR_OA_LAB 0x1162 +#define CYG_PCI_VENDOR_RENDITION 0x1163 +#define CYG_PCI_VENDOR_APT 0x1164 +#define CYG_PCI_VENDOR_IMAGRAPH 0x1165 +#define CYG_PCI_VENDOR_PEQUR 0x1166 +#define CYG_PCI_VENDOR_MUTOH 0x1167 +#define CYG_PCI_VENDOR_THINE 0x1168 +#define CYG_PCI_VENDOR_CDAC 0x1169 +#define CYG_PCI_VENDOR_POLARIS 0x116a +#define CYG_PCI_VENDOR_CONNECTWARE 0x116b +#define CYG_PCI_VENDOR_INT_RES 0x116c +#define CYG_PCI_VENDOR_EFI 0x116e +#define CYG_PCI_VENDOR_WKSTA_TECH 0x116f +#define CYG_PCI_VENDOR_INVENTEC 0x1170 +#define CYG_PCI_VENDOR_LOUGH_SOUND 0x1171 +#define CYG_PCI_VENDOR_ALTERA 0x1172 +#define CYG_PCI_VENDOR_ADOBE 0x1173 +#define CYG_PCI_VENDOR_BRIDGEPORT 0x1174 +#define CYG_PCI_VENDOR_MITRON 0x1175 +#define CYG_PCI_VENDOR_SBE 0x1176 +#define CYG_PCI_VENDOR_SILICON_ENG 0x1177 +#define CYG_PCI_VENDOR_ALFA 0x1178 +#define CYG_PCI_VENDOR_TOSHIBA_0x1179 0x1179 +#define CYG_PCI_VENDOR_A_TREND 0x117a +#define CYG_PCI_VENDOR_LG_ELEC 0x117b +#define CYG_PCI_VENDOR_ATTO 0x117c +#define CYG_PCI_VENDOR_B_D 0x117d +#define CYG_PCI_VENDOR_T_R 0x117e +#define CYG_PCI_VENDOR_ICS 0x117f +#define CYG_PCI_VENDOR_RICOH 0x1180 +#define CYG_PCI_VENDOR_TELMATICS 0x1181 +#define CYG_PCI_VENDOR_FUJIKURA 0x1183 +#define CYG_PCI_VENDOR_FORKS_0x1184 0x1184 +#define CYG_PCI_VENDOR_DATAWORLD 0x1185 +#define CYG_PCI_VENDOR_D_LINK 0x1186 +#define CYG_PCI_VENDOR_ATL 0x1187 +#define CYG_PCI_VENDOR_SHIMA 0x1188 +#define CYG_PCI_VENDOR_MATSUSHITA_0x1189 0x1189 +#define CYG_PCI_VENDOR_HILEVEL 0x118a +#define CYG_PCI_VENDOR_HYPERTEC 0x118b +#define CYG_PCI_VENDOR_COROLLARY 0x118c +#define CYG_PCI_VENDOR_BITFLOW 0x118d +#define CYG_PCI_VENDOR_HERMSTEDT 0x118e +#define CYG_PCI_VENDOR_GREEN 0x118f +#define CYG_PCI_VENDOR_ARTOP 0x1191 +#define CYG_PCI_VENDOR_DENSAN 0x1192 +#define CYG_PCI_VENDOR_ZEITNET 0x1193 +#define CYG_PCI_VENDOR_TOUCAN 0x1194 +#define CYG_PCI_VENDOR_RATOC 0x1195 +#define CYG_PCI_VENDOR_HYTEC 0x1196 +#define CYG_PCI_VENDOR_GAGE 0x1197 +#define CYG_PCI_VENDOR_LAMBDA 0x1198 +#define CYG_PCI_VENDOR_ATTACHMATE 0x1199 +#define CYG_PCI_VENDOR_MIND_SHARE 0x119a +#define CYG_PCI_VENDOR_OMEGA 0x119b +#define CYG_PCI_VENDOR_ITI 0x119c +#define CYG_PCI_VENDOR_BUG 0x119d +#define CYG_PCI_VENDOR_FUJITSU_0x119e 0x119e +#define CYG_PCI_VENDOR_BULL 0x119f +#define CYG_PCI_VENDOR_CONVEX 0x11a0 +#define CYG_PCI_VENDOR_HAMAMATSU 0x11a1 +#define CYG_PCI_VENDOR_SIERRA_0x11a2 0x11a2 +#define CYG_PCI_VENDOR_DEURETZBACHER 0x11a3 +#define CYG_PCI_VENDOR_BARCO 0x11a4 +#define CYG_PCI_VENDOR_MICROUNITY 0x11a5 +#define CYG_PCI_VENDOR_PURE_DATA 0x11a6 +#define CYG_PCI_VENDOR_POWER_COMP 0x11a7 +#define CYG_PCI_VENDOR_SYSTECH 0x11a8 +#define CYG_PCI_VENDOR_INNOSYS 0x11a9 +#define CYG_PCI_VENDOR_ACTEL 0x11aa +#define CYG_PCI_VENDOR_GALILEO 0x11ab +#define CYG_PCI_VENDOR_CANON 0x11ac +#define CYG_PCI_VENDOR_LITE_ON 0x11ad +#define CYG_PCI_VENDOR_SCITEX 0x11ae +#define CYG_PCI_VENDOR_PRO_LOG 0x11af +#define CYG_PCI_VENDOR_V3 0x11b0 +#define CYG_PCI_VENDOR_APRICOT 0x11b1 +#define CYG_PCI_VENDOR_KODAK 0x11b2 +#define CYG_PCI_VENDOR_BARR 0x11b3 +#define CYG_PCI_VENDOR_LEITCH 0x11b4 +#define CYG_PCI_VENDOR_RADSTONE 0x11b5 +#define CYG_PCI_VENDOR_UNITED_VIDEO 0x11b6 +#define CYG_PCI_VENDOR_MOTOROLA_0x11b7 0x11b7 +#define CYG_PCI_VENDOR_XPOINT 0x11b8 +#define CYG_PCI_VENDOR_PATHLIGHT 0x11b9 +#define CYG_PCI_VENDOR_VIDEOTRON 0x11ba +#define CYG_PCI_VENDOR_PYRAMID 0x11bb +#define CYG_PCI_VENDOR_NET_PERIPH 0x11bc +#define CYG_PCI_VENDOR_PINNACLE 0x11bd +#define CYG_PCI_VENDOR_IMI 0x11be +#define CYG_PCI_VENDOR_ASTRODESIGN 0x11bf +#define CYG_PCI_VENDOR_H_P 0x11c0 +#define CYG_PCI_VENDOR_AT_T 0x11c1 +#define CYG_PCI_VENDOR_SAND 0x11c2 +#define CYG_PCI_VENDOR_NEC_0x11c3 0x11c3 +#define CYG_PCI_VENDOR_DOC_TECH 0x11c4 +#define CYG_PCI_VENDOR_SHIVA 0x11c5 +#define CYG_PCI_VENDOR_DAINIPPON 0x11c6 +#define CYG_PCI_VENDOR_D_C_M 0x11c7 +#define CYG_PCI_VENDOR_DOLPHIN 0x11c8 +#define CYG_PCI_VENDOR_MAGMA 0x11c9 +#define CYG_PCI_VENDOR_LSI_SYS 0x11ca +#define CYG_PCI_VENDOR_SPECIALIX 0x11cb +#define CYG_PCI_VENDOR_M_K 0x11cc +#define CYG_PCI_VENDOR_HAL 0x11cd +#define CYG_PCI_VENDOR_PRI 0x11ce +#define CYG_PCI_VENDOR_PEC 0x11cf +#define CYG_PCI_VENDOR_LORAL 0x11d0 +#define CYG_PCI_VENDOR_AURAVISION 0x11d1 +#define CYG_PCI_VENDOR_INTERCOM 0x11d2 +#define CYG_PCI_VENDOR_TRANCELL 0x11d3 +#define CYG_PCI_VENDOR_AD 0x11d4 +#define CYG_PCI_VENDOR_IKON 0x11d5 +#define CYG_PCI_VENDOR_TEKELEC 0x11d6 +#define CYG_PCI_VENDOR_TRENTON 0x11d7 +#define CYG_PCI_VENDOR_ITD 0x11d8 +#define CYG_PCI_VENDOR_TEC 0x11d9 +#define CYG_PCI_VENDOR_NOVELL 0x11da +#define CYG_PCI_VENDOR_SEGA 0x11db +#define CYG_PCI_VENDOR_QUESTRA 0x11dc +#define CYG_PCI_VENDOR_CROSFIELD 0x11dd +#define CYG_PCI_VENDOR_ZORAN 0x11de +#define CYG_PCI_VENDOR_NEW_WAVE 0x11df +#define CYG_PCI_VENDOR_CRAY 0x11e0 +#define CYG_PCI_VENDOR_GEC_PLESSEY 0x11e1 +#define CYG_PCI_VENDOR_SAMSUNG_0x11e2 0x11e2 +#define CYG_PCI_VENDOR_QUICKLOGIC 0x11e3 +#define CYG_PCI_VENDOR_SECOND_WAVE 0x11e4 +#define CYG_PCI_VENDOR_IIX 0x11e5 +#define CYG_PCI_VENDOR_MITSUI 0x11e6 +#define CYG_PCI_VENDOR_TOSHIBA_0x11e7 0x11e7 +#define CYG_PCI_VENDOR_DPSI 0x11e8 +#define CYG_PCI_VENDOR_HIGHWATER 0x11e9 +#define CYG_PCI_VENDOR_ELSAG 0x11ea +#define CYG_PCI_VENDOR_FORMATION 0x11eb +#define CYG_PCI_VENDOR_CORECO 0x11ec +#define CYG_PCI_VENDOR_MEDIAMATICS 0x11ed +#define CYG_PCI_VENDOR_DOME 0x11ee +#define CYG_PCI_VENDOR_NICOLET 0x11ef +#define CYG_PCI_VENDOR_COMPU_SHACK 0x11f0 +#define CYG_PCI_VENDOR_SYMBIOS 0x11f1 +#define CYG_PCI_VENDOR_PIC_TEL 0x11f2 +#define CYG_PCI_VENDOR_KEITHLEY 0x11f3 +#define CYG_PCI_VENDOR_KINETIC 0x11f4 +#define CYG_PCI_VENDOR_COMP_DEV 0x11f5 +#define CYG_PCI_VENDOR_POWERMATIC 0x11f6 +#define CYG_PCI_VENDOR_S_A 0x11f7 +#define CYG_PCI_VENDOR_PMC_SIERRA 0x11f8 +#define CYG_PCI_VENDOR_I_CUBE 0x11f9 +#define CYG_PCI_VENDOR_KASAN 0x11fa +#define CYG_PCI_VENDOR_DATEL 0x11fb +#define CYG_PCI_VENDOR_SILICON_MAGIC 0x11fc +#define CYG_PCI_VENDOR_HIGH_STREET 0x11fd +#define CYG_PCI_VENDOR_COMTROL 0x11fe +#define CYG_PCI_VENDOR_SCION 0x11ff +#define CYG_PCI_VENDOR_CSS 0x1200 +#define CYG_PCI_VENDOR_VISTA 0x1201 +#define CYG_PCI_VENDOR_NETWORK_GEN 0x1202 +#define CYG_PCI_VENDOR_AGFA 0x1203 +#define CYG_PCI_VENDOR_LATTICE 0x1204 +#define CYG_PCI_VENDOR_ARRAY 0x1205 +#define CYG_PCI_VENDOR_AMDAHL 0x1206 +#define CYG_PCI_VENDOR_PARSYTEC 0x1208 +#define CYG_PCI_VENDOR_SCI_SYS 0x1209 +#define CYG_PCI_VENDOR_SYNAPTEL 0x120a +#define CYG_PCI_VENDOR_ADAPTIVE 0x120b +#define CYG_PCI_VENDOR_COMP_LABS 0x120d +#define CYG_PCI_VENDOR_CYCLADES 0x120e +#define CYG_PCI_VENDOR_ESSENTIAL 0x120f +#define CYG_PCI_VENDOR_HYPERPARALLEL 0x1210 +#define CYG_PCI_VENDOR_BRAINTECH 0x1211 +#define CYG_PCI_VENDOR_KINGSTON 0x1212 +#define CYG_PCI_VENDOR_AISI 0x1213 +#define CYG_PCI_VENDOR_PERF_TECH 0x1214 +#define CYG_PCI_VENDOR_INTERWARE 0x1215 +#define CYG_PCI_VENDOR_PURUP 0x1216 +#define CYG_PCI_VENDOR_O2MICRO 0x1217 +#define CYG_PCI_VENDOR_HYBRICON 0x1218 +#define CYG_PCI_VENDOR_FIRST_VIRTUAL 0x1219 +#define CYG_PCI_VENDOR_3DFX 0x121a +#define CYG_PCI_VENDOR_ATM 0x121b +#define CYG_PCI_VENDOR_NIPPON_TEXA 0x121c +#define CYG_PCI_VENDOR_LIPPERT 0x121d +#define CYG_PCI_VENDOR_CSPI 0x121e +#define CYG_PCI_VENDOR_ARCUS 0x121f +#define CYG_PCI_VENDOR_ARIEL 0x1220 +#define CYG_PCI_VENDOR_CONTEC 0x1221 +#define CYG_PCI_VENDOR_ANCOR 0x1222 +#define CYG_PCI_VENDOR_HEURIKON 0x1223 +#define CYG_PCI_VENDOR_INT_IMG 0x1224 +#define CYG_PCI_VENDOR_POWER_IO 0x1225 +#define CYG_PCI_VENDOR_TECH_SOURCE 0x1227 +#define CYG_PCI_VENDOR_NORSK 0x1228 +#define CYG_PCI_VENDOR_DATA_KIN 0x1229 +#define CYG_PCI_VENDOR_INT_TELECOM 0x122a +#define CYG_PCI_VENDOR_LG_IND 0x122b +#define CYG_PCI_VENDOR_SICAN 0x122c +#define CYG_PCI_VENDOR_AZTECH 0x122d +#define CYG_PCI_VENDOR_XYRATEX 0x122e +#define CYG_PCI_VENDOR_ANDREW 0x122f +#define CYG_PCI_VENDOR_FISHCAMP 0x1230 +#define CYG_PCI_VENDOR_W_MCCOACH 0x1231 +#define CYG_PCI_VENDOR_GPT 0x1232 +#define CYG_PCI_VENDOR_BUS_TECH 0x1233 +#define CYG_PCI_VENDOR_TECHNICAL 0x1234 +#define CYG_PCI_VENDOR_RISQ_MOD 0x1235 +#define CYG_PCI_VENDOR_SIGMA_0x1236 0x1236 +#define CYG_PCI_VENDOR_ALTA_TECH 0x1237 +#define CYG_PCI_VENDOR_ADTRAN 0x1238 +#define CYG_PCI_VENDOR_3DO 0x1239 +#define CYG_PCI_VENDOR_VISICOM 0x123a +#define CYG_PCI_VENDOR_SEEQ 0x123b +#define CYG_PCI_VENDOR_CENTURY_SYS 0x123c +#define CYG_PCI_VENDOR_EDT 0x123d +#define CYG_PCI_VENDOR_C_CUBE 0x123f +#define CYG_PCI_VENDOR_MARATHON 0x1240 +#define CYG_PCI_VENDOR_DSC 0x1241 +#define CYG_PCI_VENDOR_DELPHAX 0x1243 +#define CYG_PCI_VENDOR_AVM 0x1244 +#define CYG_PCI_VENDOR_APD 0x1245 +#define CYG_PCI_VENDOR_DIPIX 0x1246 +#define CYG_PCI_VENDOR_XYLON 0x1247 +#define CYG_PCI_VENDOR_CENTRAL_DATA 0x1248 +#define CYG_PCI_VENDOR_SAMSUNG_0x1249 0x1249 +#define CYG_PCI_VENDOR_AEG 0x124a +#define CYG_PCI_VENDOR_GREENSPRING 0x124b +#define CYG_PCI_VENDOR_SOLITRON 0x124c +#define CYG_PCI_VENDOR_STALLION 0x124d +#define CYG_PCI_VENDOR_CYLINK 0x124e +#define CYG_PCI_VENDOR_INFORTREND 0x124f +#define CYG_PCI_VENDOR_HITACHI_0x1250 0x1250 +#define CYG_PCI_VENDOR_VLSI_SOL 0x1251 +#define CYG_PCI_VENDOR_GUZIK 0x1253 +#define CYG_PCI_VENDOR_LINEAR_SYSTEMS 0x1254 +#define CYG_PCI_VENDOR_OPTIBASE 0x1255 +#define CYG_PCI_VENDOR_PERCEPTIVE 0x1256 +#define CYG_PCI_VENDOR_VERTEX 0x1257 +#define CYG_PCI_VENDOR_GILBARCO 0x1258 +#define CYG_PCI_VENDOR_ALLIED_TSYN 0x1259 +#define CYG_PCI_VENDOR_ABB_PWR 0x125a +#define CYG_PCI_VENDOR_ASIX 0x125b +#define CYG_PCI_VENDOR_AURORA 0x125c +#define CYG_PCI_VENDOR_ESS 0x125d +#define CYG_PCI_VENDOR_SPECVIDEO 0x125e +#define CYG_PCI_VENDOR_CONCURRENT 0x125f +#define CYG_PCI_VENDOR_HARRIS 0x1260 +#define CYG_PCI_VENDOR_MATSUSHITA_0x1261 0x1261 +#define CYG_PCI_VENDOR_ES_COMP 0x1262 +#define CYG_PCI_VENDOR_SONIC_SOL 0x1263 +#define CYG_PCI_VENDOR_AVAL_NAG 0x1264 +#define CYG_PCI_VENDOR_CASIO 0x1265 +#define CYG_PCI_VENDOR_MICRODYNE 0x1266 +#define CYG_PCI_VENDOR_SA_TELECOM 0x1267 +#define CYG_PCI_VENDOR_TEKTRONIX 0x1268 +#define CYG_PCI_VENDOR_THOMSON_CSF 0x1269 +#define CYG_PCI_VENDOR_LEXMARK 0x126a +#define CYG_PCI_VENDOR_ADAX 0x126b +#define CYG_PCI_VENDOR_NORTEL 0x126c +#define CYG_PCI_VENDOR_SPLASH 0x126d +#define CYG_PCI_VENDOR_SUMITOMO 0x126e +#define CYG_PCI_VENDOR_SIL_MOTION 0x126f +#define CYG_PCI_VENDOR_OLYMPUS 0x1270 +#define CYG_PCI_VENDOR_GW_INSTR 0x1271 +#define CYG_PCI_VENDOR_TELEMATICS 0x1272 +#define CYG_PCI_VENDOR_HUGHES 0x1273 +#define CYG_PCI_VENDOR_ENSONIQ 0x1274 +#define CYG_PCI_VENDOR_NETAPP 0x1275 +#define CYG_PCI_VENDOR_SW_NET_TECH 0x1276 +#define CYG_PCI_VENDOR_COMSTREAM 0x1277 +#define CYG_PCI_VENDOR_TRANSTECH 0x1278 +#define CYG_PCI_VENDOR_TRANSMETA 0x1279 +#define CYG_PCI_VENDOR_ROCKWELL_SEMI 0x127a +#define CYG_PCI_VENDOR_PIXERA 0x127b +#define CYG_PCI_VENDOR_CROSSPOINT 0x127c +#define CYG_PCI_VENDOR_VELA_RES 0x127d +#define CYG_PCI_VENDOR_WINNOW 0x127e +#define CYG_PCI_VENDOR_FUJIFILM_0x127f 0x127f +#define CYG_PCI_VENDOR_PHOTOSCRIPT 0x1280 +#define CYG_PCI_VENDOR_YOKOGAWA 0x1281 +#define CYG_PCI_VENDOR_DAVICOM 0x1282 +#define CYG_PCI_VENDOR_ITEXPRESS 0x1283 +#define CYG_PCI_VENDOR_SAHARA 0x1284 +#define CYG_PCI_VENDOR_PLAT_TECH 0x1285 +#define CYG_PCI_VENDOR_MAZET 0x1286 +#define CYG_PCI_VENDOR_LUXSONOR 0x1287 +#define CYG_PCI_VENDOR_TIMESTEP 0x1288 +#define CYG_PCI_VENDOR_AVC_TECH 0x1289 +#define CYG_PCI_VENDOR_ASANTE 0x128a +#define CYG_PCI_VENDOR_TRANSWITCH 0x128b +#define CYG_PCI_VENDOR_RETIX 0x128c +#define CYG_PCI_VENDOR_G2_NET 0x128d +#define CYG_PCI_VENDOR_SAMHO 0x128e +#define CYG_PCI_VENDOR_TATENO 0x128f +#define CYG_PCI_VENDOR_SORD 0x1290 +#define CYG_PCI_VENDOR_NCS_COMP 0x1291 +#define CYG_PCI_VENDOR_TRITECH 0x1292 +#define CYG_PCI_VENDOR_M_REALITY 0x1293 +#define CYG_PCI_VENDOR_RHETOREX 0x1294 +#define CYG_PCI_VENDOR_IMAGENATION 0x1295 +#define CYG_PCI_VENDOR_KOFAX 0x1296 +#define CYG_PCI_VENDOR_HOLCO 0x1297 +#define CYG_PCI_VENDOR_SPELLCASTER 0x1298 +#define CYG_PCI_VENDOR_KNOW_TECH 0x1299 +#define CYG_PCI_VENDOR_VMETRO 0x129a +#define CYG_PCI_VENDOR_IMG_ACCESS 0x129b +#define CYG_PCI_VENDOR_COMPCORE 0x129d +#define CYG_PCI_VENDOR_VICTOR_JPN 0x129e +#define CYG_PCI_VENDOR_OEC_MED 0x129f +#define CYG_PCI_VENDOR_A_B 0x12a0 +#define CYG_PCI_VENDOR_SIMPACT 0x12a1 +#define CYG_PCI_VENDOR_NEWGEN 0x12a2 +#define CYG_PCI_VENDOR_LUCENT 0x12a3 +#define CYG_PCI_VENDOR_NTT_ELECT 0x12a4 +#define CYG_PCI_VENDOR_VISION_DYN 0x12a5 +#define CYG_PCI_VENDOR_SCALABLE 0x12a6 +#define CYG_PCI_VENDOR_AMO 0x12a7 +#define CYG_PCI_VENDOR_NEWS_DATACOM 0x12a8 +#define CYG_PCI_VENDOR_XIOTECH 0x12a9 +#define CYG_PCI_VENDOR_SDL 0x12aa +#define CYG_PCI_VENDOR_YUAN_YUAN 0x12ab +#define CYG_PCI_VENDOR_MEASUREX 0x12ac +#define CYG_PCI_VENDOR_MULTIDATA 0x12ad +#define CYG_PCI_VENDOR_ALTEON 0x12ae +#define CYG_PCI_VENDOR_TDK_USA 0x12af +#define CYG_PCI_VENDOR_JORGE_SCI 0x12b0 +#define CYG_PCI_VENDOR_GAMMALINK 0x12b1 +#define CYG_PCI_VENDOR_GEN_SIGNAL 0x12b2 +#define CYG_PCI_VENDOR_INTER_FACE 0x12b3 +#define CYG_PCI_VENDOR_FUTURE_TEL 0x12b4 +#define CYG_PCI_VENDOR_GRANITE 0x12b5 +#define CYG_PCI_VENDOR_NAT_MICRO 0x12b6 +#define CYG_PCI_VENDOR_ACUMEN 0x12b7 +#define CYG_PCI_VENDOR_KORG 0x12b8 +#define CYG_PCI_VENDOR_US_ROBOTICS 0x12b9 +#define CYG_PCI_VENDOR_BITTWARE 0x12ba +#define CYG_PCI_VENDOR_NIPPON_UNI 0x12bb +#define CYG_PCI_VENDOR_ARRAY_MICRO 0x12bc +#define CYG_PCI_VENDOR_COMPUTERM 0x12bd +#define CYG_PCI_VENDOR_ANCHOR_CHIPS 0x12be +#define CYG_PCI_VENDOR_FUJIFILM_0x12bf 0x12bf +#define CYG_PCI_VENDOR_INFIMED 0x12c0 +#define CYG_PCI_VENDOR_GMM_RES 0x12c1 +#define CYG_PCI_VENDOR_MENTEC 0x12c2 +#define CYG_PCI_VENDOR_HOLTEK 0x12c3 +#define CYG_PCI_VENDOR_CONN_TECH 0x12c4 +#define CYG_PCI_VENDOR_PICTUREL 0x12c5 +#define CYG_PCI_VENDOR_MITANI 0x12c6 +#define CYG_PCI_VENDOR_DIALOGIC 0x12c7 +#define CYG_PCI_VENDOR_G_FORCE 0x12c8 +#define CYG_PCI_VENDOR_GIGI_OPS 0x12c9 +#define CYG_PCI_VENDOR_I_C_ENGINES 0x12ca +#define CYG_PCI_VENDOR_ANTEX 0x12cb +#define CYG_PCI_VENDOR_PLUTO 0x12cc +#define CYG_PCI_VENDOR_AIMS_LAB 0x12cd +#define CYG_PCI_VENDOR_NETSPEED 0x12ce +#define CYG_PCI_VENDOR_PROPHET 0x12cf +#define CYG_PCI_VENDOR_GDE_SYS 0x12d0 +#define CYG_PCI_VENDOR_PSITECH 0x12d1 +#define CYG_PCI_VENDOR_NVIDIA_0x12d2 0x12d2 +#define CYG_PCI_VENDOR_VINGMED 0x12d3 +#define CYG_PCI_VENDOR_DGM_S 0x12d4 +#define CYG_PCI_VENDOR_EQUATOR 0x12d5 +#define CYG_PCI_VENDOR_ANALOGIC 0x12d6 +#define CYG_PCI_VENDOR_BIOTRONIC 0x12d7 +#define CYG_PCI_VENDOR_PERICOM 0x12d8 +#define CYG_PCI_VENDOR_ACULAB 0x12d9 +#define CYG_PCI_VENDOR_TRUE_TIME 0x12da +#define CYG_PCI_VENDOR_ANNAPOLIS 0x12db +#define CYG_PCI_VENDOR_SYMICRON 0x12dc +#define CYG_PCI_VENDOR_MGI 0x12dd +#define CYG_PCI_VENDOR_RAINBOW 0x12de +#define CYG_PCI_VENDOR_SBS_TECH 0x12df +#define CYG_PCI_VENDOR_CHASE 0x12e0 +#define CYG_PCI_VENDOR_NINTENDO 0x12e1 +#define CYG_PCI_VENDOR_DATUM 0x12e2 +#define CYG_PCI_VENDOR_IMATION 0x12e3 +#define CYG_PCI_VENDOR_BROOKTROUT 0x12e4 +#define CYG_PCI_VENDOR_CIREL 0x12e6 +#define CYG_PCI_VENDOR_SEBRING 0x12e7 +#define CYG_PCI_VENDOR_CRISC 0x12e8 +#define CYG_PCI_VENDOR_GE_SPACENET 0x12e9 +#define CYG_PCI_VENDOR_ZUKEN 0x12ea +#define CYG_PCI_VENDOR_AUREAL 0x12eb +#define CYG_PCI_VENDOR_3A_INTL 0x12ec +#define CYG_PCI_VENDOR_OPTIVISION 0x12ed +#define CYG_PCI_VENDOR_ORANGE_MICRO 0x12ee +#define CYG_PCI_VENDOR_VIENNA 0x12ef +#define CYG_PCI_VENDOR_PENTEK 0x12f0 +#define CYG_PCI_VENDOR_SORENSON 0x12f1 +#define CYG_PCI_VENDOR_GAMMAGRAPHX 0x12f2 +#define CYG_PCI_VENDOR_MEGATEL 0x12f4 +#define CYG_PCI_VENDOR_FORKS_0x12f5 0x12f5 +#define CYG_PCI_VENDOR_DAWSON_FR 0x12f6 +#define CYG_PCI_VENDOR_COGNEX 0x12f7 +#define CYG_PCI_VENDOR_ELECTRONIC_DESIGN 0x12f8 +#define CYG_PCI_VENDOR_FFT 0x12f9 +#define CYG_PCI_VENDOR_ESD 0x12fe +#define CYG_PCI_VENDOR_RADISYS 0x1331 +#define CYG_PCI_VENDOR_VIDEOMAIL 0x1335 +#define CYG_PCI_VENDOR_ODETICS 0x1347 +#define CYG_PCI_VENDOR_ABB_NETWORK_PARTN 0x135d +#define CYG_PCI_VENDOR_PTSC 0x137e +#define CYG_PCI_VENDOR_SYMPHONY_0x1c1c 0x1c1c +#define CYG_PCI_VENDOR_TEKRAM_0x1de1 0x1de1 +#define CYG_PCI_VENDOR_CHAINTECH_0x270f 0x270f +#define CYG_PCI_VENDOR_HANSOL 0x3000 +#define CYG_PCI_VENDOR_3DLABS 0x3d3d +#define CYG_PCI_VENDOR_AVANCE_0x4005 0x4005 +#define CYG_PCI_VENDOR_DEC_0x4143 0x4143 +#define CYG_PCI_VENDOR_UMAX_COMP 0x4680 +#define CYG_PCI_VENDOR_BUSLOGIC 0x4b10 +#define CYG_PCI_VENDOR_S3 0x5333 +#define CYG_PCI_VENDOR_TU_BERLIN 0x5455 +#define CYG_PCI_VENDOR_NETPOWER_0x5700 0x5700 +#define CYG_PCI_VENDOR_C4T 0x6374 +#define CYG_PCI_VENDOR_QUANCOM 0x8008 +#define CYG_PCI_VENDOR_INTEL 0x8086 +#define CYG_PCI_VENDOR_TRIGEM_0x8800 0x8800 +#define CYG_PCI_VENDOR_SIL_MAGIC 0x8888 +#define CYG_PCI_VENDOR_COMPUTONE 0x8e0e +#define CYG_PCI_VENDOR_ADAPTEC_0x9004 0x9004 +#define CYG_PCI_VENDOR_ADAPTEC_0x9005 0x9005 +#define CYG_PCI_VENDOR_ATRONICS 0x907f +#define CYG_PCI_VENDOR_MOT_ENGRG 0xc0fe +#define CYG_PCI_VENDOR_DY4 0xd4d4 +#define CYG_PCI_VENDOR_TIGER_JET 0xe159 +#define CYG_PCI_VENDOR_ARC 0xedd8 +#define CYG_PCI_VENDOR_BAD 0xffff +//----------------------- AUTO GENERATED END --------------------------- + +#define CYG_PCI_VENDOR_UNDEFINED 0xffff + +//---------------------------------------------------------------------- +// PCI Class IDs +#define CYG_PCI_CLASS_OLD_NONVGA 0x000000 +#define CYG_PCI_CLASS_OLD_VGA 0x000100 + +#define CYG_PCI_CLASS_STORAGE_SCSI 0x010000 +#define CYG_PCI_CLASS_STORAGE_IDE 0x010100 +#define CYG_PCI_CLASS_STORAGE_FLOPPY 0x010200 +#define CYG_PCI_CLASS_STORAGE_IPI 0x010300 +#define CYG_PCI_CLASS_STORAGE_RAID 0x010400 +#define CYG_PCI_CLASS_STORAGE_OTHER 0x018000 + +#define CYG_PCI_CLASS_NET_ETHERNET 0x020000 +#define CYG_PCI_CLASS_NET_TOKEN_RING 0x020100 +#define CYG_PCI_CLASS_NET_FDDI 0x020200 +#define CYG_PCI_CLASS_NET_ATM 0x020300 +#define CYG_PCI_CLASS_NET_OTHER 0x028000 + +#define CYG_PCI_CLASS_DISPLAY_PC_COMPAT_VGA 0x030000 +#define CYG_PCI_CLASS_DISPLAY_PC_COMPAT_8514 0x030001 +#define CYG_PCI_CLASS_DISPLAY_XGA 0x030100 +#define CYG_PCI_CLASS_DISPLAY_OTHER 0x038000 + +#define CYG_PCI_CLASS_MM_VIDEO 0x040000 +#define CYG_PCI_CLASS_MM_AUDIO 0x040100 +#define CYG_PCI_CLASS_MM_OTHER 0x048000 + +#define CYG_PCI_CLASS_MEM_RAM 0x050000 +#define CYG_PCI_CLASS_MEM_FLASH 0x050100 +#define CYG_PCI_CLASS_MEM_OTHER 0x058000 + +#define CYG_PCI_CLASS_BRIDGE_HOST_PCI 0x060000 +#define CYG_PCI_CLASS_BRIDGE_PCI_ISA 0x060100 +#define CYG_PCI_CLASS_BRIDGE_PCI_EISA 0x060200 +#define CYG_PCI_CLASS_BRIDGE_PCI_MC 0x060300 +#define CYG_PCI_CLASS_BRIDGE_PCI_PCI 0x060400 +#define CYG_PCI_CLASS_BRIDGE_PCI_PCMCIA 0x060500 +#define CYG_PCI_CLASS_BRIDGE_PCI_NUBUS 0x060600 +#define CYG_PCI_CLASS_BRIDGE_PCI_CARDBUS 0x060700 +#define CYG_PCI_CLASS_BRIDGE_OTHER 0x068000 + +#define CYG_PCI_CLASS_SCC_SERIAL_GENERIC 0x070000 +#define CYG_PCI_CLASS_SCC_SERIAL_16450 0x070001 +#define CYG_PCI_CLASS_SCC_SERIAL_16550 0x070002 +#define CYG_PCI_CLASS_SCC_PARALLEL_STANDARD 0x070100 +#define CYG_PCI_CLASS_SCC_PARALLEL_BIDRECTIONAL 0x070101 +#define CYG_PCI_CLASS_SCC_PARALLEL_ECP 0x070102 +#define CYG_PCI_CLASS_SCC_OTHER 0x078000 + +#define CYG_PCI_CLASS_BSP_PIC_GENERIC 0x080000 +#define CYG_PCI_CLASS_BSP_PIC_ISA 0x080001 +#define CYG_PCI_CLASS_BSP_PIC_PCI 0x080002 +#define CYG_PCI_CLASS_BSP_DMA_GENERIC 0x080100 +#define CYG_PCI_CLASS_BSP_DMA_ISA 0x080101 +#define CYG_PCI_CLASS_BSP_DMA_EISA 0x080102 +#define CYG_PCI_CLASS_BSP_TIMER_GENERIC 0x080200 +#define CYG_PCI_CLASS_BSP_TIMER_ISA 0x080201 +#define CYG_PCI_CLASS_BSP_TIMER_EISA 0x080202 +#define CYG_PCI_CLASS_BSP_RTC_GENERIC 0x080300 +#define CYG_PCI_CLASS_BSP_RTC_ISA 0x080301 +#define CYG_PCI_CLASS_BSP_OTHER 0x088000 + +#define CYG_PCI_CLASS_INPUT_KEYBOARD 0x090000 +#define CYG_PCI_CLASS_INPUT_DIGITIZER 0x090100 +#define CYG_PCI_CLASS_INPUT_MOUSE 0x090200 +#define CYG_PCI_CLASS_INPUT_OTHER 0x098000 + +#define CYG_PCI_CLASS_DOCKING_GENERIC 0x0a0000 +#define CYG_PCI_CLASS_DOCKING_OTHER 0x0a8000 + +#define CYG_PCI_CLASS_CPU_I386 0x0b0000 +#define CYG_PCI_CLASS_CPU_I486 0x0b0100 +#define CYG_PCI_CLASS_CPU_PENTIUM 0x0b0200 +#define CYG_PCI_CLASS_CPU_ALPHA 0x0b1000 +#define CYG_PCI_CLASS_CPU_POWERPC 0x0b2000 +#define CYG_PCI_CLASS_CPU_COPROCESSOR 0x0b8000 + +#define CYG_PCI_CLASS_SBC_FIREWIRE 0x0c0000 +#define CYG_PCI_CLASS_SBC_ACCESSBUS 0x0c0100 +#define CYG_PCI_CLASS_SBC_SSA 0x0c0200 +#define CYG_PCI_CLASS_SBC_USB 0x0c0300 +#define CYG_PCI_CLASS_SBC_FIBRE_CHANNEL 0x0c0400 + +#define CYG_PCI_CLASS_UNKNOWN 0xff0000 + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PCI_CFG_H +// End of pci_cfg.h
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/include/pci_hw.h @@ -0,0 +1,97 @@ +#ifndef CYGONCE_PCI_HW_H +#define CYGONCE_PCI_HW_H +//============================================================================= +// +// pci_hw.h +// +// PCI hardware library +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, from design by nickg +// Contributors: jskov +// Date: 1999-08-09 +// Purpose: PCI hardware configuration access +// Usage: +// #include <cyg/io/pci_hw.h> +// Description: +// This API is used by the PCI library to access the PCI bus +// configuration space. Although this should not normally be +// necessary, this API may also be used by device driver or +// application code to perform PCI bus operations not supported +// by the PCI library. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +// Rely on hal_io.h to include plf_io.h if it exists for the selected target. +#include <cyg/hal/hal_io.h> // HAL_PCI_ macros + +#ifdef HAL_PCI_INIT + +// This varible selects whether the PCI library gets built (requires +// HAL_PCI_INIT to be defined by the platform io header file) +#define CYG_PCI_PRESENT + +#include <cyg/infra/cyg_type.h> + +#include <cyg/io/pci_cfg.h> + + +// This is the lowest level where devfns are used. +#define CYG_PCI_DEV_MAKE_DEVFN(__dev, __fn) (((__dev)<<3)|(__fn)) +#define CYG_PCI_DEV_GET_DEV(__devfn) ((__devfn>>3)&0x1f) +#define CYG_PCI_DEV_GET_FN(__devfn) (__devfn&0x7) + +// Init +externC void cyg_pcihw_init(void); + +// Read functions +externC void cyg_pcihw_read_config_uint8( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint8 *val); +externC void cyg_pcihw_read_config_uint16( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint16 *val); +externC void cyg_pcihw_read_config_uint32( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint32 *val); + +// Write functions +externC void cyg_pcihw_write_config_uint8( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint8 val); +externC void cyg_pcihw_write_config_uint16( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint16 val); +externC void cyg_pcihw_write_config_uint32( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint32 val); + +// Interrupt translation +externC cyg_bool cyg_pcihw_translate_interrupt( cyg_uint8 bus, cyg_uint8 devfn, + CYG_ADDRWORD *vec); + +#endif // ifdef HAL_PCI_INIT + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PCI_HW_H +// End of pci_hw.h
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/include/pkgconf/io_pci.h @@ -0,0 +1,60 @@ +#ifndef CYGONCE_PKGCONF_IO_PCI_H +#define CYGONCE_PKGCONF_IO_PCI_H +// ==================================================================== +// +// pkgconf/io_pci.h +// +// PCI Library configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-08-12 +// Purpose: To allow the user to edit PCI library configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +/* ---------------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_IO_PCI { + display "PCI configuration library" + type bool + parent CYGPKG_IO + description " + The PCI configuration library provides initialization of devices + on the PCI bus. Functions to find and access these devices are + also provided." + } + + }}CFG_DATA */ + +#endif // CYGONCE_PKGCONF_IO_PCI_H +// EOF io_pci.h
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/src/PKGconf.mak @@ -0,0 +1,42 @@ +#============================================================================== +# +# makefile +# +# io/pci/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := io_pci +include ../../../../pkgconf/pkgconf.mak +include ../../../../pkgconf/system.mak + +LIBRARY := libtarget.a +COMPILE := pci.c pci_hw.c +EXTRAS_COMPILE := +OTHER_OBJS := +OTHER_CLEAN := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src +
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/src/pci.c @@ -0,0 +1,634 @@ +//============================================================================= +// +// pci.c +// +// PCI library +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, from design by nickg +// Contributors: jskov +// Date: 1999-08-09 +// Purpose: PCI configuration +// Description: +// PCI bus support library. +// Handles simple resource allocation for devices. +// Can configure 64bit devices, but drivers may need special +// magic to access all of this memory space - this is platform +// specific and the driver must know how to handle it on its own. +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/io/pci_hw.h> + +// CYG_PCI_PRESENT only gets defined for targets that provide PCI HAL support. +// See pci_hw.h for details. +#ifdef CYG_PCI_PRESENT + +#include <cyg/io/pci.h> +#include <cyg/infra/cyg_ass.h> + +static cyg_bool cyg_pci_lib_initialized = false; + +void +cyg_pci_init( void ) +{ + if (!cyg_pci_lib_initialized) { + // Initialize the PCI bus, preparing it for general access. + cyg_pcihw_init(); + + cyg_pci_lib_initialized = true; + } +} + +//--------------------------------------------------------------------------- +// Common device configuration access functions + +void +cyg_pci_get_device_info ( cyg_pci_device_id devid, cyg_pci_device *dev_info ) +{ + int i; + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(devid); + + dev_info->devid = devid; + + cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_VENDOR, + &dev_info->vendor); + cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_DEVICE, + &dev_info->device); + cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_COMMAND, + &dev_info->command); + cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_STATUS, + &dev_info->status); + cyg_pcihw_read_config_uint32(bus, devfn, CYG_PCI_CFG_CLASS_REV, + &dev_info->class_rev); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_CACHE_LINE_SIZE, + &dev_info->cache_line_size); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_LATENCY_TIMER, + &dev_info->latency_timer); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_HEADER_TYPE, + (cyg_uint8*)&dev_info->header_type); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_BIST, + &dev_info->bist); + + for (i = 0; i < CYG_PCI_MAX_BAR; i++){ + cyg_uint32 bar; + cyg_pcihw_read_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE + 4*i, + &bar); + dev_info->base_address[i] = bar; + } + + // If device is disabled, probe BARs for sizes. + if ((dev_info->command & CYG_PCI_CFG_COMMAND_ACTIVE) == 0) { + + for (i = 0; i < CYG_PCI_MAX_BAR; i++){ + cyg_uint32 size; + + cyg_pcihw_write_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE + 4*i, + 0xffffffff); + cyg_pcihw_read_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE + 4*i, + &size); + dev_info->base_size[i] = size; + dev_info->base_map[i] = 0xffffffff; + + + // Check for a 64bit memory region. + if (CYG_PCI_CFG_BAR_SPACE_MEM == + (size & CYG_PCI_CFG_BAR_SPACE_MASK)) { + if (size & CYG_PRI_CFG_BAR_MEM_TYPE_64) { + // Clear fields for next BAR - it's the upper 32 bits. + i++; + dev_info->base_size[i] = 0; + dev_info->base_map[i] = 0xffffffff; + } + } + } + } else { + // Clear the base map so we can recognize an already configured + // device. + for (i = 0; i < CYG_PCI_MAX_BAR; i++) { + dev_info->base_size[i] = 0; + } + } + + + switch (dev_info->header_type & CYG_PCI_CFG_HEADER_TYPE_MASK) { + case CYG_PCI_HEADER_NORMAL: + cyg_pcihw_read_config_uint32(bus, devfn, CYG_PCI_CFG_CARDBUS_CIS, + &dev_info->header.normal.cardbus_cis); + cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_SUB_VENDOR, + &dev_info->header.normal.sub_vendor); + cyg_pcihw_read_config_uint16(bus, devfn, CYG_PCI_CFG_SUB_ID, + &dev_info->header.normal.sub_id); + cyg_pcihw_read_config_uint32(bus, devfn, CYG_PCI_CFG_ROM_ADDRESS, + &dev_info->header.normal.rom_address); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_CAP_LIST, + &dev_info->header.normal.cap_list); + + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_INT_LINE, + &dev_info->header.normal.int_line); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_INT_PIN, + &dev_info->header.normal.int_pin); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_MIN_GNT, + &dev_info->header.normal.min_gnt); + cyg_pcihw_read_config_uint8(bus, devfn, CYG_PCI_CFG_MAX_LAT, + &dev_info->header.normal.max_lat); + break; + case CYG_PCI_HEADER_BRIDGE: + CYG_FAIL("PCI device header 'bridge' support not implemented"); + break; + case CYG_PCI_HEADER_CARDBUS_BRIDGE: + CYG_FAIL("PCI device header 'cardbus bridge' support not implemented"); + break; + default: + CYG_FAIL("Unknown PCI device header type"); + break; + } +} + +void +cyg_pci_set_device_info ( cyg_pci_device_id devid, cyg_pci_device *dev_info ) +{ + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(devid); + + // Only writable entries are updated. + cyg_pcihw_write_config_uint16(bus, devfn, CYG_PCI_CFG_COMMAND, + dev_info->command); + cyg_pcihw_write_config_uint16(bus, devfn, CYG_PCI_CFG_STATUS, + dev_info->status); + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_CACHE_LINE_SIZE, + dev_info->cache_line_size); + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_LATENCY_TIMER, + dev_info->latency_timer); + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_BIST, + dev_info->bist); + + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_0, + dev_info->base_address[0]); + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_1, + dev_info->base_address[1]); + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_2, + dev_info->base_address[2]); + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_3, + dev_info->base_address[3]); + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_4, + dev_info->base_address[4]); + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_5, + dev_info->base_address[5]); + + switch (dev_info->header_type & CYG_PCI_CFG_HEADER_TYPE_MASK) { + case CYG_PCI_HEADER_NORMAL: + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_CARDBUS_CIS, + dev_info->header.normal.cardbus_cis); + cyg_pcihw_write_config_uint16(bus, devfn, CYG_PCI_CFG_SUB_VENDOR, + dev_info->header.normal.sub_vendor); + cyg_pcihw_write_config_uint16(bus, devfn, CYG_PCI_CFG_SUB_ID, + dev_info->header.normal.sub_id); + cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_ROM_ADDRESS, + dev_info->header.normal.rom_address); + + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_INT_LINE, + dev_info->header.normal.int_line); + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_INT_PIN, + dev_info->header.normal.int_pin); + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_MIN_GNT, + dev_info->header.normal.min_gnt); + cyg_pcihw_write_config_uint8(bus, devfn, CYG_PCI_CFG_MAX_LAT, + dev_info->header.normal.max_lat); + break; + case CYG_PCI_HEADER_BRIDGE: + CYG_FAIL("PCI device header 'bridge' support not implemented"); + break; + case CYG_PCI_HEADER_CARDBUS_BRIDGE: + CYG_FAIL("PCI device header 'cardbus bridge' support not implemented"); + break; + default: + CYG_FAIL("Unknown PCI device header type"); + break; + } + + // Update values in dev_info. + cyg_pci_get_device_info(devid, dev_info); +} + + +//--------------------------------------------------------------------------- +// Specific device configuration access functions +void +cyg_pci_read_config_uint8( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint8 *val) +{ + cyg_pcihw_read_config_uint8(CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid), + offset, val); +} + +void +cyg_pci_read_config_uint16( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint16 *val) +{ + cyg_pcihw_read_config_uint16(CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid), + offset, val); +} + +void +cyg_pci_read_config_uint32( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint32 *val) +{ + cyg_pcihw_read_config_uint32(CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid), + offset, val); +} + + +// Write functions +void +cyg_pci_write_config_uint8( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint8 val) +{ + cyg_pcihw_write_config_uint8(CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid), + offset, val); +} + +void +cyg_pci_write_config_uint16( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint16 val) +{ + cyg_pcihw_write_config_uint16(CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid), + offset, val); +} + +void +cyg_pci_write_config_uint32( cyg_pci_device_id devid, + cyg_uint8 offset, cyg_uint32 val) +{ + cyg_pcihw_write_config_uint32(CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid), + offset, val); +} + +//------------------------------------------------------------------------ +// Device find functions + +cyg_bool +cyg_pci_find_next( cyg_pci_device_id cur_devid, + cyg_pci_device_id *next_devid ) +{ + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(cur_devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(cur_devid); + cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn); + cyg_uint8 fn = CYG_PCI_DEV_GET_FN(devfn); + + // If this is the initializer, start with 0/0/0 + if (CYG_PCI_NULL_DEVID == cur_devid) { + bus = dev = fn = 0; + } else { + // Otherwise, check multi-function bit of device's first function + cyg_uint8 header; + devfn = CYG_PCI_DEV_MAKE_DEVFN(dev, 0); + cyg_pcihw_read_config_uint8(bus, devfn, + CYG_PCI_CFG_HEADER_TYPE, &header); + if (header & CYG_PCI_CFG_HEADER_TYPE_MF) { + // Multi-function device. Increase fn. + fn++; + if (fn >= CYG_PCI_MAX_FN) { + fn = 0; + dev++; + } + } else { + // Single-function device. Skip to next. + dev++; + } + } + + // Note: Reset iterators in enclosing statement's "next" part. + // Allows resuming scan with given input values. + for (;bus < CYG_PCI_MAX_BUS; bus++, dev=0) { + for (;dev < CYG_PCI_MAX_DEV; dev++, fn=0) { + for (;fn < CYG_PCI_MAX_FN; fn++) { + cyg_uint16 vendor; + devfn = CYG_PCI_DEV_MAKE_DEVFN(dev, fn); + cyg_pcihw_read_config_uint16(bus, devfn, + CYG_PCI_CFG_VENDOR, &vendor); + + if (CYG_PCI_VENDOR_UNDEFINED != vendor) { + *next_devid = CYG_PCI_DEV_MAKE_ID(bus, devfn); + return true; + } + } + } + } + + return false; +} + +cyg_bool +cyg_pci_find_device( cyg_uint16 vendor, cyg_uint16 device, + cyg_pci_device_id *devid ) +{ + // Scan entire bus, check for matches on valid devices. + while (cyg_pci_find_next(*devid, devid)) { + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(*devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(*devid); + cyg_uint16 v, d; + + // Check that vendor matches. + cyg_pcihw_read_config_uint16(bus, devfn, + CYG_PCI_CFG_VENDOR, &v); + if (v != vendor) continue; + + // Check that device matches. + cyg_pcihw_read_config_uint16(bus, devfn, + CYG_PCI_CFG_DEVICE, &d); + if (d == device) + return true; + } + + return false; +} + +cyg_bool +cyg_pci_find_class( cyg_uint32 dev_class, cyg_pci_device_id *devid ) +{ + // Scan entire bus, check for matches on valid devices. + while (cyg_pci_find_next(*devid, devid)) { + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(*devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(*devid); + cyg_uint32 c; + + // Check that class code matches. + cyg_pcihw_read_config_uint32(bus, devfn, + CYG_PCI_CFG_CLASS_REV, &c); + c >>= 8; + if (c == dev_class) + return true; + } + + return false; +} + +//------------------------------------------------------------------------ +// Resource Allocation + +static CYG_PCI_ADDRESS64 cyg_pci_memory_base = HAL_PCI_ALLOC_BASE_MEMORY; +static CYG_PCI_ADDRESS32 cyg_pci_io_base = HAL_PCI_ALLOC_BASE_IO; + +void +cyg_pci_set_memory_base(CYG_PCI_ADDRESS64 base) +{ + cyg_pci_memory_base = base; +} + +void +cyg_pci_set_io_base(CYG_PCI_ADDRESS32 base) +{ + cyg_pci_io_base = base; +} + +cyg_bool +cyg_pci_configure_device( cyg_pci_device *dev_info ) +{ + int bar; + cyg_uint32 flags; + cyg_bool ret = false; + + // Check that device is inactive. + if ((dev_info->command & CYG_PCI_CFG_COMMAND_ACTIVE) != 0) + return false; + + for (bar = 0; bar < CYG_PCI_MAX_BAR; bar++) { + flags = dev_info->base_size[bar]; + + // No reason to scan beyond first inactive BAR. + if (0 == flags) + break; + + if ((flags & CYG_PCI_CFG_BAR_SPACE_MASK) == CYG_PCI_CFG_BAR_SPACE_MEM){ + ret |= cyg_pci_allocate_memory(dev_info, bar, + &cyg_pci_memory_base); + + // If this is a 64bit memory region, skip the next bar + // since it will contain the top 32 bits. + if (flags & CYG_PRI_CFG_BAR_MEM_TYPE_64) + bar++; + } else + ret |= cyg_pci_allocate_io(dev_info, bar, &cyg_pci_io_base); + + cyg_pci_translate_interrupt(dev_info, &dev_info->hal_vector); + } + + return ret; +} + +// This is the function that handles resource allocation. It doesn't +// affect the device state. +// Should not be called with top32bit-bar of a 64bit pair. +inline cyg_bool +cyg_pci_allocate_memory_priv( cyg_pci_device *dev_info, cyg_uint32 bar, + CYG_PCI_ADDRESS64 *base, + CYG_PCI_ADDRESS64 *assigned_addr) +{ + cyg_uint32 mem_type, flags; + CYG_PCI_ADDRESS64 size, aligned_addr; + + // Get the probed size and flags + flags = dev_info->base_size[bar]; + + // Decode size + size = (CYG_PCI_ADDRESS64) ((~(flags & CYG_PRI_CFG_BAR_MEM_MASK))+1); + + // Calculate address we will assign the device. + // This can be made more clever, specifically: + // 1) The lowest 1MB should be reserved for devices with 1M memory type. + // : Needs to be handled. + // 2) The low 32bit space should be reserved for devices with 32bit type. + // : With the usual handful of devices it is unlikely that the + // low 4GB space will become full. + // 3) A bitmap can be used to avoid fragmentation. + // : Again, unlikely to be necessary. + // + // For now, simply align to required size. + aligned_addr = (*base+size-1) & ~(size-1); + + // Is the request for memory space? + if (CYG_PCI_CFG_BAR_SPACE_MEM != (flags & CYG_PCI_CFG_BAR_SPACE_MASK)) + return false; + + // Check type of memory requested... + mem_type = CYG_PRI_CFG_BAR_MEM_TYPE_MASK & flags; + + // We don't handle <1MB devices optimally yet. + if (CYG_PRI_CFG_BAR_MEM_TYPE_1M == mem_type + && (aligned_addr + size) > 1024*1024) + return false; + + // Update the resource pointer and return values. + *base = aligned_addr+size; + *assigned_addr = aligned_addr; + + dev_info->base_map[bar] = (cyg_uint32) + (aligned_addr+HAL_PCI_PHYSICAL_MEMORY_BASE) & 0xffffffff; + + // If a 64bit region, store upper 32 bits in the next bar. + // Note: The CPU is not necessarily able to access the region + // linearly - it may have to do it in segments. Driver must handle that. + if (CYG_PRI_CFG_BAR_MEM_TYPE_64 == mem_type) { + dev_info->base_map[bar+1] = (cyg_uint32) + ((aligned_addr+HAL_PCI_PHYSICAL_MEMORY_BASE) >> 32) & 0xffffffff; + } + + return true; +} + +cyg_bool +cyg_pci_allocate_memory( cyg_pci_device *dev_info, cyg_uint32 bar, + CYG_PCI_ADDRESS64 *base) +{ + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(dev_info->devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(dev_info->devid); + CYG_PCI_ADDRESS64 assigned_addr; + cyg_bool ret; + + // Check that device is inactive. + if ((dev_info->command & CYG_PCI_CFG_COMMAND_ACTIVE) != 0) + return false; + + // Allocate memory space for the device. + ret = cyg_pci_allocate_memory_priv(dev_info, bar, base, &assigned_addr); + + if (ret) { + // Map the device and update the BAR in the dev_info structure. + cyg_pcihw_write_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE+4*bar, + (cyg_uint32) + (assigned_addr & 0xffffffff)); + cyg_pcihw_read_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE+4*bar, + &dev_info->base_address[bar]); + + // Handle upper 32 bits if necessary. + if (dev_info->base_size[bar] & CYG_PRI_CFG_BAR_MEM_TYPE_64) { + cyg_pcihw_write_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE+4*(bar+1), + (cyg_uint32) + ((assigned_addr >> 32)& 0xffffffff)); + cyg_pcihw_read_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE+4*(bar+1), + &dev_info->base_address[bar+1]); + } + } + + return ret; +} + +cyg_bool +cyg_pci_allocate_io_priv( cyg_pci_device *dev_info, cyg_uint32 bar, + CYG_PCI_ADDRESS32 *base, + CYG_PCI_ADDRESS32 *assigned_addr) +{ + cyg_uint32 flags, size; + CYG_PCI_ADDRESS32 aligned_addr; + + // Get the probed size and flags + flags = dev_info->base_size[bar]; + + // Decode size + size = (~(flags & CYG_PRI_CFG_BAR_IO_MASK))+1; + + // Calculate address we will assign the device. + // This can be made more clever. + // For now, simply align to required size. + aligned_addr = (*base+size-1) & ~(size-1); + + // Ensure the region fits within the 1MB IO space + if (aligned_addr+size > 1024*1024) + return false; + + // Is the request for IO space? + if (CYG_PCI_CFG_BAR_SPACE_IO != (flags & CYG_PCI_CFG_BAR_SPACE_MASK)) + return false; + + // Update the resource pointer and return values. + *base = aligned_addr+size; + dev_info->base_map[bar] = aligned_addr+HAL_PCI_PHYSICAL_IO_BASE; + *assigned_addr = aligned_addr; + + return true; +} + + +cyg_bool +cyg_pci_allocate_io( cyg_pci_device *dev_info, cyg_uint32 bar, + CYG_PCI_ADDRESS32 *base) +{ + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(dev_info->devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(dev_info->devid); + CYG_PCI_ADDRESS32 assigned_addr; + cyg_bool ret; + + // Check that device is inactive. + if ((dev_info->command & CYG_PCI_CFG_COMMAND_ACTIVE) != 0) + return false; + + // Allocate IO space for the device. + ret = cyg_pci_allocate_io_priv(dev_info, bar, base, &assigned_addr); + + if (ret) { + // Map the device and update the BAR in the dev_info structure. + cyg_pcihw_write_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE+4*bar, + assigned_addr); + cyg_pcihw_read_config_uint32(bus, devfn, + CYG_PCI_CFG_BAR_BASE+4*bar, + &dev_info->base_address[bar]); + } + + return ret; +} + +cyg_bool +cyg_pci_translate_interrupt( cyg_pci_device *dev_info, + CYG_ADDRWORD *vec ) +{ + cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(dev_info->devid); + cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(dev_info->devid); + + return cyg_pcihw_translate_interrupt(bus, devfn, vec); +} + +#endif // ifdef CYG_PCI_PRESENT + +//----------------------------------------------------------------------------- +// end of pci.c
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/src/pci_hw.c @@ -0,0 +1,114 @@ +//============================================================================= +// +// pci_hw.c +// +// PCI hardware library +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov, from design by nickg +// Contributors: jskov +// Date: 1999-08-09 +// Purpose: PCI hardware configuration access +// Description: +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/io/pci_hw.h> + +// CYG_PCI_PRESENT only gets defined for targets that provide PCI HAL support. +// See pci_hw.h for details. +#ifdef CYG_PCI_PRESENT + +// Init +void +cyg_pcihw_init(void) +{ + HAL_PCI_INIT(); +} + +// Read functions +void +cyg_pcihw_read_config_uint8( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint8 *val) +{ + HAL_PCI_CFG_READ_UINT8(bus, devfn, offset, *val); +} + +void +cyg_pcihw_read_config_uint16( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint16 *val) +{ + HAL_PCI_CFG_READ_UINT16(bus, devfn, offset, *val); +} + +void +cyg_pcihw_read_config_uint32( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint32 *val) +{ + HAL_PCI_CFG_READ_UINT32(bus, devfn, offset, *val); +} + +// Write functions +void +cyg_pcihw_write_config_uint8( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint8 val) +{ + HAL_PCI_CFG_WRITE_UINT8(bus, devfn, offset, val); +} + +void +cyg_pcihw_write_config_uint16( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint16 val) +{ + HAL_PCI_CFG_WRITE_UINT16(bus, devfn, offset, val); +} + +void +cyg_pcihw_write_config_uint32( cyg_uint8 bus, cyg_uint8 devfn, + cyg_uint8 offset, cyg_uint32 val) +{ + HAL_PCI_CFG_WRITE_UINT32(bus, devfn, offset, val); +} + +// Interrupt translation +cyg_bool +cyg_pcihw_translate_interrupt( cyg_uint8 bus, cyg_uint8 devfn, + CYG_ADDRWORD *vec) +{ + cyg_bool valid; + + HAL_PCI_TRANSLATE_INTERRUPT(bus, devfn, *vec, valid); + + return valid; +} + +#endif // ifdef CYG_PCI_PRESENT + +//----------------------------------------------------------------------------- +// end of pci_hw.c
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/tests/PKGconf.mak @@ -0,0 +1,41 @@ +#============================================================================== +# +# makefile +# +# io/pci/tests +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := io_pci +include ../../../../pkgconf/pkgconf.mak +include ../../../../pkgconf/system.mak + +TESTS := + +ifdef CYGPKG_KERNEL +TESTS += pci1 pci2 +endif + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.tst
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/tests/pci1.c @@ -0,0 +1,322 @@ +//========================================================================== +// +// pci1.c +// +// Test PCI library API +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 1999-03-17 +// Description: Simple test that: +// Checks API (compile time) +// Prints out information about found PCI devices. +// Allocates resources to devices (but does not enable +// them). +//####DESCRIPTIONEND#### + +#include <pkgconf/system.h> + +#include <cyg/infra/diag.h> // diag_printf +#include <cyg/infra/testcase.h> // test macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +// Package requirements +#if defined(CYGPKG_IO_PCI) && defined(CYGPKG_KERNEL) + +#include <pkgconf/kernel.h> +#include <pkgconf/io_pci.h> +#include <cyg/io/pci.h> +#include <cyg/hal/hal_arch.h> + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) && defined(CYG_PCI_PRESENT) + +#include <cyg/kernel/kapi.h> + +// If the target has limited memory resources, undef the below to +// avoid inclusion of the big PCI code tables. +// +// The header file is created from http://www.yourvote.com/pci +// maintained by Jim Boemler (jboemler@halcyon.com). +// +// If you have PCI devices not listed in this list, please consider +// registering the codes in the database. +#define USE_PCI_CODE_LIST + +#ifdef USE_PCI_CODE_LIST +#include "pcihdr.h" +#endif + +// You may want to use this code to do some simple testing of the +// devices on the PCI bus. By enabling the below definition, the +// devices will get PCI IO and MEM access activated after configuration +// so you can play with IO registers and display/set contents of MEM. +#undef ENABLE_PCI_DEVICES + +unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; +cyg_thread thread_data; +cyg_handle_t thread_handle; + +cyg_bool +pci_api_test(int dummy) +{ + cyg_pci_device dev_info; + cyg_pci_device_id devid = CYG_PCI_NULL_DEVID; + cyg_bool ret; + CYG_PCI_ADDRESS64 mem_base = 0; + CYG_PCI_ADDRESS32 io_base = 0; + CYG_ADDRWORD vec; + cyg_uint8 var_uint8; + cyg_uint16 var_uint16; + cyg_uint32 var_uint32; + + + // Always return... + if (dummy) + return true; + + CYG_TEST_FAIL_FINISH("Not reached"); + + // PCI library API + cyg_pci_init(); + + cyg_pci_get_device_info (devid, &dev_info); + cyg_pci_set_device_info (devid, &dev_info); + + ret = cyg_pci_find_device(0, 0, &devid); + ret |= cyg_pci_find_class(0, &devid); + ret |= cyg_pci_find_next(devid, &devid); + + ret |= cyg_pci_configure_device(&dev_info); + + cyg_pci_set_memory_base(mem_base); + cyg_pci_set_io_base(io_base); + + ret |= cyg_pci_allocate_memory(&dev_info, 0, &mem_base); + ret |= cyg_pci_allocate_io(&dev_info, 0, &io_base); + + ret |= cyg_pci_translate_interrupt(&dev_info, &vec); + + cyg_pci_read_config_uint8(devid, 0, &var_uint8); + cyg_pci_read_config_uint16(devid, 0, &var_uint16); + cyg_pci_read_config_uint32(devid, 0, &var_uint32); + + cyg_pci_write_config_uint8(devid, 0, var_uint8); + cyg_pci_write_config_uint16(devid, 0, var_uint16); + cyg_pci_write_config_uint32(devid, 0, var_uint32); + + return ret; +} + +void +pci_test( void ) +{ + cyg_pci_device dev_info; + cyg_pci_device_id devid; + CYG_ADDRWORD irq; + int i; +#ifdef USE_PCI_CODE_LIST + cyg_bool no_match = false; + cyg_uint16 vendor, device; + cyg_uint8 bc, sc, pi; + PCI_VENTABLE* vtbl; + PCI_DEVTABLE* dtbl; + PCI_CLASSCODETABLE* ctbl; +#endif + + pci_api_test(1); + + cyg_pci_init(); + + if (cyg_pci_find_next(CYG_PCI_NULL_DEVID, &devid)) { + do { + // Get device info + cyg_pci_get_device_info(devid, &dev_info); + + + // Print stuff + diag_printf("Found device on bus %d, devfn 0x%02x:\n", + CYG_PCI_DEV_GET_BUS(devid), + CYG_PCI_DEV_GET_DEVFN(devid)); + + if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) { + diag_printf(" Note that board is active. Probed" + " sizes and CPU addresses invalid!\n"); + } + + // Configure the device + if (cyg_pci_configure_device(&dev_info)) { + diag_printf(" Device configuration succeeded\n"); +#ifdef ENABLE_PCI_DEVICES + { + cyg_uint16 cmd; + + // Don't use cyg_pci_set_device_info since it clears + // some of the fields we want to print out below. + cyg_pci_read_config_uint16(dev_info.devid, + CYG_PCI_CFG_COMMAND, &cmd); + cmd |= CYG_PCI_CFG_COMMAND_IO|CYG_PCI_CFG_COMMAND_MEMORY; + cyg_pci_write_config_uint16(dev_info.devid, + CYG_PCI_CFG_COMMAND, cmd); + } + diag_printf(" **** Device IO and MEM access enabled\n"); +#endif + } else { + diag_printf(" Device configuration failed"); + if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) + diag_printf(" - device already enabled\n"); + else + diag_printf(" - resource problem\n"); + } + + diag_printf(" Vendor 0x%04x", dev_info.vendor); +#ifdef USE_PCI_CODE_LIST + vendor = dev_info.vendor; + vtbl = PciVenTable; + for (i = 0; i < PCI_VENTABLE_LEN; i++, vtbl++) + if (vendor == vtbl->VenId) + break; + + if (i < PCI_VENTABLE_LEN) { + diag_printf(" [%s][%s]", vtbl->VenShort, vtbl->VenFull); + } else { + diag_printf(" [UNKNOWN]"); + no_match = true; + } +#endif + diag_printf("\n Device 0x%04x", dev_info.device); +#ifdef USE_PCI_CODE_LIST + device = dev_info.device; + dtbl = PciDevTable; + for (i = 0; i < PCI_DEVTABLE_LEN; i++, dtbl++) + if (vendor == dtbl->VenId && device == dtbl->DevId) + break; + + if (i < PCI_DEVTABLE_LEN) { + diag_printf(" [%s][%s]", dtbl->Chip, dtbl->ChipDesc); + } else { + diag_printf(" [UNKNOWN]"); + no_match = true; + } +#endif + + diag_printf("\n Command 0x%04x, Status 0x%04x\n", + dev_info.command, dev_info.status); + + diag_printf(" Class/Rev 0x%08x", dev_info.class_rev); +#ifdef USE_PCI_CODE_LIST + bc = (dev_info.class_rev >> 24) & 0xff; + sc = (dev_info.class_rev >> 16) & 0xff; + pi = (dev_info.class_rev >> 8) & 0xff; + ctbl = PciClassCodeTable; + for (i = 0; i < PCI_CLASSCODETABLE_LEN; i++, ctbl++) + if (bc == ctbl->BaseClass + && sc == ctbl->SubClass + && pi == ctbl->ProgIf) + break; + + if (i < PCI_CLASSCODETABLE_LEN) { + diag_printf(" [%s][%s][%s]", ctbl->BaseDesc, + ctbl->SubDesc, ctbl->ProgDesc); + } else { + diag_printf(" [UNKNOWN]"); + no_match = true; + } +#endif + diag_printf("\n Header 0x%02x\n", dev_info.header_type); + + diag_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n", + dev_info.header.normal.sub_vendor, + dev_info.header.normal.sub_id); + + + for(i = 0; i < CYG_PCI_MAX_BAR; i++) { + diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]); + diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n", + dev_info.base_size[i], dev_info.base_map[i]); + } + + if (cyg_pci_translate_interrupt(&dev_info, &irq)) + diag_printf(" Wired to HAL vector %d\n", irq); + else + diag_printf(" Does not generate interrupts.\n"); + + } while (cyg_pci_find_next(devid, &devid)); + + +#ifdef USE_PCI_CODE_LIST + diag_printf("\nStrings in [] are from the PCI Code List at http://www.yourvote.com/pci\n"); + if (no_match) { + diag_printf("It seems that some of the device information has not been registered in\n"); + diag_printf("the PCI Code List. Please consider improving the database by registering\n"); + diag_printf("the [UNKNOWN] information for your devices. Thanks.\n"); + } +#endif + } else { + diag_printf("No PCI devices found."); + } + + CYG_TEST_PASS_FINISH("pci1 test OK"); +} + +void +cyg_start(void) +{ + CYG_TEST_INIT(); + cyg_thread_create(10, // Priority - just a number + (cyg_thread_entry_t*)pci_test, // entry + 0, // + "pci_thread", // Name + &stack[0], // Stack + CYGNUM_HAL_STACK_SIZE_TYPICAL, // Size + &thread_handle, // Handle + &thread_data // Thread data structure + ); + cyg_thread_resume(thread_handle); + cyg_scheduler_start(); +} + +#else // CYGFUN_KERNEL_API_C && CYG_PCI_PRESENT +#define N_A_MSG "Needs kernel C API & PCI platform support" +#endif + +#else // CYGPKG_IO_PCI && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/PCI and Kernel" +#endif + +#ifdef N_A_MSG +void +cyg_start( void ) +{ + CYG_TEST_INIT(); + CYG_TEST_NA( N_A_MSG); +} +#endif // N_A_MSG + +// EOF pci1.c
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/tests/pci2.c @@ -0,0 +1,231 @@ +//========================================================================== +// +// pci2.c +// +// Test PCI library's resource allocation. +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors: jskov +// Date: 1999-03-17 +// Description: Simple test that prints out information about found +// PCI devices. Entirely passive - no configuration happens. +// +//####DESCRIPTIONEND#### + +#include <pkgconf/system.h> + +#include <cyg/infra/diag.h> // diag_printf +#include <cyg/infra/testcase.h> // test macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +// Package requirements +#if defined(CYGPKG_IO_PCI) && defined(CYGPKG_KERNEL) + +#include <pkgconf/kernel.h> +#include <pkgconf/io_pci.h> +#include <cyg/io/pci.h> +#include <cyg/hal/hal_arch.h> + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) && defined(CYG_PCI_PRESENT) + +#include <cyg/kernel/kapi.h> + +unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; +cyg_thread thread_data; +cyg_handle_t thread_handle; + +void +pci_test( void ) +{ + cyg_pci_device dev_info; + CYG_PCI_ADDRESS64 mem_base; + CYG_PCI_ADDRESS64 mem_assigned_addr; + CYG_PCI_ADDRESS32 io_base; + CYG_PCI_ADDRESS32 io_assigned_addr; + + // Verify that space type requests are checked. + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO; + CYG_TEST_CHECK(!cyg_pci_allocate_memory_priv(&dev_info, 0, &mem_base, + &mem_assigned_addr), + "cyg_pci_allocate_memory_priv accepted IO request"); + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_MEM; + CYG_TEST_CHECK(!cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv accepted MEM request"); + + // Check allocation and alignment of IO space + io_base = 0x0000; + // Size 4 + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xfffffffc; + CYG_TEST_CHECK(cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv(4) failed"); + CYG_TEST_CHECK(0x0004 == io_base, + "cyg_pci_allocate_io_priv(4) size failed"); + CYG_TEST_CHECK(0x0000 == io_assigned_addr, + "cyg_pci_allocate_io_priv(4) align failed"); + // Size 8 (alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xfffffff8; + CYG_TEST_CHECK(cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv(8) failed"); + CYG_TEST_CHECK(0x0010 == io_base, + "cyg_pci_allocate_io_priv(8) size failed"); + CYG_TEST_CHECK(0x0008 == io_assigned_addr, + "cyg_pci_allocate_io_priv(8) align failed"); + // Size 16 (no alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xfffffff0; + CYG_TEST_CHECK(cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv(16) failed"); + CYG_TEST_CHECK(0x0020 == io_base, + "cyg_pci_allocate_io_priv(16) size failed"); + CYG_TEST_CHECK(0x0010 == io_assigned_addr, + "cyg_pci_allocate_io_priv(16) align failed"); + // Size 64 (alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xffffffc0; + CYG_TEST_CHECK(cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv(64) failed"); + CYG_TEST_CHECK(0x0080 == io_base, + "cyg_pci_allocate_io_priv(64) size failed"); + CYG_TEST_CHECK(0x0040 == io_assigned_addr, + "cyg_pci_allocate_io_priv(64) align failed"); + // Size 256 (alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xffffff00; + CYG_TEST_CHECK(cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv(256) failed"); + CYG_TEST_CHECK(0x0200 == io_base, + "cyg_pci_allocate_io_priv(256) size failed"); + CYG_TEST_CHECK(0x0100 == io_assigned_addr, + "cyg_pci_allocate_io_priv(256) align failed"); + // Check IO space limit + io_base = 0x100000-0x80; + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xffffff00; + CYG_TEST_CHECK(!cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv overflow"); + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_IO | 0xffffff80; + CYG_TEST_CHECK(cyg_pci_allocate_io_priv(&dev_info, 0, &io_base, + &io_assigned_addr), + "cyg_pci_allocate_io_priv overflow (on limit)"); + + + // Check allocation and alignment of MEM space + mem_base = 0x00000000; + // Size 16 (no alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_MEM | 0xfffffff0; + CYG_TEST_CHECK(cyg_pci_allocate_memory_priv(&dev_info, 0, &mem_base, + &mem_assigned_addr), + "cyg_pci_allocate_memory_priv(16) failed"); + CYG_TEST_CHECK(0x00000010 == mem_base, + "cyg_pci_allocate_memory_priv(16) size failed"); + CYG_TEST_CHECK(0x00000000 == mem_assigned_addr, + "cyg_pci_allocate_memory_priv(16) align failed"); + // Size 64 (alignment required - <1MB) + dev_info.base_size[0] = (CYG_PCI_CFG_BAR_SPACE_MEM + | CYG_PRI_CFG_BAR_MEM_TYPE_1M + | 0xffffffc0); + CYG_TEST_CHECK(cyg_pci_allocate_memory_priv(&dev_info, 0, &mem_base, + &mem_assigned_addr), + "cyg_pci_allocate_memory_priv(64/<1MB) failed"); + CYG_TEST_CHECK(0x00000080 == mem_base, + "cyg_pci_allocate_memory_priv(64/<1MB) size failed"); + CYG_TEST_CHECK(0x00000040 == mem_assigned_addr, + "cyg_pci_allocate_memory_priv(64/<1MB) align failed"); + // Size 1MB (alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_MEM | 0xfff00000; + CYG_TEST_CHECK(cyg_pci_allocate_memory_priv(&dev_info, 0, &mem_base, + &mem_assigned_addr), + "cyg_pci_allocate_memory_priv(1MB) failed"); + CYG_TEST_CHECK(0x00200000 == mem_base, + "cyg_pci_allocate_memory_priv(1MB) size failed"); + CYG_TEST_CHECK(0x00100000 == mem_assigned_addr, + "cyg_pci_allocate_memory_priv(1MB) align failed"); + // Size 16MB (alignment required) + dev_info.base_size[0] = CYG_PCI_CFG_BAR_SPACE_MEM | 0xff000000; + CYG_TEST_CHECK(cyg_pci_allocate_memory_priv(&dev_info, 0, &mem_base, + &mem_assigned_addr), + "cyg_pci_allocate_memory_priv(16MB) failed"); + CYG_TEST_CHECK(0x02000000 == mem_base, + "cyg_pci_allocate_memory_priv(16MB) size failed"); + CYG_TEST_CHECK(0x01000000 == mem_assigned_addr, + "cyg_pci_allocate_memory_priv(16MB) align failed"); + // Size 32 (no alignment required - <1MB - FAILS!) + // Note: When more clever allocation has been made for the bottom + // 1MB of PCI memory space, this test needs to be made more elaborate. + dev_info.base_size[0] = (CYG_PCI_CFG_BAR_SPACE_MEM + | CYG_PRI_CFG_BAR_MEM_TYPE_1M + | 0xffffffe0); + CYG_TEST_CHECK(!cyg_pci_allocate_memory_priv(&dev_info, 0, &mem_base, + &mem_assigned_addr), + "cyg_pci_allocate_memory_priv(32/<1MB) unexpectedly worked!"); + + // TBD: Check 64bit MEM allocation. + + CYG_TEST_PASS_FINISH("pci2 test OK"); +} + +void +cyg_start(void) +{ + CYG_TEST_INIT(); + cyg_thread_create(10, // Priority - just a number + (cyg_thread_entry_t*)pci_test, // entry + 0, // + "pci_thread", // Name + &stack[0], // Stack + CYGNUM_HAL_STACK_SIZE_TYPICAL, // Size + &thread_handle, // Handle + &thread_data // Thread data structure + ); + cyg_thread_resume(thread_handle); + cyg_scheduler_start(); +} + +#else // CYGFUN_KERNEL_API_C && CYG_PCI_PRESENT +#define N_A_MSG "Needs kernel C API & PCI platform support" +#endif + +#else // CYGPKG_IO_PCI && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/PCI and Kernel" +#endif + +#ifdef N_A_MSG +void +cyg_start( void ) +{ + CYG_TEST_INIT(); + CYG_TEST_NA( N_A_MSG); +} +#endif // N_A_MSG + +// EOF pci1.c
new file mode 100644 --- /dev/null +++ b/packages/io/pci/current/tests/pcihdr.h @@ -0,0 +1,1625 @@ + +#if 0 +PCIHDR.H: PCI Vendors, Devices, and Class Type information + + Created automatically from the web using the following URL: + http://www.yourvote.com/pci + Software to create and maintain the PCICODE List written by: + Jim Boemler (jboemler@halcyon.com) + + This header created on Fri, 20 Aug 1999 15:30:47 UTC + +Too many people have contributed to this list to acknowledge them all, but +a few have provided the majority of the input and deserve special mention: + Frederic Potter, who maintains a list for Linux. + Chris Aston at Madge Networks. + Thomas Dippon of Hewlett-Packard GmbH. + Jurgen ("Josh") Thelen + William H. Avery III at Altitech +#endif + +// NOTE that the 0xFFFF of 0xFF entries at the end of some tables below are +// not properly list terminators, but are actually the printable definitions +// of values that are legitimately found on the PCI bus. The size +// definitions should be used for loop control when the table is searched. + +typedef struct _PCI_VENTABLE +{ + unsigned short VenId ; + char * VenShort ; + char * VenFull ; +} PCI_VENTABLE, *PPCI_VENTABLE ; + +PCI_VENTABLE PciVenTable [] = +{ + { 0x003D, "Lockheed Martin", "Lockheed Martin Corp" } , + { 0x0E11, "Compaq", "Compaq" } , + { 0x1000, "SYM", "Symbios Logic Inc." } , + { 0x1002, "ATI", "ATI Technologies" } , + { 0x1003, "ULSI", "ULSI" } , + { 0x1004, "VLSI", "VLSI Technology" } , + { 0x1005, "Avance", "Avance Logic Inc." } , + { 0x1006, "Reply", "Reply Group" } , + { 0x1007, "NetFrame", "Netframe Systems" } , + { 0x1008, "Epson", "Epson" } , + { 0x100A, "Phoenix", "Phoenix Technologies Ltd." } , + { 0x100B, "NSC", "National Semiconductor" } , + { 0x100C, "Tseng", "Tseng Labs" } , + { 0x100D, "AST", "AST Research" } , + { 0x100E, "Weitek", "Weitek" } , + { 0x1010, "VLogic", "Video Logic Ltd." } , + { 0x1011, "DEC", "Digital Equipment Corporation" } , + { 0x1012, "Micronics", "Micronics Computers Inc." } , + { 0x1013, "Cirrus", "Cirrus Logic" } , + { 0x1014, "IBM", "IBM" } , + { 0x1015, "LSIL", "LSI Logic Corp of Canada" } , + { 0x1016, "Fujitsu ICL", "Fujitsu ICL Computers" } , + { 0x1017, "Spea", "Spea Software AG" } , + { 0x1018, "Unisys", "Unisys Systems" } , + { 0x1019, "ECS", "Elitegroup Computer Sys" } , + { 0x101A, "NCR", "NCR/AT&T GIS" } , + { 0x101B, "Vitesse", "Vitesse Semiconductor" } , + { 0x101C, "WD", "Western Digital" } , + { 0x101E, "AMI", "American Megatrends Inc." } , + { 0x101F, "PictureTel", "PictureTel Corp." } , + { 0x1020, "Hitachi", "Hitachi Computer Electronics" } , + { 0x1021, "OKI", "Oki Electric Industry" } , + { 0x1022, "AMD", "Advanced Micro Devices" } , + { 0x1023, "Trident", "Trident Microsystems" } , + { 0x1024, "Zenith", "Zenith Data Systems" } , + { 0x1025, "Acer", "Acer Incorporated" } , + { 0x1028, "Dell", "Dell Computer Corporation" } , + { 0x1029, "Siem-Nix", "Siemens Nixdorf AG" } , + { 0x102A, "LSI", "LSI Logic Headland Div" } , + { 0x102B, "Matrox", "Matrox" } , + { 0x102C, "C&T", "Chips And Technologies" } , + { 0x102D, "Wyse", "Wyse Technologies" } , + { 0x102E, "Olivetti", "Olivetti Advanced Technology" } , + { 0x102F, "Toshiba", "Toshiba America" } , + { 0x1030, "TMC", "TMC Research" } , + { 0x1031, "miro", "miro Computer Products AG" } , + { 0x1032, "Compaq", "Compaq" } , + { 0x1033, "NEC", "NEC Corporation" } , + { 0x1034, "Burndy", "Burndy Corporation" } , + { 0x1035, "C&CRL", "Computer & &Communication Research Lab" } , + { 0x1036, "FDomain", "Future Domain" } , + { 0x1037, "Hitachi", "Hitachi Micro Systems Inc" } , + { 0x1038, "AMP", "AMP Incorporated" } , + { 0x1039, "SIS", "Silicon Integrated System" } , + { 0x103A, "Seiko", "Seiko Epson Corporation" } , + { 0x103B, "Tatung", "Tatung Corp. Of America" } , + { 0x103C, "HP", "Hewlett-Packard Company" } , + { 0x103E, "Solliday", "Solliday Engineering" } , + { 0x103F, "Logic Mod.", "Logic Modeling" } , + { 0x1040, "Kubota", "Kubota Pacific Computer Inc." } , + { 0x1041, "Computrend", "Computrend" } , + { 0x1042, "PC Tech.", "PC Technology" } , + { 0x1043, "Asustek", "Asustek Computer Inc." } , + { 0x1044, "DPT", "Distributed Processing Tech" } , + { 0x1045, "OPTi", "OPTi" } , + { 0x1046, "IPC", "IPC Corporation LTD" } , + { 0x1047, "Genoa", "Genoa Systems Corp." } , + { 0x1048, "ELSA", "ELSA GmbH" } , + { 0x1049, "Fountain", "Fountain Technology" } , + { 0x104A, "STM", "ST Microelectronics" } , + { 0x104B, "Buslogoc", "Buslogic" } , + { 0x104C, "TI", "Texas Instruments" } , + { 0x104D, "Sony", "Sony Corporation" } , + { 0x104E, "Oak", "Oak Technology" } , + { 0x104F, "Co-Time", "Co-Time Computer Ltd." } , + { 0x1050, "Winbond", "Winbond Electronics Corp." } , + { 0x1051, "Anigma", "Anigma Corp." } , + { 0x1052, "Young", "Young Micro Systems" } , + { 0x1054, "Hitachi", "Hitachi LTD" } , + { 0x1055, "EFAR", "EFAR Microsystems" } , + { 0x1056, "ICL", "ICL" } , + { 0x1057, "Motorola", "Motorola" } , + { 0x1058, "E&TR", "Electronics & Teleccommunication Res" } , + { 0x1059, "Teknor", "Teknor Microsystems" } , + { 0x105A, "Promise", "Promise Technology" } , + { 0x105B, "Foxconn", "Foxconn International" } , + { 0x105C, "Wipro", "Wipro Infotech Limited" } , + { 0x105D, "Number-Nine", "Number Nine Visual Technology" } , + { 0x105E, "Vtech", "Vtech Engineering Canada Ltd." } , + { 0x105F, "Infotronic", "Infotronic America Inc." } , + { 0x1060, "UMC", "United Microelectronics" } , + { 0x1061, "8x8", "8x8 Inc." } , + { 0x1062, "Maspar", "Maspar Computer Corp." } , + { 0x1063, "OOA", "Ocean Office Automation" } , + { 0x1064, "Alcatel", "Alcatel Cit" } , + { 0x1065, "TM", "Texas Microsystems" } , + { 0x1066, "Picopower", "Picopower Technology" } , + { 0x1067, "Mitsubishi", "Mitsubishi Electronics" } , + { 0x1068, "Div. Tech.", "Diversified Technology" } , + { 0x1069, "Mylex", "Mylex Corporation" } , + { 0x106A, "Aten", "Aten Research Inc." } , + { 0x106B, "Apple", "Apple Computer Inc." } , + { 0x106C, "Hyundai", "Hyundai Electronics America" } , + { 0x106D, "Sequent", "Sequent" } , + { 0x106E, "DFI", "DFI Inc." } , + { 0x106F, "CityGate", "City Gate Development LTD" } , + { 0x1070, "Daewoo", "Daewoo Telecom Ltd." } , + { 0x1071, "Mitac", "Mitac" } , + { 0x1072, "GIT", "GIT Co. Ltd." } , + { 0x1073, "Yamaha", "Yamaha Corporation" } , + { 0x1074, "Nexgen", "Nexgen Microsysteme" } , + { 0x1075, "AIR", "Advanced Integration Research" } , + { 0x1076, "Chaintech", "Chaintech Computer Co. Ltd." } , + { 0x1077, "Q Logic", "Q Logic" } , + { 0x1078, "Cyrix", "Cyrix Corporation" } , + { 0x1079, "I-Bus", "I-Bus" } , + { 0x107A, "Networth", "Networth" } , + { 0x107B, "Gateway", "Gateway 2000" } , + { 0x107C, "Goldstar", "Goldstar Co. Ltd." } , + { 0x107D, "Leadtek", "Leadtek Research" } , + { 0x107E, "Interphase", "Interphase Corporation" } , + { 0x107F, "DTC", "Data Technology Corporation" } , + { 0x1080, "Contaq", "Contaq Microsystems" } , + { 0x1081, "Supermac", "Supermac Technology Inc." } , + { 0x1082, "EFA", "EFA Corporation Of America" } , + { 0x1083, "Forex", "Forex Computer Corporation" } , + { 0x1084, "Parador", "Parador" } , + { 0x1085, "Tulip", "Tulip Computers Int'l BV" } , + { 0x1086, "J. Bond", "J. Bond Computer Systems" } , + { 0x1087, "Cache", "Cache Computer" } , + { 0x1088, "MS Son", "Microcomputer Systems (M) Son" } , + { 0x1089, "DG", "Data General Corporation" } , + { 0x108A, "Bit3", "Bit3 Computer" } , + { 0x108C, "Elonex", "Elonex PLC c/o Oakleigh Systems Inc." } , + { 0x108D, "Olicom", "Olicom" } , + { 0x108E, "Sun", "Sun Microsystems" } , + { 0x108F, "Systemsoft", "Systemsoft Corporation" } , + { 0x1090, "Encore", "Encore Computer Corporation" } , + { 0x1091, "Intergraph", "Intergraph Corporation" } , + { 0x1092, "Diamond", "Diamond Computer Systems" } , + { 0x1093, "Nat. Inst.", "National Instruments" } , + { 0x1094, "FIC", "First Int'l Computers" } , + { 0x1095, "CMD", "CMD Technology Inc." } , + { 0x1096, "Alacron", "Alacron" } , + { 0x1097, "Appian", "Appian Graphics" } , + { 0x1098, "Quantum", "Quantum Designs Ltd." } , + { 0x1099, "Samsung", "Samsung Electronics Co. Ltd." } , + { 0x109A, "Packard-Bell", "Packard Bell" } , + { 0x109B, "Gemlight", "Gemlight Computer Ltd." } , + { 0x109C, "Megachips", "Megachips Corporation" } , + { 0x109D, "Zida", "Zida Technologies Ltd." } , + { 0x109E, "Brooktree", "Brooktree Corporation" } , + { 0x109F, "Trigem", "Trigem Computer Inc." } , + { 0x10A0, "Meidensha", "Meidensha Corporation" } , + { 0x10A1, "Juko", "Juko Electronics Inc. Ltd." } , + { 0x10A2, "Quantum", "Quantum Corporation" } , + { 0x10A3, "Everex", "Everex Systems Inc." } , + { 0x10A4, "Globe", "Globe Manufacturing Sales" } , + { 0x10A5, "Racal", "Racal Interlan" } , + { 0x10A6, "Informtech", "Informtech Industrial Ltd." } , + { 0x10A7, "Benchmarq", "Benchmarq Microelectronics" } , + { 0x10A8, "Sierra", "Sierra Semiconductor" } , + { 0x10A9, "SG", "Silicon Graphics" } , + { 0x10AA, "ACC", "ACC Microelectronics" } , + { 0x10AB, "Digicom", "Digicom" } , + { 0x10AC, "Honeywell", "Honeywell IASD" } , + { 0x10AD, "Symphony", "Symphony Labs" } , + { 0x10AE, "Cornerstone", "Cornerstone Technology" } , + { 0x10AF, "MCS", "Micro Computer Systems Inc." } , + { 0x10B0, "Cardexpert", "Cardexpert Technology" } , + { 0x10B1, "Cabletron", "Cabletron Systems Inc." } , + { 0x10B2, "Raytheon", "Raytheon Company" } , + { 0x10B3, "Databook", "Databook Inc." } , + { 0x10B4, "STB", "STB Systems" } , + { 0x10B5, "PLX", "PLX Technology" } , + { 0x10B6, "Madge", "Madge Networks" } , + { 0x10B7, "3Com", "3Com Corporation" } , + { 0x10B8, "Standard", "Standard Microsystems" } , + { 0x10B9, "ALI", "Acer Labs Inc." } , + { 0x10BA, "Mitsubishi", "Mitsubishi Electronics Corp." } , + { 0x10BB, "Dapha", "Dapha Electronics Corporation" } , + { 0x10BC, "ALR", "Advanced Logic Research Inc." } , + { 0x10BD, "Surecom", "Surecom Technology" } , + { 0x10BE, "Tseng", "Tsenglabs International Corp." } , + { 0x10BF, "MOST", "MOST Corp." } , + { 0x10C0, "Boca", "Boca Research Inc." } , + { 0x10C1, "ICM", "ICM Corp. Ltd." } , + { 0x10C2, "Auspex", "Auspex Systems Inc." } , + { 0x10C3, "Samsung", "Samsung Semiconductors" } , + { 0x10C4, "Award", "Award Software Int'l Inc." } , + { 0x10C5, "Xerox", "Xerox Corporation" } , + { 0x10C6, "Rambus", "Rambus Inc." } , + { 0x10C7, "Media Vision", "Media Vision" } , + { 0x10C8, "Neomagic", "Neomagic Corporation" } , + { 0x10C9, "Dataexpert", "Dataexpert Corporation" } , + { 0x10CA, "Fujitsu", "Fujitsu" } , + { 0x10CB, "Omron", "Omron Corporation" } , + { 0x10CC, "Mentor", "Mentor Arc Inc." } , + { 0x10CD, "AdvanSys", "Advanced System Products" } , + { 0x10CE, "Radius", "Radius Inc." } , + { 0x10CF, "TTI", "Citicorp TTI" } , + { 0x10D0, "Fujitsu", "Fujitsu Limited" } , + { 0x10D1, "Future+", "Future+ Systems" } , + { 0x10D2, "Molex", "Molex Incorporated" } , + { 0x10D3, "Jabil", "Jabil Circuit Inc." } , + { 0x10D4, "Hualon", "Hualon Microelectronics" } , + { 0x10D5, "Autologic", "Autologic Inc." } , + { 0x10D6, "Cetia", "Cetia" } , + { 0x10D7, "BCM", "BCM Advanced Research" } , + { 0x10D8, "APL", "Advanced Peripherals Labs" } , + { 0x10D9, "Macronix", "Macronix International Co. Ltd." } , + { 0x10DA, "T-C", "Thomas-Conrad Corporation" } , + { 0x10DB, "Rohm", "Rohm Research" } , + { 0x10DC, "CERN", "CERN/EPC/EDU" } , + { 0x10DD, "E&S", "Evans & Sutherland" } , + { 0x10DE, "Nvidia", "Nvidia Corporation" } , + { 0x10DF, "Emulex", "Emulex Corporation" } , + { 0x10E0, "IMS", "Integrated Micro Solutions" } , + { 0x10E1, "Tekram", "Tekram Technology Corp. Ltd." } , + { 0x10E2, "Aptix", "Aptix Corporation" } , + { 0x10E3, "Tundra", "Tundra Semiconductor Corp." } , + { 0x10E4, "Tandem", "Tandem Computers" } , + { 0x10E5, "MIC", "Micro Industries Corporation" } , + { 0x10E6, "Gainbery", "Gainbery Computer Products Inc." } , + { 0x10E7, "Vadem", "Vadem" } , + { 0x10E8, "AMCC", "Applied Micro Circuits Corp." } , + { 0x10E9, "Alps", "Alps Electronic Corp. Ltd." } , + { 0x10EA, "Intergraphics", "Integraphics Systems" } , + { 0x10EB, "Artist", "Artist Graphics" } , + { 0x10EC, "Realtek", "Realtek Semiconductor" } , + { 0x10ED, "Ascii", "Ascii Corporation" } , + { 0x10EE, "Xilinx", "Xilinx Corporation" } , + { 0x10EF, "Racore", "Racore Computer Products" } , + { 0x10F0, "Peritek", "Peritek Corporation" } , + { 0x10F1, "Tyan", "Tyan Computer" } , + { 0x10F2, "Achme", "Achme Computer Inc." } , + { 0x10F3, "Alaris", "Alaris Inc." } , + { 0x10F4, "S-Mos", "S-Mos Systems" } , + { 0x10F5, "NKK", "NKK Corporation" } , + { 0x10F6, "Creative", "Creative Electronic Systems SA" } , + { 0x10F7, "Matsushita", "Matsushita Electric Industrial Corp." } , + { 0x10F8, "Altos", "Altos India Ltd." } , + { 0x10F9, "PC-Direct", "PC Direct" } , + { 0x10FA, "Truevision", "Truevision" } , + { 0x10FB, "Thesys", "Thesys Microelectronic's" } , + { 0x10FC, "I-O", "I-O Data Device Inc." } , + { 0x10FD, "Soyo", "Soyo Technology Corp. Ltd." } , + { 0x10FE, "Fast", "Fast Electronic GmbH" } , + { 0x10FF, "Ncube", "Ncube" } , + { 0x1100, "Jazz", "Jazz Multimedia" } , + { 0x1101, "Initio", "Initio Corporation" } , + { 0x1102, "Creative Labs", "Creative Labs" } , + { 0x1103, "Triones", "Triones Technologies Inc." } , + { 0x1104, "Rasterops", "Rasterops" } , + { 0x1105, "Sigma", "Sigma Designs Inc." } , + { 0x1106, "VIA", "VIA Technologies" } , + { 0x1107, "Stratus", "Stratus Computer" } , + { 0x1108, "Proteon", "Proteon Inc." } , + { 0x1109, "Cogent", "Cogent Data Technologies" } , + { 0x110A, "Siemens", "Siemens AG / Siemens Nixdorf AG" } , + { 0x110B, "Chromatic", "Chromatic Research Inc" } , + { 0x110C, "Mini-Max", "Mini-Max Technology Inc." } , + { 0x110D, "ZNYX", "ZNYX Corporation" } , + { 0x110E, "CPU Tech.", "CPU Technology" } , + { 0x110F, "Ross", "Ross Technology" } , + { 0x1110, "Powerhouse", "Powerhouse Systems" } , + { 0x1111, "SCO", "Santa Cruz Operation" } , + { 0x1112, "Osicom", "Osicom Technologies Inc." } , + { 0x1113, "Accton", "Accton Technology Corporation" } , + { 0x1114, "Atmel", "Atmel Corp." } , + { 0x1115, "Dupont", "Dupont Pixel Systems Ltd." } , + { 0x1116, "Data Trans.", "Data Translation" } , + { 0x1117, "Datacube", "Datacube Inc." } , + { 0x1118, "Berg", "Berg Electronics" } , + { 0x1119, "Vortex", "Vortex Computersysteme GmbH" } , + { 0x111A, "Eff. Net.", "Efficent Networks" } , + { 0x111B, "Teledyne", "Teledyne Electronic Systems" } , + { 0x111C, "Tricord", "Tricord Systems Inc." } , + { 0x111D, "IDT", "Integrated Device Technology Inc." } , + { 0x111E, "Eldec", "Eldec Corp." } , + { 0x111F, "PDI", "Precision Digital Images" } , + { 0x1120, "EMC", "EMC Corp." } , + { 0x1121, "Zilog", "Zilog" } , + { 0x1122, "Multi-Tech", "Multi-Tech Systems Inc." } , + { 0x1123, "EDI", "Excellent Design Inc." } , + { 0x1124, "Leutron", "Leutron Vision AG" } , + { 0x1125, "Eurocore", "Eurocore/Vigra" } , + { 0x1126, "Vigra", "Vigra" } , + { 0x1127, "FORE", "FORE Systems" } , + { 0x1129, "Firmworks", "Firmworks" } , + { 0x112A, "Hermes", "Hermes Electronics Co. Ltd." } , + { 0x112B, "Linotype", "Linotype - Hell AG" } , + { 0x112C, "Zenith", "Zenith Data Systems" } , + { 0x112D, "Ravicad", "Ravicad" } , + { 0x112E, "Infomedia", "Infomedia" } , + { 0x112F, "ImagTech", "Imaging Technology" } , + { 0x1130, "Computervision", "Computervision" } , + { 0x1131, "Philips", "Philips Semiconductors" } , + { 0x1132, "Mitel", "Mitel Corp." } , + { 0x1133, "EIC", "Eicon Technology Corporation" } , + { 0x1134, "MCS", "Mercury Computer Systems Inc." } , + { 0x1135, "Fuji", "Fuji Xerox Co Ltd" } , + { 0x1136, "Momentum", "Momentum Data Systems" } , + { 0x1137, "Cisco", "Cisco Systems Inc" } , + { 0x1138, "Ziatech", "Ziatech Corporation" } , + { 0x1139, "Dyn. Pict.", "Dynamic Pictures Inc" } , + { 0x113A, "FWB", "FWB Inc" } , + { 0x113B, "NCD", "Network Computing Devices" } , + { 0x113C, "Cyclone", "Cyclone Microsystems" } , + { 0x113D, "Leading Edge", "Leading Edge Products Inc" } , + { 0x113E, "Sanyo", "Sanyo Electric Co" } , + { 0x113F, "Equinox", "Equinox Systems" } , + { 0x1140, "Intervoice", "Intervoice Inc" } , + { 0x1141, "Crest", "Crest Microsystem Inc" } , + { 0x1142, "Alliance", "Alliance Semiconductor" } , + { 0x1143, "Netpower", "Netpower Inc" } , + { 0x1144, "Cinn. Mil.", "Cincinnati Milacron" } , + { 0x1145, "Workbit", "Workbit Corp" } , + { 0x1146, "Force", "Force Computers" } , + { 0x1147, "Interface", "Interface Corp" } , + { 0x1148, "S&K", "Schneider & Koch" } , + { 0x1149, "Win System", "Win System Corporation" } , + { 0x114A, "VMIC", "VMIC" } , + { 0x114B, "Canopus", "Canopus Co. Ltd" } , + { 0x114C, "Annabooks", "Annabooks" } , + { 0x114D, "IC Corp.", "IC Corporation" } , + { 0x114E, "Nikon", "Nikon Systems Inc" } , + { 0x114F, "Stargate", "Stargate" } , + { 0x1150, "TMC", "Thinking Machines Corporation" } , + { 0x1151, "JAE", "JAE Electronics Inc." } , + { 0x1152, "Megatek", "Megatek" } , + { 0x1153, "Land Win", "Land Win Electronic Corp" } , + { 0x1154, "Melco", "Melco Inc" } , + { 0x1155, "Pine", "Pine Technology Ltd" } , + { 0x1156, "Periscope", "Periscope Engineering" } , + { 0x1157, "Avsys", "Avsys Corporation" } , + { 0x1158, "Voarx", "Voarx R&D Inc" } , + { 0x1159, "Mutech", "Mutech" } , + { 0x115A, "Harlequin", "Harlequin Ltd" } , + { 0x115B, "Parallax", "Parallax Graphics" } , + { 0x115C, "Photron", "Photron Ltd." } , + { 0x115D, "Xircom", "Xircom" } , + { 0x115E, "Peer", "Peer Protocols Inc" } , + { 0x115F, "Maxtor", "Maxtor Corporation" } , + { 0x1160, "Megasoft", "Megasoft Inc" } , + { 0x1161, "PFU", "PFU Ltd" } , + { 0x1162, "OA Lab", "OA Laboratory Co Ltd" } , + { 0x1163, "Rendition", "Rendition Inc" } , + { 0x1164, "APT", "Advanced Peripherals Tech" } , + { 0x1165, "Imagraph", "Imagraph Corporation" } , + { 0x1166, "Pequr", "Pequr Technology Inc." } , + { 0x1167, "Mutoh", "Mutoh Industries Inc" } , + { 0x1168, "Thine", "Thine Electronics Inc" } , + { 0x1169, "CDAC", "Centre f/Dev. of Adv. Computing" } , + { 0x116A, "Polaris", "Polaris Communications" } , + { 0x116B, "Connectware", "Connectware Inc" } , + { 0x116C, "Int Res.", "Intelligent Resources" } , + { 0x116E, "EFI", "Electronics for Imaging" } , + { 0x116F, "WkSta. Tech.", "Workstation Technology" } , + { 0x1170, "Inventec", "Inventec Corporation" } , + { 0x1171, "Lough. Sound", "Loughborough Sound Images" } , + { 0x1172, "Altera", "Altera Corporation" } , + { 0x1173, "Adobe", "Adobe Systems" } , + { 0x1174, "Bridgeport", "Bridgeport Machines" } , + { 0x1175, "Mitron", "Mitron Computer Inc." } , + { 0x1176, "SBE", "SBE" } , + { 0x1177, "Silicon Eng.", "Silicon Engineering" } , + { 0x1178, "Alfa", "Alfa Inc" } , + { 0x1179, "Toshiba", "Toshiba America Info Systems" } , + { 0x117A, "A-Trend", "A-Trend Technology" } , + { 0x117B, "LG Elec.", "LG Electronics Inc." } , + { 0x117C, "Atto", "Atto Technology" } , + { 0x117D, "B&D", "Becton & Dickinson" } , + { 0x117E, "T/R", "T/R Systems" } , + { 0x117F, "ICS", "Integrated Circuit Systems" } , + { 0x1180, "Ricoh", "Ricoh Co Ltd" } , + { 0x1181, "Telmatics", "Telmatics International" } , + { 0x1183, "Fujikura", "Fujikura Ltd" } , + { 0x1184, "Forks", "Forks Inc" } , + { 0x1185, "Dataworld", "Dataworld" } , + { 0x1186, "D-Link", "D-Link System Inc" } , + { 0x1187, "ATL", "Advanced Technology Laboratories" } , + { 0x1188, "Shima", "Shima Seiki Manufacturing Ltd." } , + { 0x1189, "Matsushita", "Matsushita Electronics" } , + { 0x118A, "Hilevel", "Hilevel Technology" } , + { 0x118B, "Hypertec", "Hypertec Pty Ltd" } , + { 0x118C, "Corollary", "Corollary Inc" } , + { 0x118D, "BitFlow", "BitFlow Inc" } , + { 0x118E, "Hermstedt", "Hermstedt GmbH" } , + { 0x118F, "Green", "Green Logic" } , + { 0x1191, "Artop", "Artop Electric" } , + { 0x1192, "Densan", "Densan Co. Ltd" } , + { 0x1193, "Zeitnet", "Zeitnet Inc." } , + { 0x1194, "Toucan", "Toucan Technology" } , + { 0x1195, "Ratoc", "Ratoc System Inc" } , + { 0x1196, "Hytec", "Hytec Electronics Ltd" } , + { 0x1197, "Gage", "Gage Applied Sciences Inc." } , + { 0x1198, "Lambda", "Lambda Systems Inc" } , + { 0x1199, "Attachmate", "Attachmate Corp." } , + { 0x119A, "Mind Share", "Mind Share Inc." } , + { 0x119B, "Omega", "Omega Micro Inc." } , + { 0x119C, "ITI", "Information Technology Inst." } , + { 0x119D, "Bug", "Bug Sapporo Japan" } , + { 0x119E, "Fujitsu", "Fujitsu" } , + { 0x119F, "Bull", "Bull Hn Information Systems" } , + { 0x11A0, "Convex", "Convex Computer Corporation" } , + { 0x11A1, "Hamamatsu", "Hamamatsu Photonics K.K." } , + { 0x11A2, "Sierra", "Sierra Research and Technology" } , + { 0x11A3, "Deuretzbacher", "Deuretzbacher GmbH & Co. Eng. KG" } , + { 0x11A4, "Barco", "Barco" } , + { 0x11A5, "MicroUnity", "MicroUnity Systems Engineering Inc." } , + { 0x11A6, "Pure Data", "Pure Data" } , + { 0x11A7, "Power Comp.", "Power Computing Corp." } , + { 0x11A8, "Systech", "Systech Corp." } , + { 0x11A9, "InnoSys", "InnoSys Inc." } , + { 0x11AA, "Actel", "Actel" } , + { 0x11AB, "Galileo", "Galileo Technology Ltd." } , + { 0x11AC, "Canon", "Canon Information Systems" } , + { 0x11AD, "Lite-On", "Lite-On Communications Inc" } , + { 0x11AE, "Scitex", "Scitex Corporation Ltd" } , + { 0x11AF, "Pro-Log", "Pro-Log Corporation" } , + { 0x11B0, "V3", "V3 Semiconductor Inc." } , + { 0x11B1, "Apricot", "Apricot Computers" } , + { 0x11B2, "Kodak", "Eastman Kodak" } , + { 0x11B3, "Barr", "Barr Systems Inc." } , + { 0x11B4, "Leitch", "Leitch Technology International" } , + { 0x11B5, "Radstone", "Radstone Technology Plc" } , + { 0x11B6, "United Video", "United Video Corp" } , + { 0x11B7, "Motorola", "Motorola" } , + { 0x11B8, "Xpoint", "Xpoint Technologies Inc" } , + { 0x11B9, "Pathlight", "Pathlight Technology Inc." } , + { 0x11BA, "Videotron", "Videotron Corp" } , + { 0x11BB, "Pyramid", "Pyramid Technology" } , + { 0x11BC, "Net. Periph.", "Network Peripherals Inc" } , + { 0x11BD, "Pinnacle", "Pinnacle Systems Inc." } , + { 0x11BE, "IMI", "International Microcircuits Inc" } , + { 0x11BF, "Astrodesign", "Astrodesign Inc." } , + { 0x11C0, "H-P", "Hewlett-Packard" } , + { 0x11C1, "AT&T", "AT&T Microelectronics" } , + { 0x11C2, "Sand", "Sand Microelectronics" } , + { 0x11C3, "NEC", "NEC Corporation" } , + { 0x11C4, "Doc. Tech.", "Document Technologies Ind." } , + { 0x11C5, "Shiva", "Shiva Corporatin" } , + { 0x11C6, "Dainippon", "Dainippon Screen Mfg. Co" } , + { 0x11C7, "D.C.M.", "D.C.M. Data Systems" } , + { 0x11C8, "Dolphin", "Dolphin Interconnect Solutions" } , + { 0x11C9, "MAGMA", "MAGMA" } , + { 0x11CA, "LSI Sys.", "LSI Systems Inc" } , + { 0x11CB, "Specialix", "Specialix International Ltd." } , + { 0x11CC, "M&K", "Michels & Kleberhoff Computer GmbH" } , + { 0x11CD, "HAL", "HAL Computer Systems Inc." } , + { 0x11CE, "PRI", "Primary Rate Inc" } , + { 0x11CF, "PEC", "Pioneer Electronic Corporation" } , + { 0x11D0, "Loral", "Loral Frederal Systems - Manassas" } , + { 0x11D1, "AuraVision", "AuraVision Corporation" } , + { 0x11D2, "Intercom", "Intercom Inc." } , + { 0x11D3, "Trancell", "Trancell Systems Inc" } , + { 0x11D4, "AD", "Analog Devices" } , + { 0x11D5, "Ikon", "Ikon Corp" } , + { 0x11D6, "Tekelec", "Tekelec Technologies" } , + { 0x11D7, "Trenton", "Trenton Terminals Inc" } , + { 0x11D8, "ITD", "Image Technologies Development" } , + { 0x11D9, "Tec", "Tec Corporation" } , + { 0x11DA, "Novell", "Novell" } , + { 0x11DB, "Sega", "Sega Enterprises Ltd" } , + { 0x11DC, "Questra", "Questra Corp" } , + { 0x11DD, "Crosfield", "Crosfield Electronics Ltd" } , + { 0x11DE, "Zoran", "Zoran Corporation" } , + { 0x11DF, "New Wave", "New Wave Pdg" } , + { 0x11E0, "Cray", "Cray Communications A/S" } , + { 0x11E1, "Gec Plessey", "Gec Plessey Semi Inc" } , + { 0x11E2, "Samsung", "Samsung Information Systems America" } , + { 0x11E3, "Quicklogic", "Quicklogic Corp" } , + { 0x11E4, "Second Wave", "Second Wave Inc" } , + { 0x11E5, "IIX", "IIX Consulting" } , + { 0x11E6, "Mitsui", "Mitsui-Zosen System Research" } , + { 0x11E7, "Toshiba", "Toshiba America Elec. Co" } , + { 0x11E8, "DPSI", "Digital Processing Systems Inc" } , + { 0x11E9, "Highwater", "Highwater Designs Ltd" } , + { 0x11EA, "Elsag", "Elsag Bailey" } , + { 0x11EB, "Formation", "Formation Inc" } , + { 0x11EC, "Coreco", "Coreco Inc" } , + { 0x11ED, "Mediamatics", "Mediamatics" } , + { 0x11EE, "Dome", "Dome Imaging Systems Inc" } , + { 0x11EF, "Nicolet", "Nicolet Technologies BV" } , + { 0x11F0, "Compu-Shack", "Compu-Shack GmbH" } , + { 0x11F1, "Symbios", "Symbios Logic Inc" } , + { 0x11F2, "Pic-Tel", "Picture Tel Japan KK" } , + { 0x11F3, "Keithley", "Keithley Metrabyte" } , + { 0x11F4, "Kinetic", "Kinetic Systems Corporation" } , + { 0x11F5, "Comp Dev", "Computing Devices Intl" } , + { 0x11F6, "Powermatic", "Powermatic Data Systems Ltd" } , + { 0x11F7, "S-A", "Scientific Atlanta" } , + { 0x11F8, "PMC-Sierra", "PMC-Sierra Inc." } , + { 0x11F9, "I-Cube", "I-Cube Inc" } , + { 0x11FA, "Kasan", "Kasan Electronics Co Ltd" } , + { 0x11FB, "Datel", "Datel Inc" } , + { 0x11FC, "Silicon Magic", "Silicon Magic" } , + { 0x11FD, "High Street", "High Street Consultants" } , + { 0x11FE, "Comtrol", "Comtrol Corp" } , + { 0x11FF, "Scion", "Scion Corp" } , + { 0x1200, "CSS", "CSS Corp" } , + { 0x1201, "Vista", "Vista Controls Corp" } , + { 0x1202, "Network Gen", "Network General Corp" } , + { 0x1203, "Agfa", "Bayer Corporation Agfa Div" } , + { 0x1204, "Lattice", "Lattice Semiconductor Corp" } , + { 0x1205, "Array", "Array Corp" } , + { 0x1206, "Amdahl", "Amdahl Corp" } , + { 0x1208, "Parsytec", "Parsytec GmbH" } , + { 0x1209, "Sci Sys", "Sci Systems Inc" } , + { 0x120A, "Synaptel", "Synaptel" } , + { 0x120B, "Adaptive", "Adaptive Solutions" } , + { 0x120D, "Comp Labs", "Compression Labs Inc." } , + { 0x120E, "Cyclades", "Cyclades Corporation" } , + { 0x120F, "Essential", "Essential Communications" } , + { 0x1210, "Hyperparallel", "Hyperparallel Technologies" } , + { 0x1211, "Braintech", "Braintech Inc" } , + { 0x1212, "Kingston", "Kingston Technology Corp" } , + { 0x1213, "AISI", "Applied Intelligent Systems Inc" } , + { 0x1214, "Perf Tech", "Performance Technologies Inc" } , + { 0x1215, "Interware", "Interware Co Ltd" } , + { 0x1216, "Purup", "Purup Prepress A/S" } , + { 0x1217, "O2Micro", "O2Micro Inc" } , + { 0x1218, "Hybricon", "Hybricon Corp" } , + { 0x1219, "First Virtual", "First Virtual Corp" } , + { 0x121A, "3dfx", "3dfx Interactive Inc" } , + { 0x121B, "ATM", "Advanced Telecommunications Modules" } , + { 0x121C, "Nippon Texa", "Nippon Texa Co Ltd" } , + { 0x121D, "Lippert", "Lippert Automationstechnik GmbH" } , + { 0x121E, "CSPI", "CSPI" } , + { 0x121F, "Arcus", "Arcus Technology Inc" } , + { 0x1220, "Ariel", "Ariel Corporation" } , + { 0x1221, "Contec", "Contec Co Ltd" } , + { 0x1222, "Ancor", "Ancor Communications Inc" } , + { 0x1223, "Heurikon", "Heurikon/Computer Products" } , + { 0x1224, "Int. Img.", "Interactive Images" } , + { 0x1225, "Power IO", "Power I/O Inc." } , + { 0x1227, "Tech-Source", "Tech-Source" } , + { 0x1228, "Norsk", "Norsk Elektro Optikk A/S" } , + { 0x1229, "Data Kin", "Data Kinesis Inc." } , + { 0x122A, "Int. Telecom", "Integrated Telecom" } , + { 0x122B, "LG Ind.", "LG Industrial Systems Co. Ltd." } , + { 0x122C, "Sican", "Sican GmbH" } , + { 0x122D, "Aztech", "Aztech System Ltd" } , + { 0x122E, "Xyratex", "Xyratex" } , + { 0x122F, "Andrew", "Andrew Corp." } , + { 0x1230, "Fishcamp", "Fishcamp Engineering" } , + { 0x1231, "W McCoach", "Woodward McCoach Inc." } , + { 0x1232, "GPT", "GPT Ltd." } , + { 0x1233, "Bus-Tech", "Bus-Tech Inc." } , + { 0x1234, "Technical", "Technical Corp" } , + { 0x1235, "Risq Mod", "Risq Modular Systems Inc." } , + { 0x1236, "Sigma", "Sigma Designs Corp." } , + { 0x1237, "Alta Tech", "Alta Technology Corp." } , + { 0x1238, "Adtran", "Adtran" } , + { 0x1239, "3DO", "The 3DO Company" } , + { 0x123A, "Visicom", "Visicom Laboratories Inc." } , + { 0x123B, "Seeq", "Seeq Technology Inc." } , + { 0x123C, "Century Sys", "Century Systems Inc." } , + { 0x123D, "EDT", "Engineering Design Team Inc." } , + { 0x123F, "C-Cube", "C-Cube Microsystems" } , + { 0x1240, "Marathon", "Marathon Technologies Corp." } , + { 0x1241, "DSC", "DSC Communications" } , + { 0x1243, "Delphax", "Delphax" } , + { 0x1244, "AVM", "AVM" } , + { 0x1245, "APD", "APD S.A." } , + { 0x1246, "Dipix", "Dipix Technologies Inc" } , + { 0x1247, "Xylon", "Xylon Research Inc." } , + { 0x1248, "Central Data", "Central Data Corp." } , + { 0x1249, "Samsung", "Samsung Electronics Co. Ltd." } , + { 0x124A, "AEG", "AEG Electrocom GmbH" } , + { 0x124B, "GreenSpring", "GreenSpring Computers" } , + { 0x124C, "Solitron", "Solitron Technologies Inc." } , + { 0x124D, "Stallion", "Stallion Technologies" } , + { 0x124E, "Cylink", "Cylink" } , + { 0x124F, "Infortrend", "Infortrend Technology Inc" } , + { 0x1250, "Hitachi", "Hitachi Microcomputer System Ltd." } , + { 0x1251, "VLSI Sol.", "VLSI Solution OY" } , + { 0x1253, "Guzik", "Guzik Technical Enterprises" } , + { 0x1254, "Linear Systems", "Linear Systems Ltd." } , + { 0x1255, "Optibase", "Optibase Ltd." } , + { 0x1256, "Perceptive", "Perceptive Solutions Inc." } , + { 0x1257, "Vertex", "Vertex Networks Inc." } , + { 0x1258, "Gilbarco", "Gilbarco Inc." } , + { 0x1259, "Allied Tsyn", "Allied Telesyn International" } , + { 0x125A, "ABB Pwr", "ABB Power Systems" } , + { 0x125B, "Asix", "Asix Electronics Corp." } , + { 0x125C, "Aurora", "Aurora Technologies Inc." } , + { 0x125D, "ESS", "ESS Technology" } , + { 0x125E, "Specvideo", "Specialvideo Engineering SRL" } , + { 0x125F, "Concurrent", "Concurrent Technologies Inc." } , + { 0x1260, "Harris", "Harris Semiconductor" } , + { 0x1261, "Matsushita", "Matsushita-Kotobuki Electronics Indu" } , + { 0x1262, "ES Comp.", "ES Computer Co. Ltd." } , + { 0x1263, "Sonic Sol.", "Sonic Solutions" } , + { 0x1264, "Aval Nag.", "Aval Nagasaki Corp." } , + { 0x1265, "Casio", "Casio Computer Co. Ltd." } , + { 0x1266, "Microdyne", "Microdyne Corp." } , + { 0x1267, "SA Telecom", "S.A. Telecommunications" } , + { 0x1268, "Tektronix", "Tektronix" } , + { 0x1269, "Thomson-CSF", "Thomson-CSF/TTM" } , + { 0x126A, "Lexmark", "Lexmark International Inc." } , + { 0x126B, "Adax", "Adax Inc." } , + { 0x126C, "NorTel", "Northern Telecom" } , + { 0x126D, "Splash", "Splash Technology Inc." } , + { 0x126E, "Sumitomo", "Sumitomo Metal Industries Ltd." } , + { 0x126F, "Sil Motion", "Silicon Motion" } , + { 0x1270, "Olympus", "Olympus Optical Co. Ltd." } , + { 0x1271, "GW Instr.", "GW Instruments" } , + { 0x1272, "Telematics", "Telematics International" } , + { 0x1273, "Hughes", "Hughes Network Systems" } , + { 0x1274, "Ensoniq", "Ensoniq" } , + { 0x1275, "NetApp", "Network Appliance" } , + { 0x1276, "Sw Net Tech", "Switched Network Technologies Inc." } , + { 0x1277, "Comstream", "Comstream" } , + { 0x1278, "Transtech", "Transtech Parallel Systems" } , + { 0x1279, "Transmeta", "Transmeta Corp." } , + { 0x127A, "Rockwell Semi", "Rockwell Semiconductor Systems" } , + { 0x127B, "Pixera", "Pixera Corp" } , + { 0x127C, "Crosspoint", "Crosspoint Solutions Inc." } , + { 0x127D, "Vela Res", "Vela Research" } , + { 0x127E, "Winnow", "Winnov L.P." } , + { 0x127F, "Fujifilm", "Fujifilm" } , + { 0x1280, "Photoscript", "Photoscript Group Ltd." } , + { 0x1281, "Yokogawa", "Yokogawa Electronic Corp." } , + { 0x1282, "Davicom", "Davicom Semiconductor Inc." } , + { 0x1283, "ITExpress", "Integrated Technology Express Inc." } , + { 0x1284, "Sahara", "Sahara Networks Inc." } , + { 0x1285, "Plat Tech", "Platform Technologies Inc." } , + { 0x1286, "Mazet", "Mazet GmbH" } , + { 0x1287, "LuxSonor", "LuxSonor Inc." } , + { 0x1288, "Timestep", "Timestep Corp." } , + { 0x1289, "AVC Tech", "AVC Technology Inc." } , + { 0x128A, "Asante", "Asante Technologies Inc." } , + { 0x128B, "Transwitch", "Transwitch Corp." } , + { 0x128C, "Retix", "Retix Corp." } , + { 0x128D, "G2 Net", "G2 Networks Inc." } , + { 0x128E, "Samho", "Samho Multi Tech Ltd." } , + { 0x128F, "Tateno", "Tateno Dennou Inc." } , + { 0x1290, "Sord", "Sord Computer Corp." } , + { 0x1291, "NCS Comp", "NCS Computer Italia" } , + { 0x1292, "Tritech", "Tritech Microelectronics Intl PTE" } , + { 0x1293, "M Reality", "Media Reality Technology" } , + { 0x1294, "Rhetorex", "Rhetorex Inc." } , + { 0x1295, "Imagenation", "Imagenation Corp." } , + { 0x1296, "Kofax", "Kofax Image Products" } , + { 0x1297, "Holco", "Holco Enterprise" } , + { 0x1298, "Spellcaster", "Spellcaster Telecommunications Inc." } , + { 0x1299, "Know Tech", "Knowledge Technology Laboratories" } , + { 0x129A, "VMETRO", "VMETRO" } , + { 0x129B, "Img Access", "Image Access" } , + { 0x129D, "CompCore", "CompCore Multimedia Inc." } , + { 0x129E, "Victor Jpn", "Victor Co. of Japan Ltd." } , + { 0x129F, "OEC Med", "OEC Medical Systems Inc." } , + { 0x12A0, "A-B", "Allen Bradley Co." } , + { 0x12A1, "Simpact", "Simpact Inc" } , + { 0x12A2, "NewGen", "NewGen Systems Corp." } , + { 0x12A3, "Lucent", "Lucent Technologies" } , + { 0x12A4, "NTT Elect", "NTT Electronics Technology Co." } , + { 0x12A5, "Vision Dyn", "Vision Dynamics Ltd." } , + { 0x12A6, "Scalable", "Scalable Networks Inc." } , + { 0x12A7, "AMO", "AMO GmbH" } , + { 0x12A8, "News Datacom", "News Datacom" } , + { 0x12A9, "Xiotech", "Xiotech Corp." } , + { 0x12AA, "SDL", "SDL Communications Inc." } , + { 0x12AB, "Yuan Yuan", "Yuan Yuan Enterprise Co. Ltd." } , + { 0x12AC, "MeasureX", "MeasureX Corp." } , + { 0x12AD, "Multidata", "Multidata GmbH" } , + { 0x12AE, "Alteon", "Alteon Networks Inc." } , + { 0x12AF, "TDK USA", "TDK USA Corp." } , + { 0x12B0, "Jorge Sci", "Jorge Scientific Corp." } , + { 0x12B1, "GammaLink", "GammaLink" } , + { 0x12B2, "Gen Signal", "General Signal Networks" } , + { 0x12B3, "Inter-Face", "Inter-Face Co. Ltd." } , + { 0x12B4, "Future Tel", "Future Tel Inc." } , + { 0x12B5, "Granite", "Granite Systems Inc." } , + { 0x12B6, "Nat Micro", "Natural Microsystems" } , + { 0x12B7, "Acumen", "Acumen" } , + { 0x12B8, "Korg", "Korg" } , + { 0x12B9, "US Robotics", "US Robotics" } , + { 0x12BA, "Bittware", "Bittware Research Systems Inc" } , + { 0x12BB, "Nippon Uni", "Nippon Unisoft Corp." } , + { 0x12BC, "Array Micro", "Array Microsystems" } , + { 0x12BD, "Computerm", "Computerm Corp." } , + { 0x12BE, "Anchor Chips", "Anchor Chips Inc." } , + { 0x12BF, "Fujifilm", "Fujifilm Microdevices" } , + { 0x12C0, "Infimed", "Infimed" } , + { 0x12C1, "GMM Res", "GMM Research Corp." } , + { 0x12C2, "Mentec", "Mentec Ltd." } , + { 0x12C3, "Holtek", "Holtek Microelectronics Inc." } , + { 0x12C4, "Conn Tech", "Connect Tech Inc." } , + { 0x12C5, "PicturEl", "Picture Elements Inc." } , + { 0x12C6, "Mitani", "Mitani Corp." } , + { 0x12C7, "Dialogic", "Dialogic Corp." } , + { 0x12C8, "G Force", "G Force Co. Ltd." } , + { 0x12C9, "Gigi Ops", "Gigi Operations" } , + { 0x12CA, "I C Engines", "Integrated Computing Engines" } , + { 0x12CB, "Antex", "Antex Electronics Corp." } , + { 0x12CC, "Pluto", "Pluto Technologies International" } , + { 0x12CD, "Aims Lab", "Aims Lab" } , + { 0x12CE, "Netspeed", "Netspeed Inc." } , + { 0x12CF, "Prophet", "Prophet Systems Inc." } , + { 0x12D0, "GDE Sys", "GDE Systems Inc." } , + { 0x12D1, "PsiTech", "PsiTech" } , + { 0x12D2, "NVidia", "NVidia / SGS Thomson" } , + { 0x12D3, "Vingmed", "Vingmed Sound A/S" } , + { 0x12D4, "DGM&S", "DGM & S" } , + { 0x12D5, "Equator", "Equator Technologies" } , + { 0x12D6, "Analogic", "Analogic Corp." } , + { 0x12D7, "Biotronic", "Biotronic SRL" } , + { 0x12D8, "Pericom", "Pericom Semiconductor" } , + { 0x12D9, "Aculab", "Aculab Plc." } , + { 0x12DA, "True Time", "True Time" } , + { 0x12DB, "Annapolis", "Annapolis Micro Systems Inc." } , + { 0x12DC, "Symicron", "Symicron Computer Communication Ltd." } , + { 0x12DD, "MGI", "Management Graphics Inc." } , + { 0x12DE, "Rainbow", "Rainbow Technologies" } , + { 0x12DF, "SBS Tech", "SBS Technologies Inc." } , + { 0x12E0, "Chase", "Chase Research PLC" } , + { 0x12E1, "Nintendo", "Nintendo Co. Ltd." } , + { 0x12E2, "Datum", "Datum Inc. Bancomm-Timing Division" } , + { 0x12E3, "Imation", "Imation Corp. - Medical Imaging Syst" } , + { 0x12E4, "Brooktrout", "Brooktrout Technology Inc." } , + { 0x12E6, "Cirel", "Cirel Systems" } , + { 0x12E7, "Sebring", "Sebring Systems Inc" } , + { 0x12E8, "CRISC", "CRISC Corp." } , + { 0x12E9, "GE Spacenet", "GE Spacenet" } , + { 0x12EA, "Zuken", "Zuken" } , + { 0x12EB, "Aureal", "Aureal Semiconductor" } , + { 0x12EC, "3A Intl", "3A International Inc." } , + { 0x12ED, "Optivision", "Optivision Inc." } , + { 0x12EE, "Orange Micro", "Orange Micro" } , + { 0x12EF, "Vienna", "Vienna Systems" } , + { 0x12F0, "Pentek", "Pentek" } , + { 0x12F1, "Sorenson", "Sorenson Vision Inc." } , + { 0x12F2, "Gammagraphx", "Gammagraphx Inc." } , + { 0x12F4, "Megatel", "Megatel" } , + { 0x12F5, "Forks", "Forks" } , + { 0x12F6, "Dawson Fr", "Dawson France" } , + { 0x12F7, "Cognex", "Cognex" } , + { 0x12F8, "Electronic-Design", "Electronic-Design GmbH" } , + { 0x12F9, "FFT", "FourFold Technologies" } , + { 0x12FE, "ESD", "ESD Electronic System Design GmbH" } , + { 0x1331, "RadiSys", "RadiSys Corporation" } , + { 0x1335, "Videomail", "Videomail Inc." } , + { 0x1347, "Odetics", "Odetics" } , + { 0x135D, "ABB Network Partn", "ABB Network Partner AB" } , + { 0x137E, "PTSC", "Patriot Scientific Corp." } , + { 0x1C1C, "Symphony", "Symphony" } , + { 0x1DE1, "Tekram", "Tekram" } , + { 0x270F, "ChainTech", "ChainTech Computer Co. Ltd." } , + { 0x3000, "Hansol", "Hansol Electronics Inc." } , + { 0x3D3D, "3DLabs", "3DLabs" } , + { 0x4005, "Avance", "Avance Logic Inc." } , + { 0x4143, "DEC", "Digital Equipment Corp." } , + { 0x4680, "UMAX Comp", "UMAX Computer Corp." } , + { 0x4B10, "Buslogic", "Buslogic Inc" } , + { 0x5333, "S3", "S3 Incorporated" } , + { 0x5455, "TU-Berlin", "Technische Universtiaet Berlin" } , + { 0x5700, "Netpower", "Netpower" } , + { 0x6374, "C4T", "c't Magazin f_r Computertechnik" } , + { 0x8008, "Quancom", "Quancom Electronic GmbH" } , + { 0x8086, "Intel", "Intel Corporation" } , + { 0x8800, "Trigem", "Trigem Computer" } , + { 0x8888, "Sil Magic", "Silicon Magic" } , + { 0x8E0E, "Computone", "Computone Corporation" } , + { 0x9004, "Adaptec", "Adaptec" } , + { 0x9005, "Adaptec", "Adaptec" } , + { 0x907F, "Atronics", "Atronics" } , + { 0xC0FE, "Mot Engrg", "Motion Engineering Inc." } , + { 0xD4D4, "DY4", "DY4 Systems Inc." } , + { 0xE159, "Tiger Jet", "Tiger Jet Network Inc" } , + { 0xEDD8, "ARC", "ARC Logic" } , + { 0xFFFF, "BAD!", "ILLEGITIMATE VENDOR ID" } , +} ; + + +// Use this value for loop control during searching: +#define PCI_VENTABLE_LEN (sizeof(PciVenTable)/sizeof(PCI_VENTABLE)) + +typedef struct _PCI_DEVTABLE +{ + unsigned short VenId ; + unsigned short DevId ; + char * Chip ; + char * ChipDesc ; +} PCI_DEVTABLE, *PPCI_DEVTABLE ; + +PCI_DEVTABLE PciDevTable [] = +{ + { 0x0E11, 0x0002, "ISA Bridge", "" } , + { 0x0E11, 0x1000, "", "Triflex/PCI CPU Bridge" } , + { 0x0E11, 0x2000, "", "Triflex/PCI CPU Bridge" } , + { 0x0E11, 0x3032, "QVision", "GUI Accelerator v0" } , + { 0x0E11, 0x3033, "QVision", "GUI Accelerator v1" } , + { 0x0E11, 0x3034, "QVision", "GUI Accelerator v2" } , + { 0x0E11, 0x4000, "4000", "Triflex/PCI CPU Bridge" } , + { 0x0E11, 0xAE32, "", "Netelligent 10/100 TX" } , + { 0x0E11, 0xAE34, "", "Netelligent 10 T" } , + { 0x0E11, 0xAE35, "", "Integrated NetFlex 3/P" } , + { 0x0E11, 0xAE40, "", "Dual Port Netelligent 10/100 TX" } , + { 0x0E11, 0xAE43, "", "ProLiant Integrated Netelligent 10/100 TX" } , + { 0x0E11, 0xB011, "", "Dual Port Netelligent 10/100 TX" } , + { 0x0E11, 0xF130, "", "NetFlex 3/P" } , + { 0x0E11, 0xF150, "", "NetFlex 3/P w/ BNC" } , + { 0x1000, 0x0001, "53C810", "Fast/Narrow SCSI I/O Cntrlr" } , + { 0x1000, 0x0002, "53C820", "Fast-wide SCSI" } , + { 0x1000, 0x0003, "53C825", "Fast-wide SCSI" } , + { 0x1000, 0x0004, "53C815", "Fast SCSI" } , + { 0x1000, 0x0005, "", "" } , + { 0x1000, 0x0006, "53C860", "Ultra SCSI/Narrow" } , + { 0x1000, 0x000B, "", "" } , + { 0x1000, 0x000C, "", "" } , + { 0x1000, 0x000D, "", "" } , + { 0x1000, 0x000F, "53C875", "Ultra-Wide SCSI" } , + { 0x1000, 0x0012, "", "" } , + { 0x1000, 0x008F, "", "" } , + { 0x1002, 0x4158, "68800", "Mach 32" } , + { 0x1002, 0x4354, "215CT222", "" } , + { 0x1002, 0x4358, "210888CX", "" } , + { 0x1002, 0x4758, "210888GX", "Mach 64 (WinTurbo)" } , + { 0x1002, 0x5246, "", "" } , + { 0x1002, 0x5654, "215VT222", "VIDEO XPRESSION" } , + { 0x1003, 0x0201, "US201", "Graphics Cntrlr" } , + { 0x1004, 0x0005, "82C591", "CPU Bridge" } , + { 0x1004, 0x0006, "82C593", "ISA Bridge" } , + { 0x1004, 0x0007, "82C594", "Wildcat System Controller" } , + { 0x1004, 0x0008, "82C596/597", "Wildcat ISA Bridge" } , + { 0x1004, 0x000C, "82C541", "" } , + { 0x1004, 0x000D, "82C543", "" } , + { 0x1004, 0x0101, "82C532", "" } , + { 0x1004, 0x0102, "82C534", "" } , + { 0x1004, 0x0104, "82C535", "" } , + { 0x1004, 0x0105, "82C147", "" } , + { 0x1004, 0x0200, "82C975", "RISC GUI Accelerator" } , + { 0x1004, 0x0280, "82C925", "RISC GUI Accelerator" } , + { 0x1005, 0x2301, "AVL2301", "GUI Accelerator" } , + { 0x1005, 0x2302, "AVG2302", "GUI Accelerator" } , + { 0x100B, 0x0001, "DP83810", "10/100 Ethernet MAC" } , + { 0x100B, 0xD001, "87410", "EIDE Ctrlr" } , + { 0x100C, 0x3202, "ET4000W32P-A", "GUI Accelerator" } , + { 0x100C, 0x3205, "ET4000W32P-B", "GUI Accelerator" } , + { 0x100C, 0x3206, "ET4000W32P-C", "GUI Accelerator" } , + { 0x100C, 0x3207, "ET4000W32P-D", "GUI Accelerator" } , + { 0x100C, 0x3208, "ET6000", "Graphics/Multimedia Engine" } , + { 0x100E, 0x9001, "P9000", "GUI Accelerator" } , + { 0x100E, 0x9100, "P9100", "GUI Accelerator" } , + { 0x1011, 0x0001, "DC21050", "PCI-PCI Bridge" } , + { 0x1011, 0x0002, "DC21040", "Ethernet Ctrlr" } , + { 0x1011, 0x0009, "DC21140", "Fast Ethernet Ctrlr" } , + { 0x1011, 0x000F, "DEFPA", "FDDI" } , + { 0x1011, 0x0014, "DC21041", "Ethernet Ctrlr" } , + { 0x1011, 0x0016, "DGLPB", "ATM" } , + { 0x1011, 0x0019, "DC21143", "PCI/CardBus 10/100 Mbit Ethernet Ctlr" } , + { 0x1011, 0x0021, "21052", "PCI-PCI Bridge" } , + { 0x1011, 0x0022, "21150", "PCI-PCI Bridge" } , + { 0x1011, 0x0024, "21152", "PCI-PCI Bridge" } , + { 0x1011, 0x0025, "21153", "PCI-PCI Bridge" } , + { 0x1011, 0x0026, "21154", "PCI-PCI Bridge" } , + { 0x1013, 0x0038, "CL-GD7548", "Video Controller" } , + { 0x1013, 0x00A0, "GD 5340", "GUI Accelerator" } , + { 0x1013, 0x00A4, "GD 5434", "GUI Accelerator" } , + { 0x1013, 0x00A8, "GD 5434-HC-B", "GUI Accelerator" } , + { 0x1013, 0x00AC, "", "" } , + { 0x1013, 0x00B8, "GD5446", "Visual Media Accelerator (64bit)" } , + { 0x1013, 0x1100, "CL 6729", "PCMCIA Bridge" } , + { 0x1013, 0x1110, "6832", "PCMCIA/CardBus Controller" } , + { 0x1013, 0x1200, "7542", "GUI Accelerator" } , + { 0x1013, 0x1202, "7543", "GUI Accelerator" } , + { 0x1013, 0x1204, "7541", "Nordic-lite VGA Cntrlr" } , + { 0x1014, 0x0002, "MCA Bridge", "MCA Bridge" } , + { 0x1014, 0x0005, "Alta Lite", "CPU Bridge" } , + { 0x1014, 0x0007, "Alta MP", "CPU Bridge" } , + { 0x1014, 0x000A, "ISA Bridge w/PnP", "ISA Bridge w/PnP" } , + { 0x1014, 0x0017, "CPU Bridge", "CPU Bridge" } , + { 0x1014, 0x0018, "Auto LANStreamer", "" } , + { 0x1014, 0x001B, "GXT-150P", "Graphics Adapter" } , + { 0x1014, 0x0020, "", "MCA Bridge" } , + { 0x1014, 0x0022, "PCI-PCI BRIDGE", "PCI-PCI BRIDGE" } , + { 0x1014, 0x002E, "RAID SCSI", "RAID SCSI device" } , + { 0x1014, 0x0036, "Miami/PCI", "32-bit LocalBus Bridge" } , + { 0x1014, 0x0053, "", "25 MBit ATM controller" } , + { 0x101C, 0x0193, "WD33C193A", "8-bit SCSI Cntrlr" } , + { 0x101C, 0x0196, "SCSI Bridge", "SCSI Bridge" } , + { 0x101C, 0x0197, "WD33C197A", "16-bit SCSI Cntrlr" } , + { 0x101C, 0x0296, "WD33C296A", "high perf 16-bit SCSI Cntrlr" } , + { 0x101C, 0x3193, "WD7193", "Fast SCSI-II" } , + { 0x101C, 0x3197, "WD7197", "Fast-wide SCSI-II" } , + { 0x101C, 0x3296, "WD33C296A", "Fast Wide SCSI bridge" } , + { 0x101C, 0x4296, "WD34C296", "Wide Fast-20 Bridge" } , + { 0x101C, 0xC24A, "90C", "" } , + { 0x101E, 0x9010, "MegaRAID", "Fast-wide SCSI/RAID" } , + { 0x101E, 0x9030, "", "IDE Cntrlr" } , + { 0x101E, 0x9031, "", "IDE Cntrlr" } , + { 0x101E, 0x9032, "", "IDE and SCSI Cntrlr" } , + { 0x101E, 0x9033, "", "SCSI Cntrlr" } , + { 0x101E, 0x9040, "", "Multimedia card" } , + { 0x1022, 0x2000, "79C970", "Ethernet Ctrlr" } , + { 0x1022, 0x2020, "53C974", "SCSI Ctrlr" } , + { 0x1022, 0x2040, "79C974", "Ethernet & SCSI Ctrlr" } , + { 0x1023, 0x9320, "", "32-bit GUI Accelerator" } , + { 0x1023, 0x9350, "", "32-bit GUI Accelerator" } , + { 0x1023, 0x9360, "", "Flat panel Cntrlr" } , + { 0x1023, 0x9420, "9420", "VGA Ctrlr" } , + { 0x1023, 0x9440, "9440", "" } , + { 0x1023, 0x9460, "", "32-bit GUI Accelerator" } , + { 0x1023, 0x9660, "9660", "" } , + { 0x1023, 0x9682, "", "Multimedia Accelerator" } , + { 0x1025, 0x1435, "M1435", "VL Bridge" } , + { 0x1025, 0x1445, "M1445", "VL Bridge & EIDE" } , + { 0x1025, 0x1449, "M1449", "ISA Bridge" } , + { 0x1025, 0x1451, "M1451", "Pentium Chipset" } , + { 0x1025, 0x1461, "M1461", "P54C Chipset" } , + { 0x1025, 0x3141, "M3141", "GUI Accelerator" } , + { 0x1025, 0x3143, "M3143", "GUI Accelerator" } , + { 0x1025, 0x3145, "M3145", "GUI Accelerator" } , + { 0x1025, 0x3147, "M3147", "GUI Accelerator" } , + { 0x1025, 0x3149, "M3149", "GUI Accelerator" } , + { 0x1025, 0x3151, "M3151", "GUI Accelerator" } , + { 0x1025, 0x5215, "?", "EIDE Ctrlr" } , + { 0x102A, 0x0000, "HYDRA", "P5 Chipset" } , + { 0x102A, 0x0010, "ASPEN", "i486 Chipset" } , + { 0x102B, 0x0518, "Atlas PX2085", "GUI Accelerator" } , + { 0x102B, 0x0519, "2064W", "Millenium GUI Accelerator" } , + { 0x102B, 0x051A, "MGA 1064SG", "64-bit graphics chip" } , + { 0x102B, 0x051F, "", "" } , + { 0x102B, 0x0521, "", "" } , + { 0x102B, 0x0D10, "Impression", "GUI Accelerator" } , + { 0x102C, 0x00B8, "64310", "GUI Accelerator" } , + { 0x102C, 0x00D0, "65545", "Flat panel/crt VGA Cntrlr" } , + { 0x102C, 0x00D8, "65545", "GUI Accelerator" } , + { 0x102C, 0x00DC, "65548", "GUI Accelerator" } , + { 0x102C, 0x00E0, "65550", "LCD/CRT controller" } , + { 0x102C, 0x00E4, "65554", "Display" } , + { 0x102C, 0x00E5, "65555", "VGA GUI Accelerator" } , + { 0x102F, 0x0009, "", "r4x00 Bridge" } , + { 0x1031, 0x5607, "", "video in and out with motion jpeg compression and deco" } , + { 0x1033, 0x0001, "", "PCI to 486 like bus Bridge" } , + { 0x1033, 0x0002, "", "PCI to vl98 Bridge" } , + { 0x1033, 0x0003, "", "atm lan Cntrlr" } , + { 0x1033, 0x0004, "", "r4000PCI bus Bridge" } , + { 0x1033, 0x0005, "", "PCI to 486 like peripheral bus Bridge" } , + { 0x1033, 0x0006, "", "GUI Accelerator" } , + { 0x1033, 0x0007, "", "PCI to ux-bus Bridge" } , + { 0x1033, 0x0008, "", "GUI Accelerator (vga equivalent)" } , + { 0x1033, 0x0009, "", "graphic Cntrlr for 98" } , + { 0x1036, 0x0000, "TMC-18C30", "" } , + { 0x1039, 0x0001, "86C201", "True-Color GUI Accelerator" } , + { 0x1039, 0x0002, "", "VGA Cntrlr" } , + { 0x1039, 0x0006, "85C501/2", "Pentium Bridge" } , + { 0x1039, 0x0008, "85C503/5513", "ISA Bridge" } , + { 0x1039, 0x0406, "85C501/2", "Pentium Bridge" } , + { 0x1039, 0x0496, "85C496", "VL Bridge" } , + { 0x1039, 0x0596, "", "p5 chipset w/DE" } , + { 0x1039, 0x0601, "601", "EIDE Ctrlr" } , + { 0x1039, 0x3602, "", "IDE Cntrlr" } , + { 0x1039, 0x5401, "", "486 chipset" } , + { 0x1039, 0x5511, "SiS5511/5512", "Pentium Chipset" } , + { 0x1039, 0x5513, "SiS5513", "EIDE Ctrlr" } , + { 0x1039, 0x5581, "", "p5 chipset" } , + { 0x1039, 0x5582, "", "ISA Bridge" } , + { 0x1039, 0x5596, "", "p5 chipset" } , + { 0x1039, 0x5597, "", "" } , + { 0x1039, 0x6204, "", "video decoder/mpeg interface" } , + { 0x1039, 0x6205, "", "PCI vga Cntrlr" } , + { 0x103C, 0x1030, "J2585A", "10/100VG LAN Adapter" } , + { 0x103C, 0x2910, "E2910A", "PCI Bus Exerciser" } , + { 0x103C, 0x2925, "E2925A", "PCI Bus Exerciser" } , + { 0x1042, 0x1000, "FDC 37C665", "EIDE" } , + { 0x1042, 0x1000, "RZ1000", "IDE Ctrlr" } , + { 0x1042, 0x1001, "37C922", "" } , + { 0x1044, 0xA400, "2124A/9X", "SmartCache/Raid SCSI" } , + { 0x1045, 0xC178, "92C178", "LCD GUI Accelerator" } , + { 0x1045, 0xC557, "82C557", "CPU Bridge (Viper)" } , + { 0x1045, 0xC558, "82C558", "ISA Bridge w/PnP" } , + { 0x1045, 0xC621, "82C621", "VESA Bridge" } , + { 0x1045, 0xC822, "82C822", "EIDE Ctrlr" } , + { 0x104B, 0x0140, "BT-946C", "SCSI-II" } , + { 0x104B, 0x1040, "BA80C30", "SCSI" } , + { 0x104B, 0x8130, "Flashpoint LT", "Ultra SCSI" } , + { 0x104C, 0x0500, "", "100 MBit LAN Cntrlr" } , + { 0x104C, 0x0508, "", "tms380c2x compressor interface" } , + { 0x104C, 0x1000, "TI PCI Eagle i/f AS", "" } , + { 0x104C, 0xA001, "TDC1570", "64-bit PCI ATM sar" } , + { 0x104C, 0xA100, "TDC1561", "32-bit PCI ATM sar" } , + { 0x104C, 0xAC10, "PCI1050", "pc card Cntrlr" } , + { 0x104C, 0xAC11, "PCI1053", "pc card Cntrlr" } , + { 0x104C, 0xAC12, "PCI1130", "pc card Cardbus Cntrlr" } , + { 0x104C, 0xac17, "", "" } , + { 0x104E, 0x0107, "OTI107", "Spitfire VGA Accelerator" } , + { 0x1050, 0x0000, "", "Ethernet Cntrlr" } , + { 0x1054, 0x0001, "", "PCI Bridge" } , + { 0x1054, 0x0002, "", "PCI bus Cntrlr" } , + { 0x1055, 0x0810, "", "486 host Bridge" } , + { 0x1055, 0x0922, "", "Pentium/p54c host Bridge" } , + { 0x1055, 0x0926, "", "ISA Bridge" } , + { 0x1057, 0x0001, "MPC105", "PowerPC Chipset" } , + { 0x1057, 0x0002, "MPC106", "PowerPC Chipset" } , + { 0x105A, 0x5300, "DC5300", "" } , + { 0x105D, 0x2309, "Imagine 128", "GUI Accelerator" } , + { 0x105D, 0x2339, "I128s2", "Imagine 128 Series 2" } , + { 0x105D, 0x493D, "T2R", "Imagine 128 3D" } , + { 0x1060, 0x0001, "UM82C881", "486 Chipset" } , + { 0x1060, 0x0002, "UM82C886", "ISA Bridge" } , + { 0x1060, 0x0101, "UM8673F", "EIDE Controller" } , + { 0x1060, 0x0881, "UM8881", "" } , + { 0x1060, 0x0881, "UM8881", "HB4 486 PCI Chipset" } , + { 0x1060, 0x0886, "UM8886F", "ISA Bridge" } , + { 0x1060, 0x0891, "UM82C891", "Pentium Chipset" } , + { 0x1060, 0x1001, "UM886A", "IDE Cntrlr (dual function)" } , + { 0x1060, 0x673A, "UM8886", "Funktion 1: EIDE Controller" } , + { 0x1060, 0x8710, "UM8710", "VGA Cntrlr" } , + { 0x1060, 0x886A, "UM8886", "ISA Bridge with EIDE" } , + { 0x1060, 0x8881, "UM8881F", "HB4 486 PCI Chipset" } , + { 0x1060, 0x8886, "UM8886", "ISA Bridge" } , + { 0x1060, 0x8891, "UM8891", "586 Chipset" } , + { 0x1060, 0x9017, "UM9017F", "" } , + { 0x1060, 0xE881, "UM8881", "486 Chipset" } , + { 0x1060, 0xE886, "UM8886", "ISA Bridge w/EIDE" } , + { 0x1060, 0xE891, "UM8891", "Pentium Chipset" } , + { 0x1061, 0x0001, "AGX016", "GUI Accelerator" } , + { 0x1061, 0x0002, "IIT3204/3501", "MPEG Decoder" } , + { 0x1066, 0x0000, "PT80C826", "VL Bridge" } , + { 0x1069, 0x0001, "DAC960P", "Wide SCSI w/RAID" } , + { 0x1073, 0x0001, "", "3D graphics Cntrlr" } , + { 0x1073, 0x0002, "YGV615", "RPA3 3D-Graphics Controller" } , + { 0x1077, 0x1020, "ISP1020A", "Fast-wide SCSI" } , + { 0x1077, 0x1022, "ISP1022A", "Fast-wide SCSI" } , + { 0x107D, 0x0000, "P86C850", "Graphic GLU-Logic" } , + { 0x107E, 0x0001, "", "ATM interface card" } , + { 0x107E, 0x0002, "", "100 vg anylan Cntrlr" } , + { 0x107E, 0x0008, "", "155 MBit ATM controller" } , + { 0x107F, 0x0802, "SL82C105", "EIDE Ctrlr" } , + { 0x1080, 0x0600, "82C599", "VL Bridge" } , + { 0x1083, 0x0001, "FR710", "EIDE Ctrlr" } , + { 0x1083, 0x0613, "", "Host Bridge" } , + { 0x108A, 0x0001, "Model 617", "PCI-VME Bus Adapter" } , + { 0x108D, 0x0001, "", "Ethernet Ctrlr" } , + { 0x1091, 0x0020, "", "3D Graphics Processor" } , + { 0x1091, 0x0021, "", "3D graphics processor w/texturing" } , + { 0x1091, 0x0040, "", "3D graphics frame buffer" } , + { 0x1091, 0x0041, "", "3D graphics frame buffer" } , + { 0x1091, 0x0060, "", "Proprietary bus Bridge" } , + { 0x1091, 0x0720, "", "Motion JPEG Codec" } , + { 0x1093, 0xC801, "PCI-GPIB", "GPIB Controller Interface Board" } , + { 0x1095, 0x0640, "PCI0640A", "EIDE Ctrlr" } , + { 0x1095, 0x0642, "", "IDE Cntrlr w/RAID 1" } , + { 0x1095, 0x0643, "", "" } , + { 0x1095, 0x0646, "PCI0646", "EIDE Ctrlr" } , + { 0x1095, 0x0650, "PBC0650A", "Fast SCSI-II Ctrlr" } , + { 0x1097, 0x0038, "", "EIDE Ctrlr" } , + { 0x1098, 0x0001, "QD-8500", "" } , + { 0x1098, 0x0002, "QD-8580", "" } , + { 0x109E, 0x0350, "BT848", "TV/PCI with DMA Push" } , + { 0x109E, 0x2115, "BtV 2115", "BtV Mediastream Controller" } , + { 0x109E, 0x2125, "BtV 2125", "BtV Mediastream Controller" } , + { 0x109E, 0x8230, "?", "?" } , + { 0x10A8, 0x0000, "?", "64-bit GUI Accelerator" } , + { 0x10AA, 0x0000, "2188", "ACCM 2188 VL-PCI Bridge (Pentium)" } , + { 0x10AD, 0x0001, "W83769F", "EIDE Ctrlr" } , + { 0x10AD, 0x0103, "sl82c103", "PCI-ide mode 4.5 Cntrlr" } , + { 0x10AD, 0x0105, "sl82c105", "- bus master PCI-ide mode 4.5 Cntrlr" } , + { 0x10B5, 0x9036, "PCI9036", "Interface chip" } , + { 0x10B5, 0x9050, "PCI 9050", "Target PCI Interface Chip" } , + { 0x10B5, 0x9060, "PCI9060xx", "Interface chip" } , + { 0x10B5, 0x9080, "PCI 9080", "High performance PCI to Local Bus chip" } , + { 0x10B6, 0x0001, "Smart 16/4", "Ringnode" } , + { 0x10B6, 0x0004, "", "Smart 16/4 Ringnode" } , + { 0x10B6, 0x1000, "Collage 25", "ATM adapter" } , + { 0x10B6, 0x1001, "Collage 155", "ATM adapter" } , + { 0x10B7, 0x5900, "3C590", "Ethernet 10bT" } , + { 0x10B7, 0x5950, "3C595", "Ethernet 100bTX" } , + { 0x10B7, 0x5951, "3C595", "Ethernet 100bT4" } , + { 0x10B7, 0x5952, "3C595", "Ethernet 100b-MII" } , + { 0x10B7, 0x8811, "", "Token Ring" } , + { 0x10B7, 0x9000, "3C900-TPO", "Fast Etherlink XL PCI 10" } , + { 0x10B7, 0x9001, "3C900-COMBO", "Fast Etherlink XL PCI 10" } , + { 0x10B7, 0x9050, "3C905-TX", "Fast Etherlink XL PCI 10/100" } , + { 0x10B7, 0x9051, "3C905-T4", "Fast Etherlink XL 10/100" } , + { 0x10B7, 0x9055, "3C905B", "Fast Etherlink XL 10/100" } , + { 0x10B8, 0x1000, "37C665", "FDC" } , + { 0x10B8, 0x1001, "37C922", "FDC" } , + { 0x10B8, 0xA011, "83C170QF", "Fast ethernet controller" } , + { 0x10B9, 0x1435, "M1435", "VL Bridge" } , + { 0x10B9, 0x1445, "M1445", "VL Bridge w/EIDE" } , + { 0x10B9, 0x1449, "M1449", "ISA Bridge" } , + { 0x10B9, 0x1451, "M1451", "Pentium Chipset" } , + { 0x10B9, 0x1461, "M1461", "P54C Chipset" } , + { 0x10B9, 0x3141, "M3141", "GUI Accelerator" } , + { 0x10B9, 0x3143, "M3143", "GUI Accelerator" } , + { 0x10B9, 0x3145, "M3145", "GUI Accelerator" } , + { 0x10B9, 0x3147, "M3147", "GUI Accelerator" } , + { 0x10B9, 0x3149, "M3149", "GUI Accelerator" } , + { 0x10B9, 0x3151, "M3151", "GUI Accelerator" } , + { 0x10B9, 0x5215, "MS4803", "EIDE Ctrlr" } , + { 0x10B9, 0x5217, "m5217h", "I/O (?)" } , + { 0x10B9, 0x5219, "m5219", "I/O (?)" } , + { 0x10B9, 0x5235, "m5225", "I/O (?)" } , + { 0x10BD, 0x5240, "", "IDE Cntrlr" } , + { 0x10BD, 0x5241, "", "PCMCIA Bridge" } , + { 0x10BD, 0x5242, "", "General Purpose Cntrlr" } , + { 0x10BD, 0x5243, "", "Bus Cntrlr" } , + { 0x10BD, 0x5244, "", "FCD Cntrlr" } , + { 0x10C8, 0x0000, "", "Graphics Cntrlr" } , + { 0x10CD, 0x1100, "", "SCSI I/O Cntrlr" } , + { 0x10CD, 0x1200, "ASC1200", "Fast SCSI-II" } , + { 0x10CD, 0x1300, "ASC-3050", "ASC-3150" } , + { 0x10CF, 0x2001, "mb86605", "Wide SCSI-2" } , + { 0x10DC, 0x0002, "ATT 2C15-3 (FPGA)", "SCI bridge on PCI 5 Volt card" } , + { 0x10DC, 0x10DC, "ATT 2C15-3 (FPGA)", "" } , + { 0x10DD, 0x0001, "", "3D graphics processor" } , + { 0x10DF, 0x1AE5, "", "Fibre Channel Host Adapter" } , + { 0x10E0, 0x5026, "IMS5026/27/28", "VL Bridge" } , + { 0x10E0, 0x5028, "", "ISA Bridge" } , + { 0x10E0, 0x8849, "8849", "VL Bridge" } , + { 0x10E0, 0x8853, "", "ATM network card" } , + { 0x10E0, 0x9128, "IMS9129", "GUI Accelerator" } , + { 0x10E3, 0x0000, "CA91C042", "VMEbus Bridge" } , + { 0x10E3, 0x0860, "CA91C860", "Motorola Processor Bridge" } , + { 0x10E8, 0x4750, "S5933", "PCI Ctrlr" } , + { 0x10E8, 0x8043, "LANai4.x", "Myrinet LANai interface chip" } , + { 0x10E8, 0x8088, "FS", "Kongsberg Spacetec Format Synchronizer" } , + { 0x10E8, 0x8089, "SOB", "Kongsberg Spacetec Serial Output Board" } , + { 0x10E8, 0x811A, "PCI-DSlink", "PCI-IEEE1355-DS-DE interface" } , + { 0x10EB, 0x0101, "3GA", "64 bit graphics processor" } , + { 0x10EC, 0x8029, "", "NE2000 compatible Ethernet" } , + { 0x10ec, 8139, "", "" } , + { 0x10ED, 0x7310, "V7310", "VGA Video Overlay Adapter" } , + { 0x10F5, 0xA001, "NDR4000", "NR4600 Bridge" } , + { 0x10FA, 0x0000, "", "GUI Accelerator" } , + { 0x10FA, 0x0001, "", "GUI Accelerator" } , + { 0x10FA, 0x0002, "", "GUI Accelerator" } , + { 0x10FA, 0x0003, "", "GUI Accelerator" } , + { 0x10FA, 0x0004, "", "GUI Accelerator" } , + { 0x10FA, 0x0005, "", "GUI Accelerator" } , + { 0x10FA, 0x0006, "", "GUI Accelerator" } , + { 0x10FA, 0x0007, "", "GUI Accelerator" } , + { 0x10FA, 0x0008, "", "GUI Accelerator" } , + { 0x10FA, 0x0009, "", "GUI Accelerator" } , + { 0x10FA, 0x0010, "", "GUI Accelerator" } , + { 0x10FA, 0x0011, "", "GUI Accelerator" } , + { 0x10FA, 0x0012, "", "GUI Accelerator" } , + { 0x10FA, 0x0013, "", "GUI Accelerator" } , + { 0x10FA, 0x0014, "", "GUI Accelerator" } , + { 0x10FA, 0x0015, "", "GUI Accelerator" } , + { 0x1101, 0x9100, "", "8-bit Fast-wide SCSI" } , + { 0x1101, 0x9400, "", "Fast Wide SCSI" } , + { 0x1101, 0x9700, "", "Fast Wide SCSI" } , + { 0x1102, 0x02, "", "" } , + { 0x1105, 0x8300, "", "" } , + { 0x1106, 0x0505, "82C505", "VL Bridge" } , + { 0x1106, 0x0561, "82C561", "IDE" } , + { 0x1106, 0x0571, "", "" } , + { 0x1106, 0x0576, "82C576", "P54 Ctrlr" } , + { 0x1106, 0x0585, "VT82C585VP", "Host Bus-PCI Bridge" } , + { 0x1106, 0x0586, "VT82C586VP", "PCI-ISA Bridge w/ IDE & USB" } , + { 0x1106, 0x0597, "", "" } , + { 0x1106, 0x0926, "VT86C926", "Ethernet Ctrlr (NE2000 compatible)" } , + { 0x1106, 0x1000, "82C570MV", "P54 Ctrlr" } , + { 0x1106, 0x1106, "82C570MV", "ISA Bridge w/IDE" } , + { 0x1106, 0x3038, "", "" } , + { 0x1106, 0x3040, "", "" } , + { 0x1106, 0x8597, "", "" } , + { 0x1108, 0x0100, "p1690plus-AA", "Token Ring Adapter" } , + { 0x1108, 0x0101, "p1690plus-AB", "2-Port Token Ring Adapter" } , + { 0x1109, 0x1400, "EM110TX", "EX110TX PCI Fast Ethernet Adapter" } , + { 0x110A, 0x4942, "FPGA-IBTR", "I-Bus Tracer for MBD" } , + { 0x110A, 0x6120, "SZB6120", "Multimedia Adapter" } , + { 0x1112, 0x2200, "", "FDDI adapter" } , + { 0x1112, 0x2300, "", "fast ethernet adapter" } , + { 0x1112, 0X2340, "4 Port FEN Adapter", "4 10/100 UTP Fast Ethernet Adapter" } , + { 0x1112, 0x2400, "", "ATM adapter" } , + { 0x1117, 0x9500, "", "max-lc SVGA card" } , + { 0x1117, 0x9501, "", "max-lc image processing" } , + { 0x1119, 0x0000, "GDT6000/6020/6050", "SCSI RAID" } , + { 0x1119, 0x0001, "GDT6000/6010", "SCSI RAID" } , + { 0x1119, 0x0002, "GDT6110/6510", "SCSI RAID" } , + { 0x1119, 0x0003, "GDT6120/6520", "2-chan SCSI RAID" } , + { 0x1119, 0x0004, "GDT6530", "3-chan SCSI RAID" } , + { 0x1119, 0x0005, "GDT6550", "5-chan SCSI RAID" } , + { 0x111A, 0x0000, "155P-MF1", "" } , + { 0x111C, 0x0001, "", "Powerbus Bridge" } , + { 0x111F, 0x5243, "", "Frame Capture Bus Interface" } , + { 0x112E, 0x0000, "", "EIDE/hdd and IDE/cd-rom Ctrlr" } , + { 0x112E, 0x000B, "", "EIDE/hdd and IDE/cd-rom Ctrlr" } , + { 0x112F, 0x0000, "ICPCI", "" } , + { 0x112F, 0x0001, "", "video frame grabber/processor" } , + { 0x1131, 0x7146, "SAA7146", "Multi Media Bridge Scaler" } , + { 0x1134, 0x0001, "", "Raceway Bridge" } , + { 0x1135, 0x0001, "", "Printer Cntrlr" } , + { 0x1138, 0x8905, "8905", "STD 32 Bridge" } , + { 0x1139, 0x0001, "", "VGA" } , + { 0x1139, 0x0001, "", "VGA compatible 3D graphics" } , + { 0x1141, 0x0001, "", "EIDE/ATAPI super adapter" } , + { 0x1142, 0x3210, "ProMotion 3210", "VGA/AVI Playback Accelerator" } , + { 0x1142, 0x6410, "", "GUI Accelerator" } , + { 0x1142, 0x6412, "", "GUI Accelerator" } , + { 0x1142, 0x6420, "", "GUI Accelerator" } , + { 0x1142, 0x6422, "Provideo", "" } , + { 0x1142, 0x6424, "", "GUI Accelerator" } , + { 0x1142, 0x6426, "", "GUI Accelerator" } , + { 0x1144, 0x0001, "", "Noservo Cntrlr" } , + { 0x1148, 0x4000, "", "FDDI adapter" } , + { 0x1158, 0x3011, "", "Tokenet/vg 1001/10m anylan" } , + { 0x1158, 0x9051, "", "Lanfleet/Truevalue" } , + { 0x1159, 0x0001, "MV1000", "" } , + { 0x1161, 0x0001, "", "Host Bridge" } , + { 0x1165, 0x0001, "", "Motion JPEG rec/play w/audio" } , + { 0x1178, 0xAFA1, "", "Fast Ethernet" } , + { 0x1179, 0x0601, "", "Toshiba CPU to PCI bridge" } , + { 0x1179, 0x060A, "", "Toshiba ToPIC95 CardBus Controller" } , + { 0x1189, 0x1592, "", "?" } , + { 0x118C, 0x0014, "PCIB", "C-bus II to PCI bus host bridge chip" } , + { 0x118C, 0x1117, "", "" } , + { 0x118D, 0x0001, "n/a", "Raptor-PCI framegrabber" } , + { 0x118D, 0x0012, "Model 12", "Road Runner Frame Grabber" } , + { 0x118D, 0x0014, "Model 14", "Road Runner Frame Grabber" } , + { 0x118D, 0x0024, "Model 24", "Road Runner Frame Grabber" } , + { 0x118D, 0x0044, "Model 44", "Road Runner Frame Grabber" } , + { 0x118D, 0x0112, "Model 12", "Road Runner Frame Grabber" } , + { 0x118D, 0x0114, "Model 14", "Road Runner Frame Grabber" } , + { 0x118D, 0x0124, "Model 24", "Road Runner Frame Grabber" } , + { 0x118D, 0x0144, "Model 44", "Road Runner Frame Grabber" } , + { 0x118D, 0x0212, "Model 12", "Road Runner Frame Grabber" } , + { 0x118D, 0x0214, "Model 14", "Road Runner Frame Grabber" } , + { 0x118D, 0x0224, "Model 24", "Road Runner Frame Grabber" } , + { 0x118D, 0x0244, "Model 44", "Road Runner Frame Grabber" } , + { 0x118D, 0x0312, "Model 12", "Road Runner Frame Grabber" } , + { 0x118D, 0x0314, "Model 14", "Road Runner Frame Grabber" } , + { 0x118D, 0x0324, "Model 24", "Road Runner Frame Grabber" } , + { 0x118D, 0x0344, "Model 44", "Road Runner Frame Grabber" } , + { 0x1191, 0x0001, "", "IDE Ctrlr" } , + { 0x1191, 0x0002, "", "IDE Cntrlr" } , + { 0x1191, 0x0003, "", "SCSI-2 cache Cntrlr" } , + { 0x1191, 0x0004, "ATP8400", "ASIC cache accelerator" } , + { 0x1191, 0x8001, "", "SCSI-2 cache Cntrlr" } , + { 0x1191, 0x8002, "", "SCSI-2 Cntrlr" } , + { 0x1193, 0x0001, "1221", "" } , + { 0x1199, 0x0001, "", "" } , + { 0x1199, 0x0002, "", "" } , + { 0x1199, 0x0201, "", "" } , + { 0x11A9, 0x4240, "AMCC S5933Q", "Intelligent Serial Card" } , + { 0x11AB, 0x0146, "GT-64010", "System ctrlr w/PCI for R46xx CPU" } , + { 0x11AB, 0x4801, "GT-48001", "8 port switched ethernet ctrlr" } , + { 0x11B0, 0x0292, "V292PBC", "Am29030/40 Bridge" } , + { 0x11B0, 0x0960, "V96xPBC", "i960 Bridges for i960 Processors" } , + { 0x11B0, 0xC960, "V96DPC", "i960 Dual PCI Bridge" } , + { 0x11b3, 0001, "", "" } , + { 0x11b3, 0002, "", "" } , + { 0x11b3, 0010, "", "" } , + { 0x11b3, 0100, "", "" } , + { 0x11b3, 1001, "", "" } , + { 0x11b3, 1002, "", "" } , + { 0x11B9, 0xC0ED, "SSA Ctrlr", "" } , + { 0x11C8, 0x0658, "PSB", "PCI-SCI Bridge" } , + { 0x11C9, 0x0010, "", "16-line serial DMA" } , + { 0x11C9, 0x0011, "", "4-line serial DMA" } , + { 0x11CB, 0x2000, "PCI-9050", "Target Interface" } , + { 0x11CB, 0x4000, "SUPI-1", "Target Interface" } , + { 0x11CB, 0x8000, "T225", "Bridge" } , + { 0x11D1, 0x01F7, "VxP524", "PCI Video Processor" } , + { 0x11F8, 0x7375, "PM7375", "LASAR-155 ATM SAR" } , + { 0x1208, 0x4853, "", "HS-Link Device" } , + { 0x120E, 0x0100, "Cyclom-Y", "Multiport Serial Card" } , + { 0x120E, 0x0200, "Cyclom-Z", "Intelligent Multiport Serial" } , + { 0x121A, 0x0003, "", "" } , + { 0x121a, 0x4, "", "" } , + { 0x121a, 0x5, "", "" } , + { 0x1244, 0x0700, "AVM", "B1 ISDN controller" } , + { 0x12BE, 0x3041, "AN3041Q", "CO-MEM PCI Bus Interface and Cache" } , + { 0x12be, 0x3042, "", "" } , + { 0x12C5, 0x0081, "pcivst", "PCI Thresholding Engine" } , + { 0x12E0, 0x0010, "ST16C654", "Quad UART" } , + { 0x12E0, 0x0020, "ST16C654", "Quad UART" } , + { 0x12E0, 0x0030, "ST16C654", "Quad UART" } , + { 0x12EB, 0x0001, "AU8820", "Vortex Digital Audio Processor" } , + { 0x1C1C, 0x0001, "FR710", "EIDE Ctrlr" } , + { 0x1C1C, 0x0001, "82C101", "IDE Ctrlr" } , + { 0x1DE1, 0xDC29, "DC290M", "Bus Master IDE PCI 2 controllers" } , + { 0x3D3D, 0x0004, "3C0SX", "GUI Accelerator" } , + { 0x4005, 0x2301, "AVL2301", "GUI Accelerator" } , + { 0x4005, 0x2302, "AVG2302", "GUI Accelerator" } , + { 0x4B10, 0x3080, "", "SCSI - ti" } , + { 0x4B10, 0x4010, "", "Fast/wide SCSI-2" } , + { 0x5333, 0x5631, "86C325", "Virge 3D GUI Accelerator" } , + { 0x5333, 0x8800, "", "Vision 866 GUI Accelerator" } , + { 0x5333, 0x8801, "", "Vision 964 GUI Accelerator" } , + { 0x5333, 0x8810, "86C764", "Trio 32 GUI Accelerator v0" } , + { 0x5333, 0x8811, "86C764", "Trio 32/64 GUI Accelerator v1" } , + { 0x5333, 0x8813, "86C764", "Trio 32/64 GUI Accelerator v3" } , + { 0x5333, 0x883D, "86C988", "ViRGE/VX 3D GUI Accelerator" } , + { 0x5333, 0x8880, "86C868", "GUI Accelerator v0" } , + { 0x5333, 0x8881, "86C868", "GUI Accelerator v1" } , + { 0x5333, 0x8882, "86C868", "GUI Accelerator v2" } , + { 0x5333, 0x8883, "86C868", "GUI Accelerator v3" } , + { 0x5333, 0x88B0, "86C928", "GUI Accelerator v0" } , + { 0x5333, 0x88B1, "86C928", "GUI Accelerator v1" } , + { 0x5333, 0x88B2, "86C928", "GUI Accelerator v2" } , + { 0x5333, 0x88B3, "86C928", "GUI Accelerator v3" } , + { 0x5333, 0x88C0, "86C864", "GUI Accelerator v0" } , + { 0x5333, 0x88C1, "86C864", "GUI Accelerator v1" } , + { 0x5333, 0x88C2, "86C864", "GUI Accelerator v2" } , + { 0x5333, 0x88C3, "86C864", "GUI Accelerator v3" } , + { 0x5333, 0x88D0, "86C964", "GUI Accelerator v0" } , + { 0x5333, 0x88D1, "86C964", "GUI Accelerator v1" } , + { 0x5333, 0x88D2, "86C964", "GUI Accelerator v2" } , + { 0x5333, 0x88D3, "86C964", "GUI Accelerator v3" } , + { 0x5333, 0x88F0, "86C968", "GUI Accelerator v0" } , + { 0x5333, 0x88F1, "86C968", "GUI Accelerator v1" } , + { 0x5333, 0x88F2, "86C968", "GUI Accelerator v2" } , + { 0x5333, 0x88F3, "86C968", "GUI Accelerator v3" } , + { 0x5333, 0x8A01, "", "" } , + { 0x5333, 0xCA00, "86C617", "SonicVibes PCI Audio Accelerator" } , + { 0x5455, 0x4458, "S5933", "PCI-MyBus-Bridge" } , + { 0x6374, 0x6773, "GPPCI", "PCI Interface" } , + { 0x8008, 0x0010, "PCI-WDOG1", "PCI-Watchdog 1" } , + { 0x8008, 0x0011, "PWDOG2", "Watchdog2/PCI" } , + { 0x8086, 0x0482, "82375EB", "EISA Bridge" } , + { 0x8086, 0x0483, "82424", "CPU (i486) Bridge (Saturn)" } , + { 0x8086, 0x0484, "82378", "SIO ISA Bridge" } , + { 0x8086, 0x0486, "82430ZX", "Aries i486 Bridge" } , + { 0x8086, 0x04A3, "82434LX", "CPU (Pentium) Bridge" } , + { 0x8086, 0x0960, "80960RP", "i960 RP Microprocessor/Bridge" } , + { 0x8086, 0x1221, "82092AA", "PCMCIA Bridge" } , + { 0x8086, 0x1222, "82092AA", "IDE Ctrlr" } , + { 0x8086, 0x1223, "SAA7116", "" } , + { 0x8086, 0x1227, "EtherExpress PRO100", "10/100 Fast Ethernet Adapter Card" } , + { 0x8086, 0x1228, "EE PRO/100 Smart", "Intelligent 10/100 Fast Ethernet Adapter" } , + { 0x8086, 0x1229, "82557", "Fast Ethernet LAN Controller" } , + { 0x8086, 0x122D, "82437FX", "Host Bridge (Triton)" } , + { 0x8086, 0x122E, "82371FB", "ISA Bridge (Triton)" } , + { 0x8086, 0x1230, "82371FB", "IDE Interface (Triton)" } , + { 0x8086, 0x1234, "", "Bridge: Intel Unknown device (rev 3)" } , + { 0x8086, 0x1234, "82371MX", "Mobile PCI I/O IDE Xcelerator (MPIIX)" } , + { 0x8086, 0x1235, "82437MX", "Mobile System Controller (MTSC)" } , + { 0x8086, 0x1237, "82440FX", "82441FX(PMC)/82442FX(DBX) (Mars)" } , + { 0x8086, 0x1239, "82371FB", "IDE Interface (Triton)" } , + { 0x8086, 0x1250, "82430HX", "TXC Host Bridge (Triton II)" } , + { 0x8086, 0x1960, "80960RP", "i960RP Microprocessor" } , + { 0x8086, 0x7000, "82371SB", "PIIX3 ISA Bridge (Triton II)" } , + { 0x8086, 0x7010, "82371SB", "PIIX3 IDE Interface (Triton II)" } , + { 0x8086, 0x7020, "82371SB", "PIIX3 USB Interface (Triton II)" } , + { 0x8086, 0x7030, "82430VX", "Host Bridge (Triton VX)" } , + { 0x8086, 0x7100, "430TX", "82439TX MTXC System Ctrlr" } , + { 0x8086, 0x7110, "82371AB", "PIIX4 ISA Bridge" } , + { 0x8086, 0x7111, "", "" } , + { 0x8086, 0x7112, "", "" } , + { 0x8086, 0x7113, "", "" } , + { 0x8086, 0x7180, "82443LX (PAC)", "Host/PCI bridge in 440LX AGP chipset" } , + { 0x8086, 0x7181, "82443LX (PAC)", "AGP device in 440LX AGP chipset" } , + { 0x8086, 0x7190, "", "" } , + { 0x8086, 0x7191, "", "" } , + { 0x8086, 0x84C4, "82450KX/GX", "450KX/GX PCI Bridge (Orion)" } , + { 0x8086, 0x84C5, "82453KX/GX", "450KX/GX Memory Controller (Orion)" } , + { 0x8086, 0x84CA, "", "" } , + { 0x8086, 0x84CB, "", "" } , + { 0x8800, 0x2008, "", "video assistant component" } , + { 0x9004, 0x1078, "AIC-7810C", "RAID Coprocessor" } , + { 0x9004, 0x3B78, "AHA-4944W/4944UW", "QuadChannel Fast-Wide/Ultra-Wide Diff. SCSI Ctrlr" } , + { 0x9004, 0x5075, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5078, "AVA-29xx", "AVA-2902I/AVA-2902E/AVA-2904/AVA-2910 SCSI Ctrlr" } , + { 0x9004, 0x5175, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5178, "AIC-7850", "FAST-SCSI Ctrlr" } , + { 0x9004, 0x5275, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5278, "AIC-7850", "Fast SCSI Ctrlr" } , + { 0x9004, 0x5375, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5378, "AIC-7850", "Fast SCSI Ctrlr" } , + { 0x9004, 0x5475, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5478, "AIC-7850", "Fast SCSI Ctrlr" } , + { 0x9004, 0x5575, "AVA-2930", "SCSI Ctrlr" } , + { 0x9004, 0x5578, "AIC-7855", "Fast SCSI Ctrlr" } , + { 0x9004, 0x5675, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5678, "AIC-7856", "Fast SCSI Ctrlr" } , + { 0x9004, 0x5775, "AIC-755x", "SCSI Ctrlr" } , + { 0x9004, 0x5778, "AIC-7850", "Fast SCSI Ctrlr" } , + { 0x9004, 0x5800, "AIC-5800", "PCI-to-1394 Ctrlr" } , + { 0x9004, 0x6078, "AIC-7860", "SCSI Ctrlr" } , + { 0x9004, 0x6178, "AHA-2940AU", "SCSI Ctrlr" } , + { 0x9004, 0x6278, "AIC-7860", "SCSI Ctrlr" } , + { 0x9004, 0x6378, "AIC-7860", "SCSI Ctrlr" } , + { 0x9004, 0x6478, "AIC-786x", "SCSI Ctrlr" } , + { 0x9004, 0x6578, "AIC-786x", "SCSI Ctrlr" } , + { 0x9004, 0x6678, "AIC-786x", "SCSI Ctrlr" } , + { 0x9004, 0x6778, "AIC-786x", "SCSI Ctrlr" } , + { 0x9004, 0x7078, "AIC-7870", "Fast and Wide SCSI Ctrlr" } , + { 0x9004, 0x7178, "AHA-2940/2940W", "Fast/Fast-Wide SCSI Ctrlr" } , + { 0x9004, 0x7278, "AHA-3940/3940W", "Multichannel Fast/Fast-Wide SCSI Ctrlr" } , + { 0x9004, 0x7378, "AHA-3985", "4-chan RAID SCSI Ctrlr" } , + { 0x9004, 0x7478, "AHA-2944", "SCSI Ctrlr" } , + { 0x9004, 0x7578, "AHA-3944/3944W", "Multichannel Fast/Fast-Wide Diff. SCSI Ctrlr" } , + { 0x9004, 0x7678, "AHA-4944W/4944UW", "QuadChannel Fast-Wide/Ultra-Wide Diff. SCSI Ctrlr" } , + { 0x9004, 0x7778, "AIC-787x", "SCSI Ctrlr" } , + { 0x9004, 0x7810, "aic 7810", "Memory control IC" } , + { 0x9004, 0x7850, "aic-7850", "SCSI IC" } , + { 0x9004, 0x7855, "aha 2930", "Single SCSI channel" } , + { 0x9004, 0x7860, "AIC-7860", "SCSI Ctrlr" } , + { 0x9004, 0x7870, "aic-7870", "SCSI IC" } , + { 0x9004, 0x7871, "aha 2940", "SCSI" } , + { 0x9004, 0x7872, "aha 3940", "Multiple SCSI channels" } , + { 0x9004, 0x7873, "aha 3980", "Multiple SCSI channels" } , + { 0x9004, 0x7874, "aha 2944", "Differential SCSI" } , + { 0x9004, 0x7880, "aic7880", "Fast 20 SCSI" } , + { 0x9004, 0x7890, "AIC-7890", "SCSI controller" } , + { 0x9004, 0x7891, "AIC-789x", "SCSI controller" } , + { 0x9004, 0x7892, "AIC-789x", "SCSI controller" } , + { 0x9004, 0x7893, "AIC-789x", "SCSI controller" } , + { 0x9004, 0x7894, "AIC-789x", "SCSI controller" } , + { 0x9004, 0x7895, "AHA-2940 AHA-394x", "SCSI controller AHA-2940U/UW AHA-394xAU/AUW/AUWD" } , + { 0x9004, 0x7896, "AIC-789x", "SCSI controller" } , + { 0x9004, 0x7897, "AIC-789x", "SCSI controller" } , + { 0x9004, 0x8078, "AIC-7880", "SCSI Ctrlr" } , + { 0x9004, 0x8178, "AHA-2940U/2940UW", "Ultra/Ultra-Wide SCSI Ctrlr" } , + { 0x9004, 0x8278, "AHA-3940Uxx", "AHA-3940U/3940UW/3940UWD SCSI Ctrlr" } , + { 0x9004, 0x8478, "AHA-2944UW", "Ultra-Wide Diff. SCSI Ctrlr" } , + { 0x9004, 0x8578, "AHA-3944U/3944UWD", "Fast-Wide/Ultra-Wide Diff. SCSI Ctrlr" } , + { 0x9004, 0x8678, "AHA-4944UW", "QuadChannel Ultra-Wide Diff. SCSI Ctrlr" } , + { 0x9004, 0x8778, "AIC-788x", "Ultra-Wide SCSI Ctrlr" } , + { 0x9004, 0xEC78, "AHA-4944W/4944UW", "QuadChannel Fast-Wide/Ultra-Wide Diff. SCSI Ctrlr" } , + { 0x9005, 0x001f, "", "" } , + { 0x907F, 0x2015, "IDE-2015PL", "EIDE Ctrlr" } , + { 0xD4D4, 0x0601, "", "" } , + { 0xEDD8, 0xA091, "Stingray", "GUI Accelerator" } , + { 0xEDD8, 0xA099, "Stingray", "2000PV GUI Accelerator" } , + { 0xEDD8, 0xA0A1, "ark2000mt", "64-bit GUI accelerator w/DCI playback" } , + { 0xFFFF, 0x0140, "BAD !", "BAD Buslogic BT-946C SCSI?" } , +} ; + + +// Use this value for loop control during searching: +#define PCI_DEVTABLE_LEN (sizeof(PciDevTable)/sizeof(PCI_DEVTABLE)) + + +typedef struct _PCI_CLASSCODETABLE +{ + unsigned char BaseClass ; + unsigned char SubClass ; + unsigned char ProgIf ; + char * BaseDesc ; + char * SubDesc ; + char * ProgDesc ; +} PCI_CLASSCODETABLE, *PPCI_CLASSCODETABLE ; + +PCI_CLASSCODETABLE PciClassCodeTable [] = +{ + { 0x00, 0x00, 0x00, "Pre-2.0 PCI Specification Device", "Non-VGA","" } , + { 0x00, 0x01, 0x00, "Pre-2.0 PCI Specification Device", "VGA Compatible", "" } , + + { 0x01, 0x00, 0x00, "Mass Storage Controller", "SCSI", "" } , + { 0x01, 0x01, 0x00, "Mass Storage Controller", "IDE", "" } , + { 0x01, 0x02, 0x00, "Mass Storage Controller", "Floppy", "" } , + { 0x01, 0x03, 0x00, "Mass Storage Controller", "IPI", "" } , + { 0x01, 0x04, 0x00, "Mass Storage Controller", "RAID", "" } , + { 0x01, 0x80, 0x00, "Mass Storage Controller", "Other", "" } , + + { 0x02, 0x00, 0x00, "Network Controller", "Ethernet", "" } , + { 0x02, 0x01, 0x00, "Network Controller", "Token Ring", "" } , + { 0x02, 0x02, 0x00, "Network Controller", "FDDI", "" } , + { 0x02, 0x03, 0x00, "Network Controller", "ATM", "" } , + { 0x02, 0x80, 0x00, "Network Controller", "Other", "" } , + + { 0x03, 0x00, 0x00, "Display Controller", "PC Compatible", "VGA" } , + { 0x03, 0x00, 0x01, "Display Controller", "PC Compatible", "8514" } , + { 0x03, 0x01, 0x00, "Display Controller", "XGA", "" } , + { 0x03, 0x80, 0x00, "Display Controller", "Other", "" } , + + { 0x04, 0x00, 0x00, "Multimedia Device", "Video", "" } , + { 0x04, 0x01, 0x00, "Multimedia Device", "Audio", "" } , + { 0x04, 0x80, 0x00, "Multimedia Device", "Other", "" } , + + { 0x05, 0x00, 0x00, "Memory Controller", "RAM", "" } , + { 0x05, 0x01, 0x00, "Memory Controller", "Flash", "" } , + { 0x05, 0x80, 0x00, "Memory Controller", "Other", "" } , + + { 0x06, 0x00, 0x00, "Bridge Device", "Host/PCI", "" } , + { 0x06, 0x01, 0x00, "Bridge Device", "PCI/ISA", "" } , + { 0x06, 0x02, 0x00, "Bridge Device", "PCI/EISA", "" } , + { 0x06, 0x03, 0x00, "Bridge Device", "PCI/Micro Channel", "" } , + { 0x06, 0x04, 0x00, "Bridge Device", "PCI/PCI", "" } , + { 0x06, 0x05, 0x00, "Bridge Device", "PCI/PCMCIA", "" } , + { 0x06, 0x06, 0x00, "Bridge Device", "PCI/NuBus", "" } , + { 0x06, 0x07, 0x00, "Bridge Device", "PCI/CardBus", "" } , + { 0x06, 0x80, 0x00, "Bridge Device", "Other", "" } , + + { 0x07, 0x00, 0x00, "Simple Communications Controller", "Serial", "Generic XT Compatible" } , + { 0x07, 0x00, 0x01, "Simple Communications Controller", "Serial", "16450 Compatible" } , + { 0x07, 0x00, 0x02, "Simple Communications Controller", "Serial", "16550 Compatible" } , + { 0x07, 0x01, 0x00, "Simple Communications Controller", "Parallel", "Standard" } , + { 0x07, 0x01, 0x00, "Simple Communications Controller", "Parallel", "Bidirectional" } , + { 0x07, 0x01, 0x01, "Simple Communications Controller", "Parallel", "ECP 1.X Compliant" } , + { 0x07, 0x80, 0x02, "Simple Communications Controller", "Other", "" } , + + { 0x08, 0x00, 0x00, "Base Systems Peripheral", "PIC (Programmable Interrupt Controller)", "Generic 8259" } , + { 0x08, 0x00, 0x01, "Base Systems Peripheral", "PIC (Programmable Interrupt Controller)", "ISA" } , + { 0x08, 0x00, 0x02, "Base Systems Peripheral", "PIC (Programmable Interrupt Controller)", "PCI" } , + { 0x08, 0x01, 0x00, "Base Systems Peripheral", "DMA (Direct Memory Access)", "Generic 8259" } , + { 0x08, 0x01, 0x01, "Base Systems Peripheral", "DMA (Direct Memory Access)", "ISA" } , + { 0x08, 0x01, 0x02, "Base Systems Peripheral", "DMA (Direct Memory Access)", "EISA" } , + { 0x08, 0x02, 0x00, "Base Systems Peripheral", "System Timer", "Generic 8259" } , + { 0x08, 0x02, 0x01, "Base Systems Peripheral", "System Timer", "ISA" } , + { 0x08, 0x02, 0x02, "Base Systems Peripheral", "System Timer", "EISA" } , + { 0x08, 0x03, 0x00, "Base Systems Peripheral", "RTC (Real Time Clock)", "Generic" } , + { 0x08, 0x03, 0x01, "Base Systems Peripheral", "RTC (Real Time Clock)", "ISA" } , + { 0x08, 0x80, 0x00, "Base Systems Peripheral", "Other", "" } , + + { 0x09, 0x00, 0x00, "Input Device", "Keyboard", "" } , + { 0x09, 0x01, 0x00, "Input Device", "Digitizer (Pen)", "" } , + { 0x09, 0x02, 0x00, "Input Device", "Mouse", "" } , + { 0x09, 0x80, 0x00, "Input Device", "Other", "" } , + + { 0x0A, 0x00, 0x00, "Docking Station", "Generic", "" } , + { 0x0A, 0x80, 0x00, "Docking Station", "Other", "" } , + + { 0x0B, 0x00, 0x00, "Processor", "i386", "" } , + { 0x0B, 0x01, 0x00, "Processor", "i486", "" } , + { 0x0B, 0x02, 0x00, "Processor", "Pentium", "" } , + { 0x0B, 0x10, 0x00, "Processor", "Alpha", "" } , + { 0x0B, 0x20, 0x00, "Processor", "Power PC", "" } , + { 0x0B, 0x80, 0x00, "Processor", "Co-processor", "" } , + + { 0x0C, 0x00, 0x00, "Serial Bus Controller", "Firewire (IEEE 1394)", "" } , + { 0x0C, 0x01, 0x00, "Serial Bus Controller", "ACCESS.bus", "" } , + { 0x0C, 0x02, 0x00, "Serial Bus Controller", "SSA (Serial Storage Archetecture)", "" } , + { 0x0C, 0x03, 0x00, "Serial Bus Controller", "USB (Universal Serial Bus)", "" } , + { 0x0C, 0x04, 0x00, "Serial Bus Controller", "Fibre Channel", "" } , + + { 0xFF, 0x00, 0x00, "Unknown", "Device Does Not Fit In Class Codes", "UDF" } , +} ; + +// Use this value for loop control during searching: +#define PCI_CLASSCODETABLE_LEN (sizeof(PciClassCodeTable)/sizeof(PCI_CLASSCODETABLE)) + + +char * PciCommandFlags [] = +{ + "I/O Access", + "Memory Access", + "Bus Mastering", + "Special Cycles", + "Memory Write & Invalidate", + "Palette Snoop", + "Parity Errors", + "Wait Cycles", + "System Errors", + "Fast Back-To-Back", + "Reserved 10", + "Reserved 11", + "Reserved 12", + "Reserved 13", + "Reserved 14", + "Reserved 15" +} ; + +// Use this value for loop control during searching: +#define PCI_COMMANDFLAGS_LEN (sizeof(PciCommandFlags)/sizeof(char *)) + + +char * PciStatusFlags [] = +{ + "Reserved 0", + "Reserved 1", + "Reserved 2", + "Reserved 3", + "Reserved 4", + "66 MHz Capable", + "User-Defined Features", + "Fast Back-To-Back", + "Data Parity Reported", + "", + "", + "Signalled Target Abort", + "Received Target Abort", + "Received Master Abort", + "Signalled System Error", + "Detected Parity Error" +} ; + +// Use this value for loop control during searching: +#define PCI_STATUSFLAGS_LEN (sizeof(PciStatusFlags)/sizeof(char *)) + + +char * PciDevSelFlags [] = +{ + "Fast Devsel Speed", // TypeC + "Medium Devsel Speed", // TypeB + "Slow Devsel Speed", // TypeA + "Reserved 9&10" +} ; + +// Use this value for loop control during searching: +#define PCI_DEVSELFLAGS_LEN (sizeof(PciDevSelFlags)/sizeof(char *)) +
--- a/packages/packages +++ b/packages/packages @@ -304,6 +304,13 @@ package CYGPKG_IO_SERIAL { include_dir cyg/io } +package CYGPKG_IO_PCI { + alias { "PCI configuration library" io_pci } + directory io/pci + default_value 0 + include_dir cyg/io +} + package CYGPKG_DEVICES_WALLCLOCK { alias { "Wallclock Device Code" wallclock devices_wallclock device_wallclock } directory devs/wallclock