Mercurial > flash_v2
changeset 92:08ffab08d2ee ecos-sw-2000-05-26
Merge from eCos master repository on 2000-05-26-07:47:03-BST
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--- a/host/tools/ecostest/common/eCosTestDownloadFilter.cpp +++ b/host/tools/ecostest/common/eCosTestDownloadFilter.cpp @@ -53,7 +53,7 @@ #include "eCosStd.h" #include "eCosTrace.h" -#define DL_FILTER_VER "$Id: eCosTestDownloadFilter.cpp,v 1.8 2000/05/19 12:47:51 jlarmour Exp $" +#define DL_FILTER_VER "$Id: eCosTestDownloadFilter.cpp,v 1.9 2000/05/26 13:46:34 jlarmour Exp $" #include "eCosTestDownloadFilter.h" CeCosTestDownloadFilter::CeCosTestDownloadFilter():
--- a/host/tools/ecostest/common/eCosTestMonitorFilter.cpp +++ b/host/tools/ecostest/common/eCosTestMonitorFilter.cpp @@ -45,7 +45,7 @@ #include "eCosStd.h" -#define SER_FILTER_VER "$Id: eCosTestMonitorFilter.cpp,v 1.7 2000/05/19 12:47:51 jlarmour Exp $" +#define SER_FILTER_VER "$Id: eCosTestMonitorFilter.cpp,v 1.8 2000/05/26 13:46:34 jlarmour Exp $" #include "eCosTestMonitorFilter.h" CeCosTestMonitorFilter::CeCosTestMonitorFilter():
--- a/host/tools/ecostest/common/eCosTestSerialFilter.cpp +++ b/host/tools/ecostest/common/eCosTestSerialFilter.cpp @@ -51,7 +51,7 @@ #include "eCosStd.h" -#define SER_FILTER_VER "$Id: eCosTestSerialFilter.cpp,v 1.8 2000/05/19 12:47:51 jlarmour Exp $" +#define SER_FILTER_VER "$Id: eCosTestSerialFilter.cpp,v 1.9 2000/05/26 13:46:34 jlarmour Exp $" #include "eCosTestSerialFilter.h" #include "eCosThreadUtils.h"
--- a/packages/ecos.db +++ b/packages/ecos.db @@ -262,6 +262,7 @@ package CYGPKG_DEVICES_WALLCLOCK_SH3 { Hitachi SH3 CPU's RTC module." } + package CYGPKG_DEVICES_WATCHDOG { alias { "Watchdog device code" watchdog devices_watchdog device_watchdog } directory devs/watchdog
--- a/packages/hal/arm/aeb/current/ChangeLog +++ b/packages/hal/arm/aeb/current/ChangeLog @@ -1,3 +1,7 @@ +2000-05-22 Jesper Skov <jskov@redhat.com> + + * src/flash_cksum.tcl: Use correct intepreter. + 2000-04-07 Jonathan Larmour <jlarmour@redhat.co.uk> * src/flash_cksum.tcl:
--- a/packages/hal/arm/aeb/current/src/flash_cksum.tcl +++ b/packages/hal/arm/aeb/current/src/flash_cksum.tcl @@ -1,6 +1,13 @@ #!/bin/sh # the next line restarts using tclsh \ - exec tclsh "$0" ${1+"$@"} + exec sh -c "if ( echo | tclsh ) 2>/dev/null ; then \ + exec tclsh \"$0\" ${1+\"$@\"} ; \ + elif ( echo | cygtclsh80 ) 2>/dev/null ; then \ + exec cygtclsh80 \"$0\" ${1+\"$@\"} ; \ + else \ + echo Could not find TCL interpreter ; \ + exit 1 ; \ + fi" #=============================================================================== #
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,12 @@ +2000-05-25 Jesper Skov <jskov@redhat.com> + + * cdl/debugging.cdl: Allow thread support to included for ROM + monitor builds. + +2000-05-22 Jesper Skov <jskov@redhat.com> + + * cdl/debugging.cdl: Allow platform to prevent CTRLC inclusion. + 2000-04-12 Jesper Skov <jskov@redhat.com> * cdl/debugging.cdl: Don't let interfaces define anything.
--- a/packages/hal/common/current/cdl/debugging.cdl +++ b/packages/hal/common/current/cdl/debugging.cdl @@ -83,9 +83,15 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SU GDB stubs are present." } +cdl_interface CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED { + display "Platform does not support CTRLC" + no_define +} + cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { display "Include GDB external break support when no stubs" requires !CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + active_if { CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0 } default_value 1 description " This option adds an interrupt handler for the GDB serial line @@ -98,9 +104,11 @@ cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SU cdl_option CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT { display "Include GDB multi-threading debug support" - requires CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT - default_value CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT + active_if { CYGSEM_HAL_ROM_MONITOR || CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT } + default_value 1 description " This option enables some extra HAL code which is needed to support multi-threaded source level debugging." + + compile dbg-threads-syscall.c }
--- a/packages/hal/mips/arch/current/ChangeLog +++ b/packages/hal/mips/arch/current/ChangeLog @@ -1,3 +1,29 @@ +2000-05-25 Jesper Skov <jskov@redhat.com> + + * include/basetype.h: + * src/mipsfp.c: + Support FPU double-LE layout in BE mode. + +2000-05-24 Jesper Skov <jskov@redhat.com> + + * src/mipsfp.c: Also handle doubles in 32bit FPU mode. + +2000-05-23 Jesper Skov <jskov@redhat.com> + + * include/arch.inc: + * src/vectors.S: + Made exception return safe. + +2000-05-22 Jesper Skov <jskov@redhat.com> + + * src/vectors.S: Call CTRLC init after stub initialization. + + * cdl/hal_mips.cdl: Only include CTRLC support if not prevented + by platform. + + * include/hal_cache.h: When using 'cache' instruction, hit all + ways, not only way0. + 2000-05-18 Jesper Skov <jskov@redhat.com> * include/hal_io.h: Allow platforms to override IO macro
--- a/packages/hal/mips/arch/current/cdl/hal_mips.cdl +++ b/packages/hal/mips/arch/current/cdl/hal_mips.cdl @@ -83,6 +83,7 @@ cdl_package CYGPKG_HAL_MIPS { cdl_option CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT { display "Architecture GDB CTRLC support" calculated { CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT } + active_if { CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0 } description " If either the CTRLC or BREAK support options in hal.h are set then set our own option to turn on shared generic support for
--- a/packages/hal/mips/arch/current/include/arch.inc +++ b/packages/hal/mips/arch/current/include/arch.inc @@ -252,11 +252,12 @@ #else .macro hal_cpu_eret pc,sr .set mips3 - mtc0 \pc,epc # put PC in EPC + ori \sr,\sr,2 # prevent interrupts until eret + mtc0 \sr,status # put SR back nop nop nop - mtc0 \sr,status # put SR back + mtc0 \pc,epc # put PC in EPC nop nop nop
--- a/packages/hal/mips/arch/current/include/basetype.h +++ b/packages/hal/mips/arch/current/include/basetype.h @@ -56,6 +56,14 @@ # error MIPS endianess not defined by configuration #endif +#if defined(CYGPKG_HAL_MIPS_DOUBLE_MSBFIRST) +# define CYG_DOUBLE_BYTEORDER CYG_MSBFIRST // Big endian +#elif defined(CYGPKG_HAL_MIPS_DOUBLE_LSBFIRST) +# define CYG_DOUBLE_BYTEORDER CYG_LSBFIRST // Little endian +#else +# define CYG_DOUBLE_BYTEORDER CYG_BYTEORDER // default to CPU endianess +#endif + //----------------------------------------------------------------------------- // MIPS does not usually use labels with undersores. Some labels generated // by the linker do, so add an underscore where required.
--- a/packages/hal/mips/arch/current/include/hal_cache.h +++ b/packages/hal/mips/arch/current/include/hal_cache.h @@ -91,6 +91,49 @@ #endif //----------------------------------------------------------------------------- +// Cache instruction uses LSB to specify which WAY to affect. This macro +// defines the necessary cache instructions to affect all ways. +#if (HAL_DCACHE_WAYS == 1) +#define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ + asm volatile ("cache %0,0(%1);" \ + : : "I" (_cmd_), "r"(_addr_) ) +#elif (HAL_DCACHE_WAYS == 2) +#define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ + asm volatile ("cache %0,0(%1);" \ + "cache %0,1(%1);" \ + : : "I" (_cmd_), "r"(_addr_) ) +#elif (HAL_DCACHE_WAYS == 4) +#define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \ + asm volatile ("cache %0,0(%1);" \ + "cache %0,1(%1);" \ + "cache %0,2(%1);" \ + "cache %0,3(%1);" \ + : : "I" (_cmd_), "r"(_addr_) ) +#else +# error "Unsupported number of ways" +#endif + +#if (HAL_ICACHE_WAYS == 1) +#define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ + asm volatile ("cache %0,0(%1);" \ + : : "I" (_cmd_), "r"(_addr_) ) +#elif (HAL_ICACHE_WAYS == 2) +#define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ + asm volatile ("cache %0,0(%1);" \ + "cache %0,1(%1);" \ + : : "I" (_cmd_), "r"(_addr_) ) +#elif (HAL_ICACHE_WAYS == 4) +#define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \ + asm volatile ("cache %0,0(%1);" \ + "cache %0,1(%1);" \ + "cache %0,2(%1);" \ + "cache %0,3(%1);" \ + : : "I" (_cmd_), "r"(_addr_) ) +#else +# error "Unsupported number of ways" +#endif + +//----------------------------------------------------------------------------- // Global control of data cache // Enable the data cache @@ -119,16 +162,16 @@ // Synchronize the contents of the cache with memory. // This uses the index-writeback-invalidate operation. #ifndef HAL_DCACHE_SYNC_DEFINED -#define HAL_DCACHE_SYNC() \ -{ \ - register CYG_ADDRESS _baddr_ = 0x80000000; \ - register CYG_ADDRESS _addr_ = 0x80000000; \ - register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ -} +#define HAL_DCACHE_SYNC() \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + register CYG_WORD _size_ = HAL_DCACHE_SIZE; \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { _HAL_ASM_DCACHE_ALL_WAYS(0x01, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + CYG_MACRO_END #endif // Set the data cache refill burst size @@ -144,20 +187,20 @@ // and then lock the cache so that it stays there. // This uses the fetch-and-lock cache operation. #ifndef HAL_DCACHE_LOCK_DEFINED -#define HAL_DCACHE_LOCK(_base_, _asize_) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED( _state_ ); \ - if( _state_ ) { \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ - } \ -CYG_MACRO_END +#define HAL_DCACHE_LOCK(_base_, _asize_) \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) { \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + } \ + CYG_MACRO_END #endif // Undo a previous lock operation. @@ -184,54 +227,54 @@ CYG_MACRO_END // for the given address range. // This uses the hit-writeback-invalidate cache operation. #ifndef HAL_DCACHE_FLUSH_DEFINED -#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED( _state_ ); \ - if( _state_ ) { \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ - } \ -CYG_MACRO_END +#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) { \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + } \ + CYG_MACRO_END #endif // Invalidate cache lines in the given range without writing to memory. // This uses the hit-invalidate cache operation. #ifndef HAL_DCACHE_INVALIDATE_DEFINED -#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ -} +#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + CYG_MACRO_END #endif // Write dirty cache lines to memory for the given address range. // This uses the hit-writeback cache operation. #ifndef HAL_DCACHE_STORE_DEFINED -#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_DCACHE_IS_ENABLED( _state_ ); \ - if( _state_ ) { \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ - } \ -CYG_MACRO_END +#define HAL_DCACHE_STORE( _base_ , _asize_ ) \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_DCACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) { \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + } \ + CYG_MACRO_END #endif // Preread the given range into the cache with the intention of reading @@ -266,15 +309,15 @@ CYG_MACRO_END // Invalidate the entire cache // This uses the index-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED -#define HAL_ICACHE_INVALIDATE_ALL() \ -{ \ - register CYG_ADDRESS _baddr_ = 0x80000000; \ - register CYG_ADDRESS _addr_ = 0x80000000; \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ -} +#define HAL_ICACHE_INVALIDATE_ALL() \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = 0x80000000; \ + register CYG_ADDRESS _addr_ = 0x80000000; \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + CYG_MACRO_END #endif // Synchronize the contents of the cache with memory. @@ -290,20 +333,20 @@ CYG_MACRO_END // and then lock the cache so that it stays there. // This uses the fetch-and-lock cache operation. #ifndef HAL_ICACHE_LOCK_DEFINED -#define HAL_ICACHE_LOCK(_base_, _asize_) \ -CYG_MACRO_START \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - register CYG_WORD _state_; \ - HAL_ICACHE_IS_ENABLED( _state_ ); \ - if( _state_ ) { \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ - } \ -CYG_MACRO_END +#define HAL_ICACHE_LOCK(_base_, _asize_) \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + register CYG_WORD _state_; \ + HAL_ICACHE_IS_ENABLED( _state_ ); \ + if( _state_ ) { \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ + { _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + } \ + CYG_MACRO_END #endif // Undo a previous lock operation. @@ -322,16 +365,16 @@ CYG_MACRO_END // Invalidate cache lines in the given range without writing to memory. // This uses the hit-invalidate cache operation. #ifndef HAL_ICACHE_INVALIDATE_DEFINED -#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ -{ \ - register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ - register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ - register CYG_WORD _size_ = (_asize_); \ - _HAL_ASM_SET_MIPS_ISA(3); \ - for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ - { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \ - _HAL_ASM_SET_MIPS_ISA(0); \ -} +#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ + CYG_MACRO_START \ + register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ + register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ + register CYG_WORD _size_ = (_asize_); \ + _HAL_ASM_SET_MIPS_ISA(3); \ + for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ + { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); } \ + _HAL_ASM_SET_MIPS_ISA(0); \ + CYG_MACRO_END #endif //-----------------------------------------------------------------------------
--- a/packages/hal/mips/arch/current/src/mipsfp.c +++ b/packages/hal/mips/arch/current/src/mipsfp.c @@ -67,9 +67,6 @@ #if (CYG_BYTEORDER == CYG_MSBFIRST) // Big endian -// Note: there do not seem to be any current machines which are Big Endian but -// have a mixed up double layout. - typedef union { cyg_int32 asi32[2]; @@ -80,17 +77,26 @@ typedef union struct { +#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) unsigned int sign : 1; unsigned int exponent: 11; unsigned int fraction0:4; unsigned int fraction1:16; unsigned int fraction2:16; unsigned int fraction3:16; - +#else + unsigned int fraction2:16; + unsigned int fraction3:16; + unsigned int sign : 1; + unsigned int exponent: 11; + unsigned int fraction0:4; + unsigned int fraction1:16; +#endif } number; struct { +#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) unsigned int sign : 1; unsigned int exponent: 11; unsigned int quiet:1; @@ -98,12 +104,26 @@ typedef union unsigned int function1:16; unsigned int function2:16; unsigned int function3:16; +#else + unsigned int function2:16; + unsigned int function3:16; + unsigned int sign : 1; + unsigned int exponent: 11; + unsigned int quiet:1; + unsigned int function0:3; + unsigned int function1:16; +#endif } nan; struct { +#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) cyg_uint32 msw; cyg_uint32 lsw; +#else + cyg_uint32 lsw; + cyg_uint32 msw; +#endif } parts; @@ -284,9 +304,26 @@ reg2flt( CYG_HAL_FPU_REG *fpu_reg_p, Cyg static __inline__ void flt2reg( Cyg_libm_ieee_float_shape_type *flt, CYG_HAL_FPU_REG *fpu_reg_p ) { - *fpu_reg_p = flt->asi32; +#if defined(CYGHWR_HAL_MIPS_FPU_32BIT) || (CYG_BYTEORDER == CYG_LSBFIRST) + *(cyg_int32 *)fpu_reg_p = flt->asi32; +#else + *((cyg_int32 *)fpu_reg_p + 1) = flt->asi32; +# endif } // flt2reg() +static __inline__ void +reg2dbl( CYG_HAL_FPU_REG *fpu_reg_p, Cyg_libm_ieee_double_shape_type *flt) +{ + flt->asi64 = *(cyg_int64 *)fpu_reg_p; +} // reg2dbl() + +static __inline__ void +dbl2reg( Cyg_libm_ieee_double_shape_type *flt, CYG_HAL_FPU_REG *fpu_reg_p ) +{ + *(cyg_uint64*)fpu_reg_p = flt->asi64; +} // dbl2reg() + + // This function returns non-zero if the exception has been handled // successfully. @@ -379,8 +416,8 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if (fp64bit) { Cyg_libm_ieee_double_shape_type s1, s2; - s1.asi64 = *srcreg1; - s2.asi64 = *srcreg2; + reg2dbl( srcreg1, &s1 ); + reg2dbl( srcreg2, &s2 ); if ( issubnormal( s1 ) ) { // flush to 0 and restart // but preserve sign @@ -388,7 +425,7 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s1.value = -0.0; else s1.value = 0.0; - *srcreg1 = s1.asi64; + dbl2reg( &s1, srcreg1 ); handled++; } @@ -404,7 +441,7 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s2.value = -0.0; else s2.value = 0.0; - *srcreg2 = s2.asi64; + dbl2reg( &s2, srcreg2 ); handled++; } @@ -439,8 +476,8 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if ( fp64bit ) { Cyg_libm_ieee_double_shape_type d, s; - d.asi64 = *dstreg; - s.asi64 = *srcreg1; + reg2dbl( dstreg, &d ); + reg2dbl( srcreg1, &s ); if ( issubnormal( s ) ) { // Sqrt of something tiny is 0 // if this is a delay slot, we can't restart properly @@ -451,14 +488,14 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s.value = -0.0; else s.value = 0.0; - *srcreg1 = s.asi64; + dbl2reg( &s, srcreg1 ); } else { // but preserve sign if (s.number.sign) d.value = -0.0; else d.value = 0.0; - *dstreg = d.asi64; + dbl2reg( &d, dstreg ); regs->pc += 4; // We've dealt with this so move on } handled++; @@ -499,8 +536,8 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if ( fp64bit ) { Cyg_libm_ieee_double_shape_type d, s; - d.asi64 = *dstreg; - s.asi64 = *srcreg1; + reg2dbl( dstreg, &d ); + reg2dbl( srcreg1, &s ); // if this is a delay slot, we can't restart properly // so if it is subnormal, clear the source register instead @@ -513,13 +550,13 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s.value = -0.0; else s.value = 0.0; - *srcreg1 = s.asi64; + dbl2reg( &s, srcreg1 ); handled++; } } else { d.asi64 = s.asi64; d.number.sign = 0; - *dstreg = d.asi64; + dbl2reg( &d, dstreg ); regs->pc += 4; handled++; } @@ -558,8 +595,8 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if ( fp64bit ) { Cyg_libm_ieee_double_shape_type d, s; - d.asi64 = *dstreg; - s.asi64 = *srcreg1; + reg2dbl( dstreg, &d ); + reg2dbl( srcreg1, &s ); // if this is a delay slot, we can't restart properly // so if it is subnormal, clear the source register instead @@ -570,12 +607,12 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s.value = -0.0; else s.value = 0.0; - *srcreg1 = s.asi64; + dbl2reg( &s, srcreg1 ); handled++; } } else { d.asi64 = s.asi64; - *dstreg = d.asi64; + dbl2reg( &d, dstreg ); regs->pc += 4; handled++; } @@ -613,8 +650,8 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if ( fp64bit ) { Cyg_libm_ieee_double_shape_type d, s; - d.asi64 = *dstreg; - s.asi64 = *srcreg1; + reg2dbl( dstreg, &d ); + reg2dbl( srcreg1, &s ); // if this is a delay slot, we can't restart properly // so if it is subnormal, clear the source register instead @@ -625,13 +662,13 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s.value = -0.0; else s.value = 0.0; - *srcreg1 = s.asi64; + dbl2reg( &s, srcreg1 ); handled++; } } else { d.asi64 = s.asi64; d.number.sign = s.number.sign ? 0 : 1; - *dstreg = d.asi64; + dbl2reg( &d, dstreg ); regs->pc += 4; handled++; } @@ -682,7 +719,7 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if ( fp64bit ) { Cyg_libm_ieee_double_shape_type s; - s.asi64 = *srcreg1; + reg2dbl( srcreg1, &s ); // just try and 0 the source register if it is subnormal if ( issubnormal( s ) ) { @@ -691,7 +728,7 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s.value = -0.0; else s.value = 0.0; - *srcreg1 = s.asi64; + dbl2reg( &s, srcreg1 ); handled++; } } else { // 32-bit @@ -718,8 +755,8 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis if (fp64bit) { Cyg_libm_ieee_double_shape_type s1, s2; - s1.asi64 = *srcreg1; - s2.asi64 = *srcreg2; + reg2dbl( srcreg1, &s1 ); + reg2dbl( srcreg2, &s2 ); if ( issubnormal( s1 ) ) { // flush to 0 and restart // but preserve sign @@ -727,7 +764,7 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s1.value = -0.0; else s1.value = 0.0; - *srcreg1 = s1.asi64; + dbl2reg( &s1, srcreg1 ); handled++; } @@ -737,7 +774,7 @@ cyg_hal_mips_process_fpe( HAL_SavedRegis s2.value = -0.0; else s2.value = 0.0; - *srcreg2 = s2.asi64; + dbl2reg( &s2, srcreg2 ); handled++; }
--- a/packages/hal/mips/arch/current/src/vectors.S +++ b/packages/hal/mips/arch/current/src/vectors.S @@ -59,7 +59,7 @@ ## Hardware supplied vectors .set noreorder - + .section ".reset_vector","ax" # Reset vector at 0xBFC00000 @@ -197,6 +197,11 @@ FUNC_START(_start) jal initialize_stub nop #endif +#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) + .extern hal_ctrlc_isr_init + jal hal_ctrlc_isr_init + nop +#endif # Call cyg_start @@ -604,13 +609,16 @@ 8: #endif restore_state: +#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) move k0,v0 +#endif # All done, restore CPU state and continue addi sp,sp,mips_stack_frame_size # retrieve CPU state ptr # Disable interrupts again while we restore state. + hal_cpu_int_disable hal_diag_restore
--- a/packages/hal/mips/jmr3904/current/ChangeLog +++ b/packages/hal/mips/jmr3904/current/ChangeLog @@ -1,3 +1,7 @@ +2000-05-22 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c: Let arch call ctrlc_init. + 2000-05-10 Jonathan Larmour <jlarmour@redhat.co.uk> * include/pkgconf/mlt_mips_tx39_jmr3904_rom.mlt: Fix mistake in last
--- a/packages/hal/mips/jmr3904/current/src/plf_misc.c +++ b/packages/hal/mips/jmr3904/current/src/plf_misc.c @@ -78,14 +78,6 @@ void hal_platform_init(void) #endif -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) - { - void hal_ctrlc_isr_init(void); - hal_ctrlc_isr_init(); - } - -#endif - #if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) {
--- a/packages/hal/mips/sim/current/ChangeLog +++ b/packages/hal/mips/sim/current/ChangeLog @@ -1,3 +1,7 @@ +2000-05-22 Jesper Skov <jskov@redhat.com> + + * cdl/hal_mips_sim.cdl: Doesn't support CTRLC. + 2000-04-04 Jonathan Larmour <jlarmour@redhat.co.uk> * include/pkgconf/mlt_mips_tx39_sim_ram.ldi,
--- a/packages/hal/mips/sim/current/cdl/hal_mips_sim.cdl +++ b/packages/hal/mips/sim/current/cdl/hal_mips_sim.cdl @@ -56,6 +56,7 @@ cdl_package CYGPKG_HAL_MIPS_SIM { compile hal_diag.c platform.S plf_misc.c + implements CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED cdl_option CYGBLD_HAL_TARGET_H { display "architecture header file"
--- a/packages/hal/mips/vrc4373/current/ChangeLog +++ b/packages/hal/mips/vrc4373/current/ChangeLog @@ -1,3 +1,13 @@ +2000-05-22 Jesper Skov <jskov@redhat.com> + + * src/hal_diag.c: Removed CTRLC init hacks. + + * src/plf_misc.c (hal_ctrlc_isr_init): Made public. + +2000-05-17 Jesper Skov <jskov@redhat.com> + + * src/plf_misc.c: Let arch call ctrlc_init. + 2000-02-18 Jonathan Larmour <jlarmour@redhat.co.uk> * cdl/hal_mips_vr4300_vrc4373.cdl (CYGBLD_BUILD_GDB_STUBS): When
--- a/packages/hal/mips/vrc4373/current/src/hal_diag.c +++ b/packages/hal/mips/vrc4373/current/src/hal_diag.c @@ -81,11 +81,7 @@ int fd; static unsigned char _diag_init[] = { 0x00, /* Register 0 */ -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) - 0x10, /* Register 1 - rx interrupts only */ -#else 0x00, /* Register 1 - no interrupts */ -#endif 0x00, /* Register 2 */ 0xC1, /* Register 3 - Rx enable, 8 data */ 0x44, /* Register 4 - x16 clock, 1 stop, no parity */ @@ -93,11 +89,7 @@ static unsigned char _diag_init[] = { 0x00, /* Register 6 */ 0x00, /* Register 7 */ 0x00, /* Register 8 */ -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) - 0x0a, /* Register 9 */ -#else 0x00, /* Register 9 */ -#endif 0x00, /* Register 10 */ 0x56, /* Register 11 - Rx, Tx clocks from baud rate generator */ 0x00, /* Register 12 - baud rate LSB */
--- a/packages/hal/mips/vrc4373/current/src/plf_misc.c +++ b/packages/hal/mips/vrc4373/current/src/plf_misc.c @@ -70,14 +70,6 @@ void hal_platform_init(void) patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); } #endif -#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) - - { - static void hal_ctrlc_isr_init(void); - hal_ctrlc_isr_init(); - } -#endif - } /*------------------------------------------------------------------------*/ @@ -141,7 +133,7 @@ void cyg_hal_user_break( CYG_ADDRWORD *r struct Hal_SavedRegisters *hal_saved_interrupt_state; -static void hal_ctrlc_isr_init(void) +void hal_ctrlc_isr_init(void) { HAL_DUART_WRITE_CR( DUART_CHAN, 1, 0x10 ); HAL_DUART_WRITE_CR( DUART_CHAN, 9, 0x0a );
--- a/packages/language/c/libc/current/ChangeLog +++ b/packages/language/c/libc/current/ChangeLog @@ -1,3 +1,13 @@ +2000-05-25 Hugo Tyson <hmt@cygnus.co.uk> + + * src/clibincl/stream.inl (set_error): If the error is EEOF, set + the EOF flag (flags.at_eof) so that clients know. + + * src/stdio/input/fgetc.cxx (__fgetc): + * src/stdio/input/fgets.cxx (_fgets): + * src/stdio/input/fread.cxx (_fread): Correctly handle an error, + or EOF indication, from real_stream->refill_read_buffer(). + 2000-05-16 Jesper Skov <jskov@redhat.com> * tests/signal/signal2.c: Also reset DIV_BY_ZERO vector.
--- a/packages/language/c/libc/current/src/clibincl/stream.inl +++ b/packages/language/c/libc/current/src/clibincl/stream.inl @@ -284,6 +284,9 @@ Cyg_StdioStream::set_error( Cyg_ErrNo er errno = error = errno_to_set; + if ( EEOF == error ) + flags.at_eof = 1; + unlock_me(); } // set_error()
--- a/packages/language/c/libc/current/src/stdio/input/fgetc.cxx +++ b/packages/language/c/libc/current/src/stdio/input/fgetc.cxx @@ -77,14 +77,14 @@ externC int err = real_stream->read( &c, 1, &bytes_read ); - // FIXME: Why do we need this? - if (!err && !bytes_read) // if no err, but nothing to read, try again - { - real_stream->refill_read_buffer(); - err = real_stream->read( &c, 1, &bytes_read ); + // Why do we need this? Because the buffer might be empty. + if (!err && !bytes_read) { // if no err, but nothing to read, try again + err = real_stream->refill_read_buffer(); + if ( !err ) + err = real_stream->read( &c, 1, &bytes_read ); } // if - CYG_ASSERT( 1 == bytes_read, "Didn't read 1 byte!" ); + CYG_ASSERT( (ENOERR != err) || (1 == bytes_read), "Didn't read 1 byte!" ); if (err) {
--- a/packages/language/c/libc/current/src/stdio/input/fgets.cxx +++ b/packages/language/c/libc/current/src/stdio/input/fgets.cxx @@ -76,8 +76,9 @@ externC char * err = real_stream->read( (cyg_uint8 *)s, n-1, &bytes_read ); if (!err && !bytes_read) { // if no err, but nothing to read, try again - real_stream->refill_read_buffer(); - err = real_stream->read( (cyg_uint8 *)s, n-1, &bytes_read ); + err = real_stream->refill_read_buffer(); + if ( !err ) + err = real_stream->read( (cyg_uint8 *)s, n-1, &bytes_read ); } // if
--- a/packages/language/c/libc/current/src/stdio/input/fread.cxx +++ b/packages/language/c/libc/current/src/stdio/input/fread.cxx @@ -89,9 +89,10 @@ externC size_t &bytes_read ); if (!err && !bytes_read) { // if no err, but nothing to read, try again - real_stream->refill_read_buffer(); - err = real_stream->read( (cyg_uint8 *)ptr, object_size*num_objects, - &bytes_read ); + err = real_stream->refill_read_buffer(); + if ( !err ) + err = real_stream->read( (cyg_uint8 *)ptr, object_size*num_objects, + &bytes_read ); } // if if (err) {
--- a/packages/language/c/libm/current/ChangeLog +++ b/packages/language/c/libm/current/ChangeLog @@ -1,3 +1,7 @@ +2000-05-26 Jesper Skov <jskov@redhat.com> + + * include/sys/ieeefp.h: Support FPU double-LE layout in BE mode. + 2000-03-28 John Dallaway <jld@cygnus.co.uk> * cdl/libm.cdl:
--- a/packages/language/c/libm/current/include/sys/ieeefp.h +++ b/packages/language/c/libm/current/include/sys/ieeefp.h @@ -61,6 +61,8 @@ // Note: there do not seem to be any current machines which are Big Endian but // have a mixed up double layout. +#if (CYG_BYTEORDER == CYG_MSBFIRST) // Big endian + typedef union { cyg_int32 asi32[2]; @@ -71,17 +73,26 @@ typedef union struct { +#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) unsigned int sign : 1; unsigned int exponent: 11; unsigned int fraction0:4; unsigned int fraction1:16; unsigned int fraction2:16; unsigned int fraction3:16; - +#else + unsigned int fraction2:16; + unsigned int fraction3:16; + unsigned int sign : 1; + unsigned int exponent: 11; + unsigned int fraction0:4; + unsigned int fraction1:16; +#endif } number; struct { +#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) unsigned int sign : 1; unsigned int exponent: 11; unsigned int quiet:1; @@ -89,18 +100,31 @@ typedef union unsigned int function1:16; unsigned int function2:16; unsigned int function3:16; +#else + unsigned int function2:16; + unsigned int function3:16; + unsigned int sign : 1; + unsigned int exponent: 11; + unsigned int quiet:1; + unsigned int function0:3; + unsigned int function1:16; +#endif } nan; struct { +#if (CYG_DOUBLE_BYTEORDER == CYG_MSBFIRST) cyg_uint32 msw; cyg_uint32 lsw; +#else + cyg_uint32 lsw; + cyg_uint32 msw; +#endif } parts; } Cyg_libm_ieee_double_shape_type; - typedef union { cyg_int32 asi32;