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1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H |
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2 #define CYGONCE_HAL_PLATFORM_SETUP_H |
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3 |
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4 /*============================================================================= |
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5 // |
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6 // hal_platform_setup.h |
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7 // |
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8 // Platform specific support for HAL (assembly code) |
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9 // |
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10 //============================================================================= |
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11 //####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License along |
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26 // with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use macros |
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30 // or inline functions from this file, or you compile this file and link it |
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31 // with other works to produce a work based on this file, this file does not |
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32 // by itself cause the resulting work to be covered by the GNU General Public |
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33 // License. However the source code for this file must still be made available |
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34 // in accordance with section (3) of the GNU General Public License. |
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35 // |
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36 // This exception does not invalidate any other reasons why a work based on |
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37 // this file might be covered by the GNU General Public License. |
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38 // |
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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40 // at http://sources.redhat.com/ecos/ecos-license/ |
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41 // ------------------------------------------- |
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42 //####ECOSGPLCOPYRIGHTEND#### |
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43 //============================================================================= |
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44 //#####DESCRIPTIONBEGIN#### |
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45 // |
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46 // Author(s): msalter |
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47 // Contributors: msalter |
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48 // Date: 2002-12-10 |
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49 // Purpose: Intel XScale IXPD specific support routines |
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50 // Description: |
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51 // Usage: #include <cyg/hal/hal_platform_setup.h> |
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52 // Only used by "vectors.S" |
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53 // |
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54 //####DESCRIPTIONEND#### |
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55 // |
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56 //===========================================================================*/ |
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57 |
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58 #include <pkgconf/system.h> // System-wide configuration info |
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59 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration |
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60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration |
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61 #include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions |
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62 #include <cyg/hal/hal_mmu.h> // MMU definitions |
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63 #include <cyg/hal/hal_mm.h> // more MMU definitions |
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64 #include <cyg/hal/ixdp425.h> // Platform specific hardware definitions |
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65 |
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66 // ------------------------------------------------------------------------ |
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67 // Convenience macros for setting up page table |
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68 // |
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69 .macro IXP_MAP_SDRAM va, c, b, x, p |
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70 XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_SIZE>>20, \c, \b, 3, \x, \p |
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71 .endm |
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72 |
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73 .macro IXP_MAP_EXP_V n, va, sz, c, b, x, p |
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74 XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p |
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75 .endm |
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76 |
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77 .macro IXP_MAP_EXP n, sz, c, b, x, p |
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78 IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p |
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79 .endm |
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80 |
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81 .macro IXP_MAP_IO addr, sz |
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82 XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0 |
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83 .endm |
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84 |
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85 |
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86 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) |
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87 #define PLATFORM_SETUP1 _platform_setup1 |
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88 #define CYGHWR_HAL_ARM_HAS_MMU |
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89 |
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90 // ------------------------------------------------------------------------ |
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91 // Define macro used to diddle the LEDs during early initialization. |
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92 // Can use r0+r1. Argument in \x. |
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93 #define CYGHWR_LED_MACRO DISPLAY \x, r0, r1 |
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94 |
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95 // Delay a bit |
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96 .macro DELAY cycles, reg0 |
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97 ldr \reg0, =\cycles |
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98 subs \reg0, \reg0, #1 |
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99 subne pc, pc, #0xc |
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100 .endm |
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101 |
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102 // ------------------------------------------------------------------------ |
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103 // This macro represents the initial startup code for the platform |
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104 .macro _platform_setup1 |
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105 |
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106 #ifdef CYGHWR_HAL_ARM_BIGENDIAN |
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107 // set big-endian |
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108 mrc p15, 0, r0, c1, c0, 0 |
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109 orr r0, r0, #0x80 |
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110 mcr p15, 0, r0, c1, c0, 0 |
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111 CPWAIT r0 |
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112 #endif |
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113 |
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114 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) |
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115 msr cpsr, r0 |
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116 |
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117 // invalidate I & D caches & BTB |
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118 mcr p15, 0, r0, c7, c7, 0 |
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119 CPWAIT r0 |
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120 |
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121 // invalidate I & Data TLB |
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122 mcr p15, 0, r0, c8, c7, 0 |
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123 CPWAIT r0 |
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124 |
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125 // drain write and fill buffers |
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126 mcr p15, 0, r0, c7, c10, 4 |
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127 CPWAIT r0 |
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128 |
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129 // disable write buffer coalescing |
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130 mrc p15, 0, r0, c1, c0, 1 |
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131 orr r0, r0, #1 |
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132 mcr p15, 0, r0, c1, c0, 1 |
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133 CPWAIT r0 |
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134 |
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135 // Setup chip selects |
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136 ldr r1, =IXP425_EXP_CFG_BASE |
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137 #ifdef IXP425_EXP_CS0_INIT |
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138 ldr r0, =IXP425_EXP_CS0_INIT |
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139 str r0, [r1, #IXP425_EXP_CS0] |
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140 #endif |
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141 #ifdef IXP425_EXP_CS1_INIT |
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142 ldr r0, =IXP425_EXP_CS1_INIT |
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143 str r0, [r1, #IXP425_EXP_CS1] |
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144 #endif |
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145 #ifdef IXP425_EXP_CS2_INIT |
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146 ldr r0, =IXP425_EXP_CS2_INIT |
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147 str r0, [r1, #IXP425_EXP_CS2] |
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148 #endif |
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149 #ifdef IXP425_EXP_CS3_INIT |
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150 ldr r0, =IXP425_EXP_CS3_INIT |
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151 str r0, [r1, #IXP425_EXP_CS3] |
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152 #endif |
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153 #ifdef IXP425_EXP_CS4_INIT |
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154 ldr r0, =IXP425_EXP_CS4_INIT |
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155 str r0, [r1, #IXP425_EXP_CS4] |
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156 #endif |
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157 #ifdef IXP425_EXP_CS5_INIT |
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158 ldr r0, =IXP425_EXP_CS5_INIT |
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159 str r0, [r1, #IXP425_EXP_CS5] |
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160 #endif |
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161 #ifdef IXP425_EXP_CS6_INIT |
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162 ldr r0, =IXP425_EXP_CS6_INIT |
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163 str r0, [r1, #IXP425_EXP_CS6] |
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164 #endif |
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165 #ifdef IXP425_EXP_CS7_INIT |
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166 ldr r0, =IXP425_EXP_CS7_INIT |
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167 str r0, [r1, #IXP425_EXP_CS7] |
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168 #endif |
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169 |
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170 DISPLAY 0x1001, r7, r8 |
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171 |
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172 // Enable the Icache |
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173 mrc p15, 0, r0, c1, c0, 0 |
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174 orr r0, r0, #MMU_Control_I |
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175 mcr p15, 0, r0, c1, c0, 0 |
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176 CPWAIT r0 |
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177 |
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178 DISPLAY 0x1002, r7, r8 |
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179 |
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180 // Setup SDRAM controller |
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181 |
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182 ldr r0, =IXP425_SDRAM_CFG_BASE |
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183 |
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184 ldr r1, =IXP425_SDRAM_CONFIG_INIT |
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185 str r1, [r0, #IXP425_SDRAM_CONFIG] |
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186 |
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187 // disable refresh cycles |
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188 mov r1, #0 |
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189 str r1, [r0, #IXP425_SDRAM_REFRESH] |
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190 |
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191 // send nop command |
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192 mov r1, #SDRAM_IR_NOP |
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193 str r1, [r0, #IXP425_SDRAM_IR] |
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194 DELAY 0x10000, r1 |
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195 |
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196 // set SDRAM internal refresh val |
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197 ldr r1, =IXP425_SDRAM_REFRESH_CNT |
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198 str r1, [r0, #IXP425_SDRAM_REFRESH] |
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199 DELAY 0x10000, r1 |
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200 |
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201 // send precharge-all command to close all open banks |
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202 mov r1, #SDRAM_IR_PRECHARGE |
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203 str r1, [r0, #IXP425_SDRAM_IR] |
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204 DELAY 0x10000, r1 |
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205 |
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206 // provide 8 auto-refresh cycles |
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207 mov r1, #SDRAM_IR_AUTO_REFRESH |
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208 mov r2, #8 |
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209 1: |
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210 str r1, [r0, #IXP425_SDRAM_IR] |
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211 DELAY 0x800, r3 |
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212 subs r2, r2, #1 |
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213 bne 1b |
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214 |
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215 // set mode register in sdram |
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216 mov r1, #IXP425_SDRAM_SET_MODE_CMD |
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217 str r1, [r0, #IXP425_SDRAM_IR] |
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218 DELAY 0x10000, r1 |
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219 |
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220 // start normal operation |
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221 mov r1, #SDRAM_IR_NORMAL |
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222 str r1, [r0, #IXP425_SDRAM_IR] |
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223 DELAY 0x10000, r1 |
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224 |
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225 DISPLAY 0x1003, r7, r8 |
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226 |
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227 // Enable byte swapping control via page table P bit. |
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228 ldr r2, =IXP425_EXP_CFG_BASE |
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229 ldr r1, [r2, #IXP425_EXP_CNFG1] |
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230 orr r1, r1, #EXP_CNFG1_BYTE_SWAP_EN |
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231 str r1, [r2, #IXP425_EXP_CNFG1] |
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232 |
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233 // value to load into pc to jump to real runtime address |
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234 ldr r0, =1f |
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235 #if defined(CYG_HAL_STARTUP_ROMRAM) |
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236 // R0 holds a RAM address for ROMRAM startup, |
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237 // so convert to a flash address. |
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238 orr r0, r0, #IXDP_FLASH_BASE |
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239 #endif |
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240 |
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241 // Setup EXP_CNFG0 value to switch EXP bus out of low memory |
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242 ldr r2, =IXP425_EXP_CFG_BASE |
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243 ldr r1, [r2, #IXP425_EXP_CNFG0] |
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244 bic r1, r1, #EXP_CNFG0_MEM_MAP |
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245 ldr r3, =0xFFFF |
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246 ldr r4, =IXDP425_LED_DATA |
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247 |
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248 |
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249 b icache_boundary |
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250 .p2align 5 |
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251 icache_boundary: |
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252 // Here is where we switch from boot address (0x000000000) to the |
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253 // actual flash runtime address. We align to cache boundary so we |
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254 // execute from cache during the switchover. Cachelines are 8 words. |
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255 str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch |
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256 nop |
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257 nop |
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258 nop |
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259 nop |
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260 mov pc, r0 |
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261 strh r3, [r4] // We should never reach this point. If we do, |
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262 // display FFFF and loop forever. |
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263 0: b 0b |
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264 1: |
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265 |
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266 DISPLAY 0x1004, r7, r8 |
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267 |
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268 #if defined(CYG_HAL_STARTUP_ROMRAM) |
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269 mov r0, #IXDP_FLASH_BASE |
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270 mov r1, #SDRAM_PHYS_BASE |
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271 ldr r2, =__ram_data_end |
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272 20: ldr r3, [r0],#4 |
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273 str r3, [r1],#4 |
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274 cmp r1, r2 |
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275 bne 20b |
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276 |
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277 // start executing from RAM |
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278 ldr r0, =30f |
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279 mov pc, r0 |
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280 30: |
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281 #endif |
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282 |
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283 // Build mmu tables into RAM so page table walks by the cpu |
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284 // don't interfere with FLASH programming. |
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285 mov r1, #SDRAM_PHYS_BASE |
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286 orr r1, r1, #0x4000 // RAM tables |
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287 add r2, r1, #0x4000 // End of tables |
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288 |
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289 // First clear table |
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290 mov r0, #0 |
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291 1: |
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292 str r0, [r1], #4 |
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293 cmp r1, r2 |
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294 bne 1b |
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295 |
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296 // Build section mappings |
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297 IXP_MAP_SDRAM SDRAM_BASE, 1, 0, 0, 0 // Cached SDRAM |
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298 IXP_MAP_SDRAM SDRAM_ALIAS_BASE, 1, 0, 0, 0 // Cached SDRAM alias |
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299 IXP_MAP_SDRAM SDRAM_UNCACHED_BASE, 0, 0, 0, 0 // Uncached SDRAM |
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300 IXP_MAP_SDRAM SDRAM_DC_BASE, 1, 0, 0, 1 // Cached data coherent SDRAM |
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301 |
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302 IXP_MAP_EXP 0, IXDP_FLASH_SIZE, 1, 0, 0, 0 // Flash |
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303 IXP_MAP_EXP 2, IXDP425_LED_SIZE, 0, 0, 0, 0 // LED |
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304 IXP_MAP_EXP 4, (1 << 20), 0, 0, 0, 0 // NPE use |
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305 IXP_MAP_EXP 5, (1 << 20), 0, 0, 0, 0 // NPE use |
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306 |
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307 IXP_MAP_EXP_V 0, IXDP_FLASH_DC_BASE, IXDP_FLASH_SIZE, 1, 0, 0, 1 // data coherent flash |
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308 |
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309 IXP_MAP_IO IXP425_PCI_WINDOW_BASE, IXP425_PCI_WINDOW_SIZE |
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310 IXP_MAP_IO IXP425_QMGR_BASE, IXP425_QMGR_SIZE |
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311 IXP_MAP_IO IXP425_PCI_CFG_BASE, IXP425_PCI_CFG_SIZE |
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312 IXP_MAP_IO IXP425_EXP_CFG_BASE, IXP425_EXP_CFG_SIZE |
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313 IXP_MAP_IO IXP425_MISC_CFG_BASE, IXP425_MISC_CFG_SIZE |
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314 IXP_MAP_IO IXP425_SDRAM_CFG_BASE, IXP425_SDRAM_CFG_SIZE |
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315 |
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316 DISPLAY 0x1005, r7, r8 |
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317 |
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318 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers |
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319 CPWAIT r0 |
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320 |
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321 // Set the TTB register to DRAM mmu_table |
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322 ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables |
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323 mcr p15, 0, r0, c2, c0, 0 // load page table pointer |
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324 CPWAIT r0 |
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325 |
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326 // enable permission checks in all domains |
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327 ldr r0, =0x55555555 |
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328 mcr p15, 0, r0, c3, c0, 0 |
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329 CPWAIT r0 |
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330 |
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331 DISPLAY 0x1006, r7, r8 |
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332 |
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333 // enable mmu |
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334 mrc p15, 0, r0, c1, c0, 0 |
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335 orr r0, r0, #MMU_Control_M |
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336 orr r0, r0, #MMU_Control_R |
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337 mcr p15, 0, r0, c1, c0, 0 |
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338 CPWAIT r0 |
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339 |
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340 DISPLAY 0x1007, r7, r8 |
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341 |
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342 // enable D cache |
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343 mrc p15, 0, r0, c1, c0, 0 |
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344 orr r0, r0, #MMU_Control_C |
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345 mcr p15, 0, r0, c1, c0, 0 |
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346 CPWAIT r0 |
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347 |
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348 DISPLAY 0x1008, r7, r8 |
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349 |
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350 // Enable branch target buffer |
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351 mrc p15, 0, r0, c1, c0, 0 |
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352 orr r0, r0, #MMU_Control_BTB |
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353 mcr p15, 0, r0, c1, c0, 0 |
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354 CPWAIT r0 |
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355 |
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356 DISPLAY 0x1009, r7, r8 |
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357 |
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358 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers |
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359 CPWAIT r0 |
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360 |
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361 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB |
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362 CPWAIT r0 |
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363 |
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364 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs |
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365 CPWAIT r0 |
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366 |
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367 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers |
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368 CPWAIT r0 |
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369 |
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370 DISPLAY 0x100A, r7, r8 |
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371 |
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372 // save SDRAM size |
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373 ldr r1, =hal_dram_size /* [see hal_intr.h] */ |
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374 mov r8, #SDRAM_SIZE |
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375 str r8, [r1] |
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376 |
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377 DISPLAY 0x100B, r7, r8 |
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378 |
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379 .endm // _platform_setup1 |
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380 |
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381 #else // defined(CYG_HAL_STARTUP_ROM) |
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382 #define PLATFORM_SETUP1 |
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383 #endif |
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384 |
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385 #define PLATFORM_VECTORS _platform_vectors |
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386 .macro _platform_vectors |
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387 .endm |
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388 |
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389 /*---------------------------------------------------------------------------*/ |
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390 /* end of hal_platform_setup.h */ |
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391 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */ |
