Mercurial > nand-ecoscentric
annotate packages/hal/arm/arch/current/src/arm_stub.c @ 38:e7ba79f6d3a8 ecos-sw-1999-09-23
Merge from eCos master repository on 1999-09-23-20:10:25-BST
| author | jlarmour |
|---|---|
| date | Thu, 23 Sep 1999 19:52:27 +0000 |
| parents | e97d78785e2d |
| children | 797268ecc331 |
| rev | line source |
|---|---|
| 2 | 1 /* arm_stub.c - helper functions for stub, generic to all ARM processors |
| 2 * | |
| 3 * Copyright (c) 1998,1999 Cygnus Solutions | |
| 4 * | |
| 5 * The authors hereby grant permission to use, copy, modify, distribute, | |
| 6 * and license this software and its documentation for any purpose, provided | |
| 7 * that existing copyright notices are retained in all copies and that this | |
| 8 * notice is included verbatim in any distributions. No written agreement, | |
| 9 * license, or royalty fee is required for any of the authorized uses. | |
| 10 * Modifications to this software may be copyrighted by their authors | |
| 11 * and need not follow the licensing terms described here, provided that | |
| 12 * the new terms are clearly indicated on the first page of each file where | |
| 13 * they apply. | |
| 14 */ | |
| 15 | |
| 16 #include <stddef.h> | |
| 17 | |
| 18 #include <pkgconf/hal.h> | |
| 19 | |
| 20 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 21 | |
| 22 #ifdef CYG_HAL_ARM_SIM | |
| 23 #error "GDB Stub support not implemented for ARM SIM" | |
| 24 #endif | |
| 25 | |
| 26 #include <cyg/hal/hal_stub.h> | |
| 27 #include <cyg/hal/hal_arch.h> | |
| 28 #include <cyg/hal/hal_intr.h> | |
| 29 | |
| 30 #ifndef FALSE | |
| 31 #define FALSE 0 | |
| 32 #define TRUE 1 | |
| 33 #endif | |
| 34 | |
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35 |
| 2 | 36 #ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT |
| 37 #include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id | |
| 38 #endif | |
| 39 | |
| 40 /* Given a trap value TRAP, return the corresponding signal. */ | |
| 41 | |
| 42 int __computeSignal (unsigned int trap_number) | |
| 43 { | |
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44 // should also catch CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION here but we |
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45 // can't tell the different between a real one and a breakpoint :-( |
| 2 | 46 switch (trap_number) { |
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47 case CYGNUM_HAL_VECTOR_ABORT_PREFETCH: // Fall through |
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48 case CYGNUM_HAL_VECTOR_ABORT_DATA: // Fall through |
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49 case CYGNUM_HAL_VECTOR_reserved: |
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50 return SIGBUS; |
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51 case CYGNUM_HAL_VECTOR_IRQ: |
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52 case CYGNUM_HAL_VECTOR_FIQ: |
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53 return SIGINT; |
| 2 | 54 default: |
| 55 return SIGTRAP; | |
| 56 } | |
| 57 } | |
| 58 | |
| 59 | |
| 60 /* Return the trap number corresponding to the last-taken trap. */ | |
| 61 int __get_trap_number (void) | |
| 62 { | |
| 63 // The vector is not not part of the GDB register set so get it | |
| 64 // directly from the save context. | |
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65 return _hal_registers->vector; |
| 2 | 66 } |
| 67 | |
| 68 /* Set the currently-saved pc register value to PC. This also updates NPC | |
| 69 as needed. */ | |
| 70 | |
| 71 void set_pc (target_register_t pc) | |
| 72 { | |
| 73 put_register (PC, pc); | |
| 74 } | |
| 75 | |
| 76 | |
| 77 /*---------------------------------------------------------------------- | |
| 78 * Single-step support | |
| 79 */ | |
| 80 | |
| 81 /* Set things up so that the next user resume will execute one instruction. | |
| 82 This may be done by setting breakpoints or setting a single step flag | |
| 83 in the saved user registers, for example. */ | |
| 84 | |
| 85 #define NULL_PTR (unsigned long *)0 | |
| 86 static unsigned long *ss_saved_pc = NULL_PTR; | |
| 87 static unsigned long ss_saved_instr; | |
| 88 | |
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89 |
| 2 | 90 #define FIXME() {diag_printf("FIXME - %s\n", __FUNCTION__); } |
| 91 | |
| 92 static int | |
| 93 ins_will_execute(unsigned long ins) | |
| 94 { | |
| 95 unsigned long psr = get_register(PS); // condition codes | |
| 96 int res = 0; | |
| 97 switch ((ins & 0xF0000000) >> 28) { | |
| 98 case 0x0: // EQ | |
| 99 res = (psr & PS_Z) != 0; | |
| 100 break; | |
| 101 case 0x1: // NE | |
| 102 res = (psr & PS_Z) == 0; | |
| 103 break; | |
| 104 case 0x2: // CS | |
| 105 res = (psr & PS_C) != 0; | |
| 106 break; | |
| 107 case 0x3: // CC | |
| 108 res = (psr & PS_C) == 0; | |
| 109 break; | |
| 110 case 0x4: // MI | |
| 111 res = (psr & PS_N) != 0; | |
| 112 break; | |
| 113 case 0x5: // PL | |
| 114 res = (psr & PS_N) == 0; | |
| 115 break; | |
| 116 case 0x6: // VS | |
| 117 res = (psr & PS_V) != 0; | |
| 118 break; | |
| 119 case 0x7: // VC | |
| 120 res = (psr & PS_V) == 0; | |
| 121 break; | |
| 122 case 0x8: // HI | |
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123 res = ((psr & PS_C) != 0) && ((psr & PS_Z) == 0); |
| 2 | 124 break; |
| 125 case 0x9: // LS | |
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126 res = ((psr & PS_C) == 0) || ((psr & PS_Z) != 0); |
| 2 | 127 break; |
| 128 case 0xA: // GE | |
| 129 res = ((psr & (PS_N|PS_V)) == (PS_N|PS_V)) || | |
| 130 ((psr & (PS_N|PS_V)) == 0); | |
| 131 break; | |
| 132 case 0xB: // LT | |
| 133 res = ((psr & (PS_N|PS_V)) == PS_N) || | |
| 134 ((psr & (PS_N|PS_V)) == PS_V); | |
| 135 break; | |
| 136 case 0xC: // GT | |
| 137 res = ((psr & (PS_N|PS_V)) == (PS_N|PS_V)) || | |
| 138 ((psr & (PS_N|PS_V)) == 0); | |
| 139 res = ((psr & PS_Z) == 0) && res; | |
| 140 break; | |
| 141 case 0xD: // LE | |
| 142 res = ((psr & (PS_N|PS_V)) == PS_N) || | |
| 143 ((psr & (PS_N|PS_V)) == PS_V); | |
| 144 res = ((psr & PS_Z) == PS_Z) || res; | |
| 145 break; | |
| 146 case 0xE: // AL | |
| 147 res = TRUE; | |
| 148 break; | |
| 149 case 0xF: // NV | |
| 150 res = FALSE; | |
| 151 break; | |
| 152 } | |
| 153 return res; | |
| 154 } | |
| 155 | |
| 156 static unsigned long | |
| 157 RmShifted(int shift) | |
| 158 { | |
| 159 unsigned long Rm = get_register(shift & 0x00F); | |
| 160 int shift_count; | |
| 161 if ((shift & 0x010) == 0) { | |
| 162 shift_count = (shift & 0xF80) >> 7; | |
| 163 } else { | |
| 164 shift_count = get_register((shift & 0xF00) >> 8); | |
| 165 } | |
| 166 switch ((shift & 0x060) >> 5) { | |
| 167 case 0x0: // Logical left | |
| 168 Rm <<= shift_count; | |
| 169 break; | |
| 170 case 0x1: // Logical right | |
| 171 Rm >>= shift_count; | |
| 172 break; | |
| 173 case 0x2: // Arithmetic right | |
| 174 Rm = (unsigned long)((long)Rm >> shift_count); | |
| 175 break; | |
| 176 case 0x3: // Rotate right | |
| 177 if (shift_count == 0) { | |
| 178 // Special case, RORx | |
| 179 Rm >>= 1; | |
| 180 if (get_register(PS) & PS_C) Rm |= 0x80000000; | |
| 181 } else { | |
| 182 Rm = (Rm >> shift_count) | (Rm << (32-shift_count)); | |
| 183 } | |
| 184 break; | |
| 185 } | |
| 186 return Rm; | |
| 187 } | |
| 188 | |
| 189 // Decide the next instruction to be executed for a given instruction | |
| 190 static unsigned long * | |
| 191 target_ins(unsigned long *pc, unsigned long ins) | |
| 192 { | |
| 193 unsigned long new_pc, offset, op2; | |
| 194 unsigned long Rn; | |
| 195 int i, reg_count, c; | |
| 196 switch ((ins & 0x0C000000) >> 26) { | |
| 197 case 0x0: | |
| 198 // Data processing | |
| 199 new_pc = (unsigned long)(pc+1); | |
| 200 if ((ins & 0x0000F000) == 0x0000F000) { | |
| 201 // Destination register is PC | |
| 202 if ((ins & 0x0FBF0000) != 0x010F0000) { | |
| 203 Rn = (unsigned long)get_register((ins & 0x000F0000) >> 16); | |
| 204 if ((ins & 0x02000000) == 0) { | |
| 205 op2 = RmShifted(ins & 0x00000FFF); | |
| 206 } else { | |
| 207 op2 = ins & 0x000000FF; | |
| 208 i = (ins & 0x00000F00) >> 8; // Rotate count | |
| 209 op2 = (op2 >> (i*2)) | (op2 << (32-(i*2))); | |
| 210 } | |
| 211 switch ((ins & 0x01E00000) >> 21) { | |
| 212 case 0x0: // AND | |
| 213 new_pc = Rn & op2; | |
| 214 break; | |
| 215 case 0x1: // EOR | |
| 216 new_pc = Rn ^ op2; | |
| 217 break; | |
| 218 case 0x2: // SUB | |
| 219 new_pc = Rn - op2; | |
| 220 break; | |
| 221 case 0x3: // RSB | |
| 222 new_pc = op2 - Rn; | |
| 223 break; | |
| 224 case 0x4: // ADD | |
| 225 new_pc = Rn + op2; | |
| 226 break; | |
| 227 case 0x5: // ADC | |
| 228 c = (get_register(PS) & PS_C) != 0; | |
| 229 new_pc = Rn + op2 + c; | |
| 230 break; | |
| 231 case 0x6: // SBC | |
| 232 c = (get_register(PS) & PS_C) != 0; | |
| 233 new_pc = Rn - op2 + c - 1; | |
| 234 break; | |
| 235 case 0x7: // RSC | |
| 236 c = (get_register(PS) & PS_C) != 0; | |
| 237 new_pc = op2 - Rn +c - 1; | |
| 238 break; | |
| 239 case 0x8: // TST | |
| 240 case 0x9: // TEQ | |
| 241 case 0xA: // CMP | |
| 242 case 0xB: // CMN | |
| 243 break; // PC doesn't change | |
| 244 case 0xC: // ORR | |
| 245 new_pc = Rn | op2; | |
| 246 break; | |
| 247 case 0xD: // MOV | |
| 248 new_pc = op2; | |
| 249 break; | |
| 250 case 0xE: // BIC | |
| 251 new_pc = Rn & ~op2; | |
| 252 break; | |
| 253 case 0xF: // MVN | |
| 254 new_pc = ~op2; | |
| 255 break; | |
| 256 } | |
| 257 } | |
| 258 } | |
| 259 return ((unsigned long *)new_pc); | |
| 260 case 0x1: | |
| 261 if ((ins & 0x02000010) == 0x02000010) { | |
| 262 // Undefined! | |
| 263 return (pc+1); | |
| 264 } else { | |
| 265 if ((ins & 0x00100000) == 0) { | |
| 266 // STR | |
| 267 return (pc+1); | |
| 268 } else { | |
| 269 // LDR | |
| 270 if ((ins & 0x0000F000) != 0x0000F000) { | |
| 271 // Rd not PC | |
| 272 return (pc+1); | |
| 273 } else { | |
| 274 Rn = (unsigned long)get_register((ins & 0x000F0000) >> 16); | |
| 275 if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch! | |
| 276 if (ins & 0x01000000) { | |
| 277 // Add/subtract offset before | |
| 278 if ((ins & 0x02000000) == 0) { | |
| 279 // Immediate offset | |
| 280 if (ins & 0x00800000) { | |
| 281 // Add offset | |
| 282 Rn += (ins & 0x00000FFF); | |
| 283 } else { | |
| 284 // Subtract offset | |
| 285 Rn -= (ins & 0x00000FFF); | |
| 286 } | |
| 287 } else { | |
| 288 // Offset is in a register | |
| 289 if (ins & 0x00800000) { | |
| 290 // Add offset | |
| 291 Rn += RmShifted(ins & 0x00000FFF); | |
| 292 } else { | |
| 293 // Subtract offset | |
| 294 Rn -= RmShifted(ins & 0x00000FFF); | |
| 295 } | |
| 296 } | |
| 297 } | |
| 298 return ((unsigned long *)*(unsigned long *)Rn); | |
| 299 } | |
| 300 } | |
| 301 } | |
| 302 return (pc+1); | |
| 303 case 0x2: // Branch, LDM/STM | |
| 304 if ((ins & 0x02000000) == 0) { | |
| 305 // LDM/STM | |
| 306 if ((ins & 0x00100000) == 0) { | |
| 307 // STM | |
| 308 return (pc+1); | |
| 309 } else { | |
| 310 // LDM | |
| 311 if ((ins & 0x00008000) == 0) { | |
| 312 // PC not in list | |
| 313 return (pc+1); | |
| 314 } else { | |
| 315 Rn = (unsigned long)get_register((ins & 0x000F0000) >> 16); | |
| 316 if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch! | |
| 317 offset = ins & 0x0000FFFF; | |
| 318 reg_count = 0; | |
| 319 for (i = 0; i < 15; i++) { | |
| 320 if (offset & (1<<i)) reg_count++; | |
| 321 } | |
| 322 if (ins & 0x00800000) { | |
| 323 // Add offset | |
| 324 Rn += reg_count*4; | |
| 325 } else { | |
| 326 // Subtract offset | |
| 327 Rn -= 4; | |
| 328 } | |
| 329 return ((unsigned long *)*(unsigned long *)Rn); | |
| 330 } | |
| 331 } | |
| 332 } else { | |
| 333 // Branch | |
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334 if (ins_will_execute(ins)) { |
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335 offset = (ins & 0x00FFFFFF) << 2; |
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336 if (ins & 0x00800000) offset |= 0xFC000000; // sign extend |
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337 new_pc = (unsigned long)(pc+2) + offset; |
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338 return ((unsigned long *)new_pc); |
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339 } else { |
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340 // Falls through |
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341 return (pc+1); |
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342 } |
| 2 | 343 } |
| 344 case 0x3: // Coprocessor & SWI | |
| 345 return (pc+1); | |
| 346 } | |
| 347 } | |
| 348 | |
| 349 void __single_step (void) | |
| 350 { | |
| 351 unsigned long *pc = (unsigned long *)get_register(PC); | |
| 352 unsigned long curins = *pc; | |
| 353 if (ins_will_execute(curins)) { | |
| 354 // Decode instruction to decide what the next PC will be | |
| 355 ss_saved_pc = target_ins(pc, curins); | |
| 356 } else { | |
| 357 // The current instruction will not execute (the conditions don't hold) | |
| 358 ss_saved_pc = (pc+1); | |
| 359 } | |
| 360 // For now | |
| 361 ss_saved_instr = *ss_saved_pc; | |
| 362 *ss_saved_pc = 0xE7FFDEFF; // As used by ARM | |
| 363 } | |
| 364 | |
| 365 /* Clear the single-step state. */ | |
| 366 | |
| 367 void __clear_single_step (void) | |
| 368 { | |
| 369 if (ss_saved_pc != NULL_PTR) { | |
| 370 *ss_saved_pc = ss_saved_instr; | |
| 371 ss_saved_pc = NULL_PTR; | |
| 372 } | |
| 373 } | |
| 374 | |
| 375 void __install_breakpoints (void) | |
| 376 { | |
| 377 // FIXME(); | |
| 378 } | |
| 379 | |
| 380 void __clear_breakpoints (void) | |
| 381 { | |
| 382 // FIXME(); | |
| 383 } | |
| 384 | |
| 385 /* If the breakpoint we hit is in the breakpoint() instruction, return a | |
| 386 non-zero value. */ | |
| 387 | |
| 388 int | |
| 389 __is_breakpoint_function () | |
| 390 { | |
| 391 return get_register (PC) == (target_register_t)&CYG_LABEL_NAME(breakinst); | |
| 392 } | |
| 393 | |
| 394 | |
| 395 /* Skip the current instruction. Since this is only called by the | |
| 396 stub when the PC points to a breakpoint or trap instruction, | |
| 397 we can safely just skip 4. */ | |
| 398 | |
| 399 void __skipinst (void) | |
| 400 { | |
| 401 put_register (PC, get_register (PC) + 4); | |
| 402 } | |
| 403 | |
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404 |
| 2 | 405 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |