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annotate packages/hal/arm/aeb/current/include/hal_cache.h @ 3403:8c8767bb9a62 default tip
devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.
| author | Ross Younger <wry@ecoscentric.com> |
|---|---|
| date | Sun, 18 Jan 2015 17:59:01 +1300 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
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| 2 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
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11 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later |
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19 // version. |
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20 // |
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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24 // for more details. |
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25 // |
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26 // You should have received a copy of the GNU General Public License |
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27 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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29 // |
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30 // As a special exception, if other files instantiate templates or use |
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31 // macros or inline functions from this file, or you compile this file |
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32 // and link it with other works to produce a work based on this file, |
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33 // this file does not by itself cause the resulting work to be covered by |
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34 // the GNU General Public License. However the source code for this file |
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35 // must still be made available in accordance with section (3) of the GNU |
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36 // General Public License v2. |
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37 // |
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38 // This exception does not invalidate any other reasons why a work based |
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39 // on this file might be covered by the GNU General Public License. |
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40 // ------------------------------------------- |
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41 // ####ECOSGPLCOPYRIGHTEND#### |
| 2 | 42 //============================================================================= |
| 43 //#####DESCRIPTIONBEGIN#### | |
| 44 // | |
| 45 // Author(s): nickg, gthomas | |
| 46 // Contributors: nickg, gthomas | |
| 47 // Date: 1998-09-28 | |
| 48 // Purpose: Cache control API | |
| 49 // Description: The macros defined here provide the HAL APIs for handling | |
| 50 // cache control operations. | |
| 51 // Usage: | |
| 52 // #include <cyg/hal/hal_cache.h> | |
| 53 // ... | |
| 54 // | |
| 55 // | |
| 56 //####DESCRIPTIONEND#### | |
| 57 // | |
| 58 //============================================================================= | |
| 59 | |
| 60 #include <cyg/infra/cyg_type.h> | |
| 61 #include <cyg/hal/hal_io.h> | |
| 62 | |
| 63 //----------------------------------------------------------------------------- | |
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64 // Cache dimensions - one unified cache |
| 2 | 65 |
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66 #define HAL_CACHE_UNIFIED |
| 2 | 67 |
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68 #define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes |
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69 #define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line |
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70 #define HAL_UCACHE_WAYS 4 // Associativity of the cache |
| 2 | 71 |
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72 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) |
| 2 | 73 |
| 74 // Cache & SRAM control | |
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75 #define CYG_DEVICE_CCR 0xFFFFA400 |
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76 #define CYG_DEVICE_LSCR 0xFFFFA404 |
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77 #define CYG_DEVICE_CACHE_MEM 0x60000800 |
| 2 | 78 |
| 79 #define CCR_E 0x01 // Cache enabled | |
| 80 #define CCR_S 0x02 // SRAM mode enabled | |
| 81 #define CCR_F 0x04 // Flush mode enabled | |
| 82 #define CCR_I 0x08 // Invalidate mode | |
| 83 | |
| 84 #define LCSR_E 0x01 // Local SRAM enabled | |
| 85 #define LCSR_L 0x02 // Local SRAM mapped to high memory | |
| 86 | |
| 87 //----------------------------------------------------------------------------- | |
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88 // Global control of cache |
| 2 | 89 |
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90 // Enable the cache |
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91 #define HAL_UCACHE_ENABLE() \ |
| 2 | 92 { \ |
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93 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \ |
| 2 | 94 } |
| 95 | |
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96 // Disable the cache |
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97 #define HAL_UCACHE_DISABLE() \ |
| 2 | 98 { \ |
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99 HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \ |
| 2 | 100 } |
| 101 | |
| 102 // Invalidate the entire cache | |
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103 #define HAL_UCACHE_INVALIDATE_ALL() \ |
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104 { \ |
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105 register cyg_uint8 old_ccr; \ |
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106 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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107 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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108 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
| 2 | 109 } |
| 110 | |
| 111 // Synchronize the contents of the cache with memory. | |
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112 #define HAL_UCACHE_SYNC() \ |
| 2 | 113 { \ |
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114 register volatile cyg_uint32 *cache_SRAM = \ |
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115 (volatile cyg_uint32*) CYG_DEVICE_CACHE_MEM; \ |
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116 register int i; \ |
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117 register cyg_uint8 old_ccr; \ |
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118 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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119 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \ |
| 2 | 120 for (i = 0; i < HAL_DCACHE_SETS; i++) { \ |
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121 cyg_uint32 tmp = *cache_SRAM++; \ |
| 2 | 122 } \ |
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123 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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124 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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125 } |
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126 |
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127 // Query the state of the cache |
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128 #define HAL_UCACHE_IS_ENABLED(_state_) \ |
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129 { \ |
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130 cyg_uint8 __ccr; \ |
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131 HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \ |
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132 (_state_) = (CCR_E == __ccr) ? 1 : 0; \ |
| 2 | 133 } |
| 134 | |
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135 // Purge contents of cache |
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136 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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137 |
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138 // Set the cache refill burst size |
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139 //#define HAL_UCACHE_BURST_SIZE(_size_) |
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140 |
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141 // Set the cache write mode |
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142 //#define HAL_UCACHE_WRITE_MODE( _mode_ ) |
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143 |
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144 //#define HAL_UCACHE_WRITETHRU_MODE 0 |
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145 //#define HAL_UCACHE_WRITEBACK_MODE 1 |
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146 |
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147 // Load the contents of the given address range into the cache |
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148 // and then lock the cache so that it stays there. |
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149 //#define HAL_UCACHE_LOCK(_base_, _size_) |
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150 |
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151 // Undo a previous lock operation |
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152 //#define HAL_UCACHE_UNLOCK(_base_, _size_) |
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153 |
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154 // Unlock entire cache |
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155 //#define HAL_UCACHE_UNLOCK_ALL() |
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156 |
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157 //----------------------------------------------------------------------------- |
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158 // Cache line control |
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159 |
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160 // Allocate cache lines for the given address range without reading its |
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161 // contents from memory. |
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162 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) |
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163 |
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164 // Write dirty cache lines to memory and invalidate the cache entries |
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165 // for the given address range. |
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166 //#define HAL_UCACHE_FLUSH( _base_ , _size_ ) |
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167 |
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168 // Invalidate cache lines in the given range without writing to memory. |
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169 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) |
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170 |
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171 // Write dirty cache lines to memory for the given address range. |
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172 //#define HAL_UCACHE_STORE( _base_ , _size_ ) |
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173 |
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174 // Preread the given range into the cache with the intention of reading |
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175 // from it later. |
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176 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) |
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177 |
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178 // Preread the given range into the cache with the intention of writing |
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179 // to it later. |
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180 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) |
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181 |
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182 // Allocate and zero the cache lines associated with the given range. |
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183 //#define HAL_UCACHE_ZERO( _base_ , _size_ ) |
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184 |
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185 //----------------------------------------------------------------------------- |
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186 |
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187 //----------------------------------------------------------------------------- |
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188 // Data and instruction cache macros map onto the both-cache macros |
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189 |
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190 //----------------------------------------------------------------------------- |
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191 // Global control of data cache |
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192 |
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193 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE |
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194 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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195 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS |
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196 #define HAL_DCACHE_SETS HAL_UCACHE_SETS |
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197 |
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198 // Enable the data cache |
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199 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() |
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200 |
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201 // Disable the data cache |
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202 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() |
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203 |
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204 // Invalidate the entire cache |
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205 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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206 |
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207 // Synchronize the contents of the cache with memory. |
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208 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() |
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209 |
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210 // Query the state of the data cache |
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211 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 212 |
| 213 // Set the data cache refill burst size | |
| 214 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 215 | |
| 216 // Set the data cache write mode | |
| 217 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 218 | |
| 219 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 220 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 221 | |
| 222 // Load the contents of the given address range into the data cache | |
| 223 // and then lock the cache so that it stays there. | |
| 224 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 225 | |
| 226 // Undo a previous lock operation | |
| 227 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 228 | |
| 229 // Unlock entire cache | |
| 230 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 231 | |
| 232 //----------------------------------------------------------------------------- | |
| 233 // Data cache line control | |
| 234 | |
| 235 // Allocate cache lines for the given address range without reading its | |
| 236 // contents from memory. | |
| 237 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 238 | |
| 239 // Write dirty cache lines to memory and invalidate the cache entries | |
| 240 // for the given address range. | |
| 241 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 242 | |
| 243 // Invalidate cache lines in the given range without writing to memory. | |
| 244 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 245 | |
| 246 // Write dirty cache lines to memory for the given address range. | |
| 247 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 248 | |
| 249 // Preread the given range into the cache with the intention of reading | |
| 250 // from it later. | |
| 251 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 252 | |
| 253 // Preread the given range into the cache with the intention of writing | |
| 254 // to it later. | |
| 255 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 256 | |
| 257 // Allocate and zero the cache lines associated with the given range. | |
| 258 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 259 | |
| 260 //----------------------------------------------------------------------------- | |
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261 // Global control of Instruction cache |
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262 |
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263 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE |
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264 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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265 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS |
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266 #define HAL_ICACHE_SETS HAL_UCACHE_SETS |
| 2 | 267 |
| 268 // Enable the instruction cache | |
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269 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() |
| 2 | 270 |
| 271 // Disable the instruction cache | |
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272 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() |
| 2 | 273 |
| 274 // Invalidate the entire cache | |
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275 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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276 |
| 2 | 277 |
| 278 // Synchronize the contents of the cache with memory. | |
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279 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() |
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280 |
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281 // Query the state of the instruction cache |
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282 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 283 |
| 284 // Set the instruction cache refill burst size | |
| 285 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 286 | |
| 287 // Load the contents of the given address range into the instruction cache | |
| 288 // and then lock the cache so that it stays there. | |
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289 |
| 2 | 290 //#define HAL_ICACHE_LOCK(_base_, _size_) |
| 291 | |
| 292 // Undo a previous lock operation | |
| 293 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 294 | |
| 295 // Unlock entire cache | |
| 296 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 297 | |
| 298 //----------------------------------------------------------------------------- | |
| 299 // Instruction cache line control | |
| 300 | |
| 301 // Invalidate cache lines in the given range without writing to memory. | |
| 302 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 303 | |
| 304 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 305 // End of hal_cache.h |
