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annotate packages/hal/arm/sa11x0/var/current/src/hal_diag.c @ 3403:8c8767bb9a62 default tip

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devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.
author Ross Younger <wry@ecoscentric.com>
date Sun, 18 Jan 2015 17:59:01 +1300
parents 74dbf4c3f2e1
children
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1 /*=============================================================================
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2 //
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3 // hal_diag.c
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4 //
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5 // HAL diagnostic output code
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6 //
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7 //=============================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //=============================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): gthomas
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43 // Contributors:nickg, gthomas, dmoseley
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44 // Travis C. Furrer <furrer@mit.edu>
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45 // Date: 2000-05-08
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46 // Purpose: HAL diagnostic output
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47 // Description: Implementations of HAL diagnostic output support.
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //===========================================================================*/
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52
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53 #include <pkgconf/hal.h>
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54 #include <pkgconf/system.h>
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55 #include CYGBLD_HAL_PLATFORM_H
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56
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57 #include <cyg/infra/cyg_type.h> // base types
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58 #include <cyg/infra/cyg_trac.h> // tracing macros
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59 #include <cyg/infra/cyg_ass.h> // assertion macros
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60
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61 #include <cyg/hal/hal_arch.h> // basic machine info
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62 #include <cyg/hal/hal_intr.h> // interrupt macros
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63 #include <cyg/hal/hal_io.h> // IO macros
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64 #include <cyg/hal/hal_if.h> // Calling interface definitions
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65 #include <cyg/hal/hal_diag.h>
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66 #include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
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67 #include <cyg/hal/hal_misc.h> // Helper functions
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68 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions
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69
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70 struct sa11x0_serial {
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71 volatile cyg_uint32 utcr0;
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72 volatile cyg_uint32 utcr1;
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73 volatile cyg_uint32 utcr2;
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74 volatile cyg_uint32 utcr3;
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75 volatile cyg_uint32 pad0010;
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76 volatile cyg_uint32 utdr;
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77 volatile cyg_uint32 pad0018;
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78 volatile cyg_uint32 utsr0;
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79 volatile cyg_uint32 utsr1;
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80 };
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81
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82 //-----------------------------------------------------------------------------
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83 typedef struct {
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84 volatile struct sa11x0_serial* base;
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85 cyg_int32 msec_timeout;
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86 int isr_vector;
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87 int baud_rate;
110
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88 } channel_data_t;
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89
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90 /*---------------------------------------------------------------------------*/
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91 // SA11x0 Serial Port (UARTx) for Debug
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92
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93 static void
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94 init_channel(channel_data_t* __ch_data)
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95 {
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96 volatile struct sa11x0_serial* base = __ch_data->base;
108
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97 cyg_uint32 brd;
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98
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99 // Disable Receiver and Transmitter (clears FIFOs)
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100 base->utcr3 = SA11X0_UART_RX_DISABLED | SA11X0_UART_TX_DISABLED;
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101
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102 // Clear sticky (writable) status bits.
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103 base->utsr0 = SA11X0_UART_RX_IDLE | SA11X0_UART_RX_BEGIN_OF_BREAK |
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104 SA11X0_UART_RX_END_OF_BREAK;
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105
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106 #if defined(CYGPKG_HAL_ARM_SA11X0_SA1100MM) || defined(CYGPKG_HAL_ARM_SA11X0_BRUTUS)
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107 // This setup is specific to only a few boards.
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108 if (SA11X0_UART1_BASE == (volatile unsigned long *)base) {
132
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109 cyg_uint32 pdr, afr, par;
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110
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111 HAL_READ_UINT32(SA11X0_GPIO_PIN_DIRECTION, pdr);
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112 HAL_READ_UINT32(SA11X0_GPIO_ALTERNATE_FUNCTION, afr);
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113 HAL_READ_UINT32(SA11X0_PPC_PIN_ASSIGNMENT, par);
108
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114
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115 //Set pin 14 as an output (Tx) and pin 15 as in input (Rx).
132
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116 HAL_WRITE_UINT32(SA11X0_GPIO_PIN_DIRECTION, ((pdr | SA11X0_GPIO_PIN_14) & ~SA11X0_GPIO_PIN_15));
108
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117
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118 // Use GPIO 14 & 15 pins for serial port 1.
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119 HAL_WRITE_UINT32(SA11X0_GPIO_ALTERNATE_FUNCTION, afr | SA11X0_GPIO_PIN_14 | SA11X0_GPIO_PIN_15);
108
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120
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121 // Pin reassignment for serial port 1.
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122 HAL_WRITE_UINT32(SA11X0_PPC_PIN_ASSIGNMENT, par | SA11X0_PPC_UART_PIN_REASSIGNMENT_MASK);
108
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123 }
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124 #endif
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125
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126 // Set UART to 8N1 (8 data bits, no partity, 1 stop bit)
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127 base->utcr0 = SA11X0_UART_PARITY_DISABLED | SA11X0_UART_STOP_BITS_1 |
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128 SA11X0_UART_DATA_BITS_8;
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129
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130 // Set the desired baud rate.
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131 brd = SA11X0_UART_BAUD_RATE_DIVISOR(__ch_data->baud_rate);
108
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132 base->utcr1 = (brd >> 8) & SA11X0_UART_H_BAUD_RATE_DIVISOR_MASK;
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133 base->utcr2 = brd & SA11X0_UART_L_BAUD_RATE_DIVISOR_MASK;
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134
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135 // Enable the receiver and the transmitter.
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136 base->utcr3 = SA11X0_UART_RX_ENABLED | SA11X0_UART_TX_ENABLED;
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137
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138 // All done
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139 }
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140
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141 void
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142 cyg_hal_plf_serial_putc(void *__ch_data, char c)
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143 {
110
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144 volatile struct sa11x0_serial* base = ((channel_data_t*)__ch_data)->base;
108
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145 CYGARC_HAL_SAVE_GP();
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146
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147 // Wait for Tx FIFO not full
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148 while ((base->utsr1 & SA11X0_UART_TX_FIFO_NOT_FULL) == 0)
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149 ;
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150 base->utdr = c;
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151
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152 CYGARC_HAL_RESTORE_GP();
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153 }
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154
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155 // FIXME: shouldn't we check for PARITY_ERROR, FRAMING_ERROR, or
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156 // RECEIVE_FIFO_OVERRUN_ERROR in the received data? This
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157 // means check the appropriate bits in UTSR1.
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158
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159 static cyg_bool
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160 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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161 {
110
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162 volatile struct sa11x0_serial* base = ((channel_data_t*)__ch_data)->base;
108
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163
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164 // If receive fifo is empty, return false
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165 if ((base->utsr1 & SA11X0_UART_RX_FIFO_NOT_EMPTY) == 0)
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166 return false;
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167
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168 *ch = (char)base->utdr;
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169
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170 // Clear receiver idle status bit, to allow another interrupt to
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171 // occur in the case where the receive fifo is almost empty.
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172 base->utsr0 = SA11X0_UART_RX_IDLE;
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173
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174 return true;
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175 }
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176
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177 cyg_uint8
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178 cyg_hal_plf_serial_getc(void* __ch_data)
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179 {
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180 cyg_uint8 ch;
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181 CYGARC_HAL_SAVE_GP();
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182
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183 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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184
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185 CYGARC_HAL_RESTORE_GP();
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186 return ch;
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187 }
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188
154
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189 static channel_data_t ser_channels[] = {
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190 #if CYGHWR_HAL_ARM_SA11X0_UART1 != 0
159
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191 { (volatile struct sa11x0_serial*)SA11X0_UART1_BASE, 1000,
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192 CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
154
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193 #endif
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194 #if CYGHWR_HAL_ARM_SA11X0_UART3 != 0
159
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195 { (volatile struct sa11x0_serial*)SA11X0_UART3_BASE, 1000,
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196 CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD },
154
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197 #endif
110
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198 };
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199
108
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200 static void
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201 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
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202 cyg_uint32 __len)
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203 {
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204 CYGARC_HAL_SAVE_GP();
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205
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206 while(__len-- > 0)
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207 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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208
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209 CYGARC_HAL_RESTORE_GP();
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210 }
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211
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212 static void
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213 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
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214 {
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215 CYGARC_HAL_SAVE_GP();
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216
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217 while(__len-- > 0)
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218 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
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219
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220 CYGARC_HAL_RESTORE_GP();
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221 }
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222
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223 cyg_bool
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224 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
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225 {
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226 int delay_count;
110
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227 channel_data_t* chan = (channel_data_t*)__ch_data;
108
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228 cyg_bool res;
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229 CYGARC_HAL_SAVE_GP();
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230
110
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231 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
108
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232
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233 for(;;) {
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234 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
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235 if (res || 0 == delay_count--)
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236 break;
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237
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238 CYGACC_CALL_IF_DELAY_US(100);
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239 }
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240
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241 CYGARC_HAL_RESTORE_GP();
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242 return res;
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243 }
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244
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245 static int
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246 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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247 {
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248 static int irq_state = 0;
110
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249 channel_data_t* chan = (channel_data_t*)__ch_data;
159
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250 int ret = -1;
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251 va_list ap;
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252
108
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253 CYGARC_HAL_SAVE_GP();
159
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254 va_start(ap, __func);
108
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255
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256 switch (__func) {
159
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257 case __COMMCTL_GETBAUD:
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258 ret = chan->baud_rate;
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259 break;
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260 case __COMMCTL_SETBAUD:
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261 chan->baud_rate = va_arg(ap, cyg_int32);
208
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262 // Should we verify this value here?
159
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263 init_channel(chan);
208
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264 ret = 0;
159
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265 break;
108
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266 case __COMMCTL_IRQ_ENABLE:
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267 irq_state = 1;
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268
110
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269 chan->base->utcr3 |= SA11X0_UART_RX_FIFO_INT_ENABLED;
108
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270
110
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271 HAL_INTERRUPT_UNMASK(chan->isr_vector);
108
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272 break;
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273 case __COMMCTL_IRQ_DISABLE:
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274 ret = irq_state;
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275 irq_state = 0;
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276
110
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277 chan->base->utcr3 &= ~SA11X0_UART_RX_FIFO_INT_ENABLED;
108
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278
110
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279 HAL_INTERRUPT_MASK(chan->isr_vector);
108
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280 break;
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281 case __COMMCTL_DBG_ISR_VECTOR:
110
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282 ret = chan->isr_vector;
108
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283 break;
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284 case __COMMCTL_SET_TIMEOUT:
110
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285 ret = chan->msec_timeout;
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286 chan->msec_timeout = va_arg(ap, cyg_uint32);
159
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287 break;
108
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288 default:
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289 break;
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290 }
159
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291 va_end(ap);
108
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292 CYGARC_HAL_RESTORE_GP();
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293 return ret;
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294 }
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295
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296 static int
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297 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
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298 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
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299 {
110
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300 int res = 0;
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301 channel_data_t* chan = (channel_data_t*)__ch_data;
108
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302 char c;
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303 int reg;
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304 CYGARC_HAL_SAVE_GP();
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305
110
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306 reg = chan->base->utsr1;
108
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307
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308 // read it anyway just in case - no harm done and we might prevent an
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309 // interrupt loop
110
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310 c = (char)chan->base->utdr;
108
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311
191
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312 // Clear receiver idle status bit, to allow another interrupt to
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313 // occur in the case where the receive fifo is almost empty.
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314 // Also for a break interrupt; these are sticky and nonmaskable.
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315 chan->base->utsr0 = (SA11X0_UART_RX_IDLE |
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316 SA11X0_UART_RX_BEGIN_OF_BREAK |
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317 SA11X0_UART_RX_END_OF_BREAK );
108
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318
110
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319 cyg_drv_interrupt_acknowledge(chan->isr_vector);
108
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320
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321 *__ctrlc = 0;
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322 if ( (reg & SA11X0_UART_RX_FIFO_NOT_EMPTY) != 0 ) {
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323 if( cyg_hal_is_break( &c , 1 ) )
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324 *__ctrlc = 1;
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325
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326 res = CYG_ISR_HANDLED;
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327 }
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328
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329 CYGARC_HAL_RESTORE_GP();
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330 return res;
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331 }
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332
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333 static void
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334 cyg_hal_plf_serial_init(void)
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335 {
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336 hal_virtual_comm_table_t* comm;
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337 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
154
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338 int i;
108
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339
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340 // Init channels
154
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341 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
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342 for (i = 0; i < NUMOF(ser_channels); i++) {
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343 init_channel(&ser_channels[i]);
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344 CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
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345 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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346 CYGACC_COMM_IF_CH_DATA_SET(*comm, &ser_channels[i]);
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347 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
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348 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
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349 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
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350 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
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351 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
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352 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
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353 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
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354 }
108
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355
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356 // Restore original console
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357 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
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358 }
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359
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360 void
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361 cyg_hal_plf_comms_init(void)
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362 {
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363 static int initialized = 0;
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364
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365 if (initialized)
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366 return;
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367
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368 initialized = 1;
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369
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370 cyg_hal_plf_serial_init();
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371 }
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372
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373 //=============================================================================
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374 // Compatibility with older stubs
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375 //=============================================================================
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376
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377 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
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378
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379 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
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380
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381 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
108
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382 # define __BASE ((void*)SA11X0_UART1_BASE)
110
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383 # define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
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384 #else
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385 # define __BASE ((void*)SA11X0_UART3_BASE)
110
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386 # define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
108
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387 #endif
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388
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389 #ifdef CYGSEM_HAL_ROM_MONITOR
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390 #define CYG_HAL_STARTUP_ROM
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391 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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392 #endif
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393
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394 #if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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395 #define HAL_DIAG_USES_HARDWARE
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396 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
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397 #define HAL_DIAG_USES_HARDWARE
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398 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
108
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399 #define HAL_DIAG_USES_HARDWARE
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400 #endif
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401
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402 static channel_data_t ser_channel = {
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403 (volatile struct sa11x0_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
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404 };
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405
108
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406 void
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407 hal_diag_init(void)
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408 {
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409 // Init serial device
110
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410 init_channel(&ser_channel);
108
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411 }
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412
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413 #ifdef HAL_DIAG_USES_HARDWARE
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414
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415 #ifdef DEBUG_DIAG
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416 #ifndef CYG_HAL_STARTUP_ROM
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417 #define DIAG_BUFSIZE 2048
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418 static char diag_buffer[DIAG_BUFSIZE];
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419 static int diag_bp = 0;
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420 #endif
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421 #endif
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422
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423 void hal_diag_read_char(char *c)
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424 {
110
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425 *c = cyg_hal_plf_serial_getc(&ser_channel);
108
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426 }
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427
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428 void hal_diag_write_char(char c)
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429 {
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430 #ifdef DEBUG_DIAG
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431 #ifndef CYG_HAL_STARTUP_ROM
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432 diag_buffer[diag_bp++] = c;
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433 if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
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434 #endif
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435 #endif
110
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436 cyg_hal_plf_serial_putc(&ser_channel, c);
108
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437 }
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438
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439 #else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
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440
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441 void
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442 hal_diag_read_char(char *c)
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443 {
110
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444 *c = cyg_hal_plf_serial_getc(&ser_channel);
108
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445 }
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446
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447 void
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448 hal_diag_write_char(char c)
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449 {
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450 static char line[100];
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451 static int pos = 0;
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452
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453 // FIXME: Some LED blinking might be nice right here.
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454
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455 // No need to send CRs
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456 if( c == '\r' ) return;
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457
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458 line[pos++] = c;
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459
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460 if( c == '\n' || pos == sizeof(line) )
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461 {
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462
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463 CYG_INTERRUPT_STATE old;
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464
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465 // Disable interrupts. This prevents GDB trying to interrupt us
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466 // while we are in the middle of sending a packet. The serial
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467 // receive interrupt will be seen when we re-enable interrupts
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468 // later.
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469
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470 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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471 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
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472 #else
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473 HAL_DISABLE_INTERRUPTS(old);
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474 #endif
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475
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476 while(1)
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477 {
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478 static char hex[] = "0123456789ABCDEF";
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479 cyg_uint8 csum = 0;
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480 int i;
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481 #ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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482 char c1;
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483 #endif
110
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484 cyg_hal_plf_serial_putc(&ser_channel, '$');
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485 cyg_hal_plf_serial_putc(&ser_channel, 'O');
108
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486 csum += 'O';
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487 for( i = 0; i < pos; i++ )
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488 {
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489 char ch = line[i];
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490 char h = hex[(ch>>4)&0xF];
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491 char l = hex[ch&0xF];
110
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492 cyg_hal_plf_serial_putc(&ser_channel, h);
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493 cyg_hal_plf_serial_putc(&ser_channel, l);
108
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494 csum += h;
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495 csum += l;
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496 }
110
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497 cyg_hal_plf_serial_putc(&ser_channel, '#');
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498 cyg_hal_plf_serial_putc(&ser_channel, hex[(csum>>4)&0xF]);
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499 cyg_hal_plf_serial_putc(&ser_channel, hex[csum&0xF]);
108
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500
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501 #ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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502
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503 break; // regardless
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504
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505 #else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
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506
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507 // Wait for the ACK character '+' from GDB here and handle
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508 // receiving a ^C instead. This is the reason for this clause
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509 // being a loop.
110
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510 c1 = cyg_hal_plf_serial_getc(&ser_channel);
108
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511
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512 if( c1 == '+' )
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513 break; // a good acknowledge
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514
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515 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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516 cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
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517 if( c1 == 3 ) {
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518 // Ctrl-C: breakpoint.
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519 cyg_hal_gdb_interrupt(
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520 (target_register_t)__builtin_return_address(0) );
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521 break;
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522 }
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523 #endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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524
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525 #endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
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526 // otherwise, loop round again
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527 }
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528
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529 pos = 0;
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530
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531
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532 // And re-enable interrupts
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533 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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534 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
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535 #else
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536 HAL_RESTORE_INTERRUPTS(old);
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537 #endif
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538
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539 }
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540 }
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541 #endif
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542
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543 #endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
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544
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545
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546 /*---------------------------------------------------------------------------*/
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547 /* End of hal_diag.c */