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devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.
author Ross Younger <wry@ecoscentric.com>
date Sun, 18 Jan 2015 17:59:01 +1300
parents 74dbf4c3f2e1
children
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1 #ifndef CYGONCE_HAL_IMP_INTR_H
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2 #define CYGONCE_HAL_IMP_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // imp_intr.h
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7 //
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8 // TX39 Interrupt and clock support
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9 //
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10 //==========================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
208
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
208
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors: nickg, jskov,
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47 // gthomas, jlarmour
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48 // Date: 1999-02-16
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49 // Purpose: TX39 Interrupt support
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // interrupts and the clock for variants of the TX39 MIPS
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52 // architecture.
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53 //
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54 // Usage:
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55 // #include <cyg/hal/imp_intr.h>
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56 // ...
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57 //
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58 //
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59 //####DESCRIPTIONEND####
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60 //
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61 //==========================================================================
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62
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63 #include <pkgconf/hal.h>
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64
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65 #include <cyg/infra/cyg_type.h>
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66
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67 #include <cyg/hal/plf_intr.h>
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68
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69 //--------------------------------------------------------------------------
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70 // Interrupt vectors.
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71
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72 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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73
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74 // These are decoded via the IP bits of the cause
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75 // register when an external interrupt is delivered.
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76
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77 #define CYGNUM_HAL_INTERRUPT_1 0
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78 #define CYGNUM_HAL_INTERRUPT_2 1
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79 #define CYGNUM_HAL_INTERRUPT_3 2
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80 #define CYGNUM_HAL_INTERRUPT_4 3
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81 #define CYGNUM_HAL_INTERRUPT_5 4
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82 #define CYGNUM_HAL_INTERRUPT_6 5
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83 #define CYGNUM_HAL_INTERRUPT_7 6
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84 #define CYGNUM_HAL_INTERRUPT_DMAC1_CH3 7
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85 #define CYGNUM_HAL_INTERRUPT_DMAC1_CH2 8
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86 #define CYGNUM_HAL_INTERRUPT_DMAC0_CH1 9
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87 #define CYGNUM_HAL_INTERRUPT_DMAC0_CH0 10
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88 #define CYGNUM_HAL_INTERRUPT_SIO_0 11
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89 #define CYGNUM_HAL_INTERRUPT_SIO_1 12
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90 #define CYGNUM_HAL_INTERRUPT_TMR_0 13
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91 #define CYGNUM_HAL_INTERRUPT_TMR_1 14
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92 #define CYGNUM_HAL_INTERRUPT_TMR_2 15
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93 #define CYGNUM_HAL_INTERRUPT_0 16
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94
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95 // Min/Max ISR numbers and how many there are
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96 #define CYGNUM_HAL_ISR_MIN 0
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97 #define CYGNUM_HAL_ISR_MAX 16
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98 #define CYGNUM_HAL_ISR_COUNT 17
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99
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100 // The vector used by the Real time clock
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101 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMR_0
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102
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103 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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104
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105 #endif
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106
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107 //--------------------------------------------------------------------------
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108 // Interrupt controller access.
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109
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110 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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111
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112 #if defined(CYGPKG_HAL_MIPS_TX3904)
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113
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114 #define CYG_HAL_MIPS_TX3904_ILR0 0xFFFFC010
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115 #define CYG_HAL_MIPS_TX3904_CConR 0xFFFFE000
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116
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117 // Array which stores the configured priority levels for the configured
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118 // interrupts.
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119 externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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120
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121
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122 #define HAL_INTERRUPT_MASK( _vector_ ) \
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123 { \
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124 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
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125 CYG_WORD32 _ilr_; \
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126 _reg_ += (_vector_)&0xC; \
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127 HAL_READ_UINT32( _reg_, _ilr_ ); \
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128 _ilr_ &= ~(7 << (((_vector_)&0x3)<<3)); \
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129 HAL_WRITE_UINT32( _reg_, _ilr_ ); \
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130 }
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131
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132 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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133 { \
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134 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
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135 CYG_WORD32 _ilr_; \
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136 _reg_ += (_vector_)&0xC; \
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137 HAL_READ_UINT32( _reg_, _ilr_ ); \
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138 _ilr_ |= hal_interrupt_level[_vector_] << (((_vector_)&0x3)<<3); \
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139 HAL_WRITE_UINT32( _reg_, _ilr_ ); \
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140 }
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141
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142 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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143 { \
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144 if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \
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145 _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \
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146 { \
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147 cyg_uint32 _v_ = _vector_ + 1; \
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148 cyg_uint8 _reg_; \
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149 \
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150 /* adjust vector to bit offset in CConR */ \
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151 if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \
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152 \
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153 /* get CConR */ \
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154 HAL_READ_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_ ); \
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155 \
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156 /* clear old value and set new */ \
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157 _reg_ &= ~(7 << 5); \
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158 _reg_ |= _v_ << 5; \
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159 HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_); \
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160 } \
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161 }
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162
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163 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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164 { \
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165 if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \
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166 _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \
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167 { \
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168 cyg_uint32 _v_ = _vector_ + 1; \
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169 cyg_uint32 _val_ = 0; \
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170 cyg_uint16 _reg_; \
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171 \
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172 /* adjust vector to bit offset in CConR */ \
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173 if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \
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174 _v_ <<= 1; \
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175 \
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176 /* set bits according to requirements */ \
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177 if( _up_ ) _val_ |= 1; \
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178 if( !(_level_) ) _val_ |= 2; \
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179 \
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180 /* get CConR */ \
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181 HAL_READ_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \
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182 \
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183 /* clear old value and set new */ \
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184 _reg_ &= ~(3 << _v_); \
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185 _reg_ |= _val_ << _v_; \
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186 HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \
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187 } \
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188 }
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189
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190 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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191 { \
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192 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
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193 CYG_WORD32 _ilr_; \
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194 _reg_ += (_vector_)&0xC; \
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195 HAL_READ_UINT32( _reg_, _ilr_ ); \
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196 _ilr_ |= (_level_) << (((_vector_)&0x3)<<3); \
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197 HAL_WRITE_UINT32( _reg_, _ilr_ ); \
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198 hal_interrupt_level[_vector_] = _level_; \
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199 }
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200
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201 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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202
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203 #else
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204
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205 #error Unspecified TX39 variant
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206
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207 #endif
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208
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209 #endif
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210
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211 //--------------------------------------------------------------------------
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212 // Clock control
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213
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214 #ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
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215
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216 #if defined(CYGPKG_HAL_MIPS_TX3904)
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217
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218 #define CYG_HAL_MIPS_TX3904_TIMER_BASE 0xFFFFF000
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219 #define CYG_HAL_MIPS_TX3904_TIMER_CR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x00)
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220 #define CYG_HAL_MIPS_TX3904_TIMER_SR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x04)
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221 #define CYG_HAL_MIPS_TX3904_TIMER_CPR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x08)
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222 #define CYG_HAL_MIPS_TX3904_TIMER_IMR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x10)
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223 #define CYG_HAL_MIPS_TX3904_TIMER_DR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x20)
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224 #define CYG_HAL_MIPS_TX3904_TIMER_RR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0xF0)
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225
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226 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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227 { \
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228 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_DR, 0x00000003 ); \
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229 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CPR, _period_ ); \
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230 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \
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231 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_IMR, 0x00008001 ); \
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232 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CR, 0x000000C0 ); \
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233 }
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234
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235 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
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236 { \
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237 HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \
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238 }
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239
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240 #if defined(CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC) && \
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241 !defined(CYGPKG_HAL_MIPS_SIM)
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242
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243 // We need to sync and check the coprocessor 0 condition - this
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244 // indicates whether data is present in the write buffer. We need to
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245 // wait until the data to be written is flushed out. This works
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246 // around a tx39 bug. gcc will insert a NOP after the asm insns.
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247
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248 # define HAL_CLOCK_READ( _pvalue_ ) \
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249 CYG_MACRO_START \
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250 asm volatile ( \
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251 "sync; nop; 1: ; bc0f 1b" \
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252 : \
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253 : \
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254 : "$0" \
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255 ); \
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256 HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \
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257 CYG_MACRO_END
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258
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259 #else
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260
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261 # define HAL_CLOCK_READ( _pvalue_ ) \
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262 CYG_MACRO_START \
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263 HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \
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264 CYG_MACRO_END
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265
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266 #endif
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267
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268 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
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269 !defined(HAL_CLOCK_LATENCY)
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270 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
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271 #endif
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272
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273 #define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
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274
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275 #else
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276
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277 #error Unspecified TX39 variant
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278
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279 #endif
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280
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281 #endif
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282
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283 //--------------------------------------------------------------------------
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284 // Timeout exception support. This is TX39 specific.
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285
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286 #if defined(CYGPKG_HAL_MIPS_TX3904)
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287
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288 #define HAL_TX39_DEBUG_TOE_ENABLE() \
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289 { \
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290 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \
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291 CYG_WORD32 _cconr_; \
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292 HAL_READ_UINT32( _reg_, _cconr_); \
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293 _cconr_ |= 0x04000000; \
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294 HAL_WRITE_UINT32( _reg_, _cconr_); \
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295 }
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296
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297 #define HAL_TX39_DEBUG_TOE_DISABLE() \
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298 { \
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299 HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \
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300 CYG_WORD32 _cconr_; \
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301 HAL_READ_UINT32( _reg_, _cconr_); \
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302 _cconr_ &= 0xFBFFFFFF; \
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303 HAL_WRITE_UINT32( _reg_, _cconr_); \
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304 }
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305
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306 #else
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307
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308 #define HAL_TX39_DEBUG_TOE_ENABLE()
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309
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310 #define HAL_TX39_DEBUG_TOE_DISABLE()
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311
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312 #endif
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313
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314
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315 //--------------------------------------------------------------------------
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316 #endif // ifndef CYGONCE_HAL_IMP_INTR_H
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317 // End of imp_intr.h