nand-ecoscentric: packages/hal/powerpc/arch/current/src/vectors.S annotate

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 3403:8c8767bb9a62 default tip

devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.

author	Ross Younger <wry@ecoscentric.com>
date	Sun, 18 Jan 2015 17:59:01 +1300
parents	5d701b4e0c3b
children

rev	line source
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	1 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3 ## vectors.S
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 ## PowerPC exception vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	6 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	7 ##==========================================================================
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	8 ## ####ECOSGPLCOPYRIGHTBEGIN####
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	9 ## -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	10 ## This file is part of eCos, the Embedded Configurable Operating System.
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	12 ##
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	13 ## eCos is free software; you can redistribute it and/or modify it under
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	14 ## the terms of the GNU General Public License as published by the Free
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	15 ## Software Foundation; either version 2 or (at your option) any later
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	16 ## version.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	17 ##
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	21 ## for more details.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	22 ##
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	23 ## You should have received a copy of the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	26 ##
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	27 ## As a special exception, if other files instantiate templates or use
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	28 ## macros or inline functions from this file, or you compile this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	29 ## and link it with other works to produce a work based on this file,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	30 ## this file does not by itself cause the resulting work to be covered by
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	31 ## the GNU General Public License. However the source code for this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	32 ## must still be made available in accordance with section (3) of the GNU
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	33 ## General Public License v2.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	34 ##
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	35 ## This exception does not invalidate any other reasons why a work based
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	36 ## on this file might be covered by the GNU General Public License.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	37 ## -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2563 diff changeset	38 ## ####ECOSGPLCOPYRIGHTEND####
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	40 #######DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	41 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	42 ## Author(s): nickg, jskov
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	43 ## Contributors: nickg, jskov
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	44 ## Date: 1999-02-20
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	45 ## Purpose: PowerPC exception vectors
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 ## Description: This file defines the code placed into the exception
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	47 ## vectors. It also contains the first level default VSRs
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	48 ## that save and restore state for both exceptions and
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	49 ## interrupts.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	50 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 ######DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	52 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	53 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	55 #===========================================================================
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	56 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	57 # The PowerPC exception handling has changed as of version 1.3.1.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	58 # The primary motivation for rewriting the code was to bring it more
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	59 # in line with the other HALs, in particular to allow a RAM application
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	60 # to cleanly take over only a subset of vectors from a running ROM
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	61 # monitor.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	62 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	63 # GDB stubs (and CygMon, should it be ported to PPC) copies
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	64 # exception vector entry handler code to address 0. These vector entry
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	65 # handlers (defined by the exception_vector macro below) compute
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	66 # a vector index into the hal_vsr_table, fetch the pointer, and
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	67 # jump to the HAL vector service routine (VSR).
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	68 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	69 # The hal_vsr_table is located immediately after the vector
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	70 # handlers (at address 0x3000), allowing RAM applications to
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	71 # change VSRs as necessary, while still keeping desired ROM
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	72 # monitor functionality available for debugging.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	73 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	74 # ROM applications can still be configured to leave the vector entry
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	75 # handlers at 0xff000000, but there is at the moment no
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	76 # provision for reclaiming the reserved vector space in RAM to
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	77 # application usage.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	78 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	79 # RAM applications can also be configured to provide exception
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	80 # handlers which are copied to address 0 on startup, thus taking
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	81 # full control of the target.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	82 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	83 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	84 # Default configuration is for RAM applications to rely on an
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	85 # existing ROM monitor to provide debugging functionality, and
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	86 # for ROM applications to copy vectors to address 0.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	87 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	88 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	89 # Unfortunately the new exception scheme is not compatible with the
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	90 # old scheme. Stubs and applications must be compiled using the same
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	91 # scheme (i.e., old binaries will not run with new stubs, and new
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	92 # binaries will not run with old stubs).
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	93 #
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	94 #===========================================================================
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	95
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 #include <pkgconf/hal.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 #ifdef CYGPKG_KERNEL
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	100 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	101
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	102 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	103 #include <cyg/hal/ppc_regs.h>
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	104
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	105 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	106
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 149 diff changeset	107 // .file "vectors.S"
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	108
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	109 .extern hal_interrupt_data
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	110 .extern hal_interrupt_handlers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	111 .extern hal_interrupt_objects
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	112 .extern hal_vsr_table
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	113
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	114 .extern cyg_hal_invoke_constructors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	115 .extern cyg_instrument
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	116 .extern cyg_start
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	117 .extern hal_IRQ_init
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	118 .extern hal_MMU_init
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	119 .extern hal_enable_caches
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	120 .extern hal_hardware_init
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	121 .extern initialize_stub
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	122
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	123 .extern __bss_start
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	124 .extern __bss_end
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	125 .extern __sbss_start
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	126 .extern __sbss_end
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	127
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	128 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	129 # MSR initialization value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 # zero all bits except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131 # FP = floating point available
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	132 # ME = machine check enabled
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	133 # IP = vectors at 0xFFFxxxxx (ROM startup only)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	134 # IR = instruction address translation
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	135 # DR = data address translation
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136 # RI = recoverable interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	138 #define CYG_MSR_COMMON (MSR_FP \| MSR_ME \| MSR_RI)
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	139
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	140 #if (CYGHWR_HAL_POWERPC_VECTOR_BASE == 0xfff00000)
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	141 # define IP_BIT MSR_IP
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	142 #else
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	143 # define IP_BIT 0
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	144 #endif
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	145
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	146 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	147 # define IR_DR_BITS (MSR_IR \| MSR_DR)
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	148 #else
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	149 # define IR_DR_BITS 0
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	150 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	151
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	152 #define CYG_MSR (CYG_MSR_COMMON \| IP_BIT \| IR_DR_BITS)
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	153
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	154 # Include variant macros after MSR definition.
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	155 #include <cyg/hal/arch.inc>
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	156 #include <cyg/hal/ppc_offsets.inc>
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	157
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	158
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	159 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	160 # If the following option is enabled, we only save registers up to R12.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	161 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162 # not need to save them when calling C functions.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	163
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	164 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	165 # define MAX_SAVE_REG 12
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	166 #else
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	167 # define MAX_SAVE_REG 31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	168 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	170
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	171 #if defined(CYGHWR_HAL_POWERPC_NEED_VECTORS)
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	172
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	173 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	174 # Start by defining the exceptions vectors that must be placed at
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	175 # locations 0xFFF00000 or 0x00000000. The following code will normally
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	176 # be located at 0xFFF00000 in the ROM. It may optionally be copied out
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	177 # to 0x00000000 if we want to use the RAM vectors. For this reason this code
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	178 # MUST BE POSITION INDEPENDENT.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	179
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	180 .section ".vectors","ax"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	181
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	182 #---------------------------------------------------------------------------
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	183 # Macros for generating an exception vector service routine
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	184
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	185 # Reset vector macro
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	186
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	187 .macro reset_vector name
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	188 .p2align CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	189 .globl __exception_\name
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	190 __exception_\name:
473 87f3e026b015 PPC60x improvements gthomas parents: 423 diff changeset	191 #ifdef CYGSEM_HAL_POWERPC_RESET_USES_JUMP
87f3e026b015 PPC60x improvements gthomas parents: 423 diff changeset	192 bl _start
87f3e026b015 PPC60x improvements gthomas parents: 423 diff changeset	193 #else
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	194 lwi r3,_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	195 mtlr r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	196 blr
473 87f3e026b015 PPC60x improvements gthomas parents: 423 diff changeset	197 #endif
87f3e026b015 PPC60x improvements gthomas parents: 423 diff changeset	198
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	199 .endm
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	200
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	201 # Generic vector macro
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	202
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	203 .macro exception_vector name
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	204 .p2align CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	205 .globl __exception_\name
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	206 __exception_\name:
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	207 mtspr SPRG1,r3 # stash some work registers away
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	208 mtspr SPRG2,r4
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	209 mtspr SPRG3,r5
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	210 mfcr r4 # stash CR
138 289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	211 li r5,__exception_\name-rom_vectors # load low half of vector addr
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	212 srwi r5,r5,(CYGHWR_HAL_POWERPC_VECTOR_ALIGNMENT-2) # shift right by alignment-2
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	213 lwi r3,hal_vsr_table # table base
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	214 lwzx r3,r3,r5 # address of vsr
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	215 mflr r5 # save link register
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	216 mtlr r3 # put vsr address into it
138 289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	217 li r3,__exception_\name-rom_vectors # reload low half of vector addr
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	218 blr # go to common code
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 .endm
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	221 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 # Define the exception vectors.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223
138 289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	224 // Some platforms won't let us put the vector code just where we want
289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	225 // This macro introduces some lattitude in vector placement
289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	226
289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	227 #ifdef CYG_HAL_FUDGE_VECTOR_ALIGNMENT
289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	228 hal_fudge_vector_alignment
289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	229 #endif
2897 5d701b4e0c3b * cdl/hal_powerpc.cdl: Add CYGHWR_HAL_POWERPC_BOOK_E_FIXED_VECTORS nickg parents: 2883 diff changeset	230
5d701b4e0c3b * cdl/hal_powerpc.cdl: Add CYGHWR_HAL_POWERPC_BOOK_E_FIXED_VECTORS nickg parents: 2883 diff changeset	231 hal_fixed_vectors
5d701b4e0c3b * cdl/hal_powerpc.cdl: Add CYGHWR_HAL_POWERPC_BOOK_E_FIXED_VECTORS nickg parents: 2883 diff changeset	232
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	233 rom_vectors:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	234 # These are the architecture defined vectors that
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	235 # are always present.
138 289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	236 #ifdef CYG_HAL_RESERVED_VECTOR_00000
289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	237 hal_reserved_vector_00000
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	238 #else
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	239 exception_vector reserved_00000
138 289bf90c6a9b Merge from eCos master repository on 2000-11-24-06:43:05-GMT jlarmour parents: 136 diff changeset	240 #endif
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	241 reset_vector reset
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	242 exception_vector machine_check
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	243 exception_vector data_storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	244 exception_vector instruction_storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	245 exception_vector external
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	246 exception_vector alignment
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	247 exception_vector program
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	248 exception_vector floatingpoint_unavailable
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	249 exception_vector decrementer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	250 exception_vector reserved_00a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	251 exception_vector reserved_00b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	252 exception_vector system_call
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	253 exception_vector trace
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	254 exception_vector floatingpoint_assist
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	255 exception_vector reserved_00f00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	256
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	257 #if defined(CYGHWR_HAL_POWERPC_BOOK_E)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	258 # Book E defines some extra vectors
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	259 exception_vector critical_input
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	260 exception_vector ap_unavailable
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	261 exception_vector interval_timer
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	262 exception_vector watchdog
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	263 exception_vector data_tlb_miss
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	264 exception_vector instruction_tlb_miss
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	265 exception_vector debug
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	266 #endif
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	267
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	268 # Variants may define extra vectors.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	269 hal_extra_vectors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	270
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	271 rom_vectors_end:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	272
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	273 #else // CYGHWR_HAL_POWERPC_NEED_VECTORS
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	274
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	275 # When vectors are not included this is the primary entry point.
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	276 .globl __exception_reset
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	277 __exception_reset:
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	278 lwi r3,_start
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	279 mtlr r3
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	280 blr
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	281
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	282 #endif // CYGHWR_HAL_POWERPC_NEED_VECTORS
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	283
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	284
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	285
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	286 #===========================================================================
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	287 # Real startup code. We jump here from the various reset vectors to set up
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	288 # the world.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	290 .text
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	291 .globl _start
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	292 _start:
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	293 # Initialize CPU to a post-reset state, ensuring the ground doesn''t
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	294 # shift under us while we try to set things up.
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	295 hal_cpu_init
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	296
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	297 # Set up global offset table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	298 lwi r2,_GLOBAL_OFFSET_TABLE_
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300 # set up time base register to zero
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301 xor r3,r3,r3
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	302 mtspr TBL_W,r3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	303 xor r4,r4,r4
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	304 mtspr TBU_W,r4
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	305
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	306 # Call platform specific hardware initialization
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	307 # This may include memory controller initialization. It is not
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	308 # safe to access RAM until after this point.
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	309 bl hal_hardware_init # this is platform dependent
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 149 diff changeset	310 .globl _hal_hardware_init_done
1223 dbcfe4e0dbd2 New platform - TAMS MOAB - and generic changes to support it gthomas parents: 1157 diff changeset	311 _hal_hardware_init_done:
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 149 diff changeset	312
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	313 hal_vectors_init
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	314
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315 # set up stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 lwi sp,__interrupt_stack
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	317 mtspr SPRG0,sp # save in sprg0 for later use
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	319 # Set up exception handlers and VSR table, taking care not to
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	320 # step on any ROM monitor''s toes.
473 87f3e026b015 PPC60x improvements gthomas parents: 423 diff changeset	321 hal_mon_init
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	322
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	323 #if defined(CYG_HAL_STARTUP_ROM)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324 # Copy data from ROM to ram
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325 lwi r3,__rom_data_start # r3 = rom start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	326 lwi r4,__ram_data_start # r4 = ram start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	327 lwi r5,__ram_data_end # r5 = ram end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	328
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	329 cmplw r4,r5 # skip if no data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	330 beq 2f
2438 8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	331 sub r5,r5,r4 # compute number of words to copy
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	332 srwi r5,r5,2
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	333 mtctr r5
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	334 subi r3,r3,4
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	335 subi r4,r4,4
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	336 1: lwzu r0,4(r3) # get word from ROM
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	337 stwu r0,4(r4) # store in RAM
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	338 bdnz 1b
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	339 2:
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	340 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	341
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	342 # clear BSS
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	343 lwi r3,__bss_start # r3 = start
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	344 lwi r4,__bss_end # r4 = end
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	345 li r0,0 # r0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	346 cmplw r3,r4 # skip if no bss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	347 beq 2f
2438 8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	348 sub r4,r4,r3 # compute number of words to clear
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	349 srwi r4,r4,2
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	350 mtctr r4
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	351 subi r3,r3,4
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	352
2438 8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	353 1: stwu r0,4(r3) # store zero & increment pointer
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	354 bdnz 1b
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	355 2:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	356
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	357 # clear SBSS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	358 lwi r3,__sbss_start # r3 = start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	359 lwi r4,__sbss_end # r4 = end
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	360 cmplw r3,r4 # skip if no sbss
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	361 beq 2f
2438 8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	362 sub r4,r4,r3 # compute number of words to clear
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	363 srwi r4,r4,2
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	364 mtctr r4
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	365 subi r3,r3,4
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	366
2438 8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	367 1: stwu r0,4(r3) # store zero & increment pointer
8317d1af06db Optimize system initialization gthomas parents: 1431 diff changeset	368 bdnz 1b
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	369 2:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	370
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	371 # It is now safe to call C functions which may rely on initialized
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	372 # data.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	373
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	374 # Set up stack for calls to C code.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	375 subi sp,sp,12 # make space on stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	376 li r0,0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	377 stw r0,0(sp) # clear back chain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	378 stw r0,8(sp) # zero return pc
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	379 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	380
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	381 # Variant HALs may need to do something special before we continue
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	382 bl hal_variant_init
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	383
101 c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	384 # Platform initialization
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	385 bl hal_platform_init
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	386
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	387 # MMU and cache are controlled by the same option since caching
1333 0e2485da1dbc Fix problem with [re]enable of FPU during interrupts gthomas parents: 1223 diff changeset	388 # on the PPC [typically] does not make sense without the MMU to mark
0e2485da1dbc Fix problem with [re]enable of FPU during interrupts gthomas parents: 1223 diff changeset	389 # regions which should not be cached.
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	390 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	391 # Initialize MMU.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	392 bl hal_MMU_init
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	393
1333 0e2485da1dbc Fix problem with [re]enable of FPU during interrupts gthomas parents: 1223 diff changeset	394 # Enable MMU (if desired) so we can safely enable caches.
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	395 lwi r3,CYG_MSR # interrupts enabled later
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	396 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	397 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	398 sync
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	399
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	400 # Enable caches
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	401 bl hal_enable_caches
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	402 #endif // CYGHWR_HAL_POWERPC_ENABLE_MMU
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	403
149 52c99470ec11 Merge from eCos master repository on 2001-01-19-06:43:03-GMT jlarmour parents: 138 diff changeset	404 # set up platform specific interrupt environment
52c99470ec11 Merge from eCos master repository on 2001-01-19-06:43:03-GMT jlarmour parents: 138 diff changeset	405 bl hal_IRQ_init
52c99470ec11 Merge from eCos master repository on 2001-01-19-06:43:03-GMT jlarmour parents: 138 diff changeset	406
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	407 # call c++ constructors
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	408 bl cyg_hal_invoke_constructors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	409
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	410 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	411 bl initialize_stub
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	412 #endif
101 c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	413 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	414 \|\| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	415 .extern hal_ctrlc_isr_init
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	416 bl hal_ctrlc_isr_init
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	417 #endif
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	418
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	419 bl cyg_start # call cyg_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	420 9:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	421 b 9b # if we return, loop
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	422
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	423 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	424 # This code handles the common part of all exception handlers.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	425 # It saves the machine state onto the stack and then calls
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	426 # a "C" routine to do the rest of the work. This work may result
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	427 # in thread switches, and changes to the saved state. When we return
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	428 # here the saved state is restored and execution is continued.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	429
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	430 .text
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	431
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	432 .globl cyg_hal_default_exception_vsr
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	433 cyg_hal_default_exception_vsr:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	434
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	435 # We come here with all register containing their
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	436 # pre-exception values except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	437 # R3 = ls 16 bits of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	438 # R4 = saved CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	439 # R5 = saved LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	440 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	441 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	442 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	443 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	444 # SRR0 = old PC
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	445 # SRR1 = old MSR and the exception cause (the POW state is lost!)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	446
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	447 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	448 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	449 # a safety margin
136 a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	450 #ifdef CYGPKG_HAL_POWERPC_PPC40x
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	451 // The caches on this processor are always enabled when the MMU is on
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	452 // (and disabled when off). Thus we need to be careful about cache
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	453 // polution and staleness when changing the MMU state.
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	454 // At this point, the MMU is off due to the exception. We need to
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	455 // flush the part of the cache which may be touched before the MMU
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	456 // is reenabled so that memory will be consistent when that happens.
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	457 // Of course, this is complicated by the fact that there are no "free"
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	458 // registers at this point in the code.
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	459 dcbf 0,sp // Flushes first line
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	460 stw r3,0(sp) // This is now safe
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	461 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	462 dcbf r3,sp
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	463 li r3,CYGARC_PPCREG_CR
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	464 dcbf r3,sp
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	465 li r3,CYGARC_PPCREG_LR
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	466 dcbf r3,sp
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	467 lwz r3,0(sp) // Restore register
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	468 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	469
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	470 # First, save away some registers
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	471 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	472 stw r4,CYGARC_PPCREG_CR(sp) # stash CR
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	473 stw r5,CYGARC_PPCREG_LR(sp) # stash LR
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	474
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	475 # Save exception PC and MSR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	476 mfsrr0 r3
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	477 stw r3,CYGARC_PPCREG_PC(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	478 mfsrr1 r3
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	479 stw r3,CYGARC_PPCREG_MSR(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	480
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	481 cyg_hal_default_exception_vsr_common:
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	482
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	483 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	484 # Mark this frame as an Exception frame
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	485 lwi r3,0xDDDDDDE0
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	486 stw r3,CYGARC_PPCREG_WALL_HEAD(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	487 lwi r3,0xDDDDDDE1
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	488 stw r3,CYGARC_PPCREG_WALL_TAIL(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	489 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	490
1333 0e2485da1dbc Fix problem with [re]enable of FPU during interrupts gthomas parents: 1223 diff changeset	491 # Enable MMU & interrupt/FPU environment (as configured)
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	492 lwi r3,CYG_MSR
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	493 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	494 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	495 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	496
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	497 mfspr r3,SPRG1 # save original R3
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	498 stw r3,CYGARC_PPCREG_REGS+3*4(sp)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	499 mfspr r4,SPRG2 # save original R4
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	500 stw r4,CYGARC_PPCREG_REGS+4*4(sp)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	501 mfspr r5,SPRG3 # save original R5
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	502 stw r5,CYGARC_PPCREG_REGS+5*4(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	503
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	504 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	505 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	506
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	507 mr r3,sp # recreate original SP
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	508 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	509 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	510
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	511 # Save registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	512 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	513 .rept MAX_SAVE_REG+1-6
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	514 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	515 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	516 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	517
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	518 # Save registers used in vsr (r14+r15)
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	519 stw r14,(CYGARC_PPCREG_REGS+14*4)(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	520 stw r15,(CYGARC_PPCREG_REGS+15*4)(sp)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	521
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	522 # get remaining family CPU registers
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	523 mfxer r3
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	524 mfctr r4
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	525 # and store them
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	526 stw r3,CYGARC_PPCREG_XER(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	527 stw r4,CYGARC_PPCREG_CTR(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	528
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	529 # Save variant registers
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	530 hal_variant_save sp
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	531
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	532 # Save FPU registers
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	533 hal_fpu_save sp
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	534
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	535 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	536 # call into C to do something with it.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	537
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	538 mr r3,sp # R3 = register dump
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	539
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	540 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	541
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	542 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	543 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	544 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	545
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	546 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	547 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	548
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	549 lwi r5,restore_state # get return link
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	550 mtlr r5 # to link register
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	551
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	552 .extern cyg_hal_exception_handler
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	553 b cyg_hal_exception_handler # call C code, r3 = registers
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	554
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	555 # When the call returns it will go to restore_state below.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	556
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	557 #if defined(CYGHWR_HAL_POWERPC_BOOK_E)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	558 ##--------------------------------------------------------------------------
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	559 ## Critical exception handling code.
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	560 ##
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	561 ## Book E processors save the old PC and MSR in CSRR0/1 for certain
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	562 ## exceptions. This VSR saves the values from these registers before
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	563 ## branching to the common VSR code.
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	564
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	565 .globl cyg_hal_default_critical_exception_vsr
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	566 cyg_hal_default_critical_exception_vsr:
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	567
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	568 # We come here with all register containing their
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	569 # pre-exception values except:
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	570 # R3 = ls 16 bits of vector address
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	571 # R4 = saved CR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	572 # R5 = saved LR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	573 # LR = VSR address
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	574 # SPRG1 = old R3
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	575 # SPRG2 = old R4
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	576 # SPRG3 = old R5
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	577 # CSRR0 = old PC
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	578 # CSRR1 = old MSR and the exception cause
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	579
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	580 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	581 # leave space for registers and
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	582 # a safety margin
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	583
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	584 # First, save away some registers
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	585 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	586 stw r4,CYGARC_PPCREG_CR(sp) # stash CR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	587 stw r5,CYGARC_PPCREG_LR(sp) # stash LR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	588
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	589 # Save exception PC and MSR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	590 mfspr r3,58
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	591 stw r3,CYGARC_PPCREG_PC(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	592 mfspr r3,59
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	593 stw r3,CYGARC_PPCREG_MSR(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	594
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	595 b cyg_hal_default_exception_vsr_common
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	596
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	597 #endif
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	598
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	599 ##--------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	600 ## The following macros are defined depending on whether the Interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	601 ## system is using isr tables or chaining, and depending on the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	602 ## controller in the system.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	603
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	604 #ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	605
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	606 ## This is the simple version. No interrupt controller, CYGARC_PPCREG_VECTOR
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	607 ## is updated with the decoded interrupt vector. Isr tables/chaining
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	608 ## use same interrupt decoder.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	609 ## Bit 21 biffers between decrementer (0) and external (1).
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	610
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	611 # decode the interrupt
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	612 .macro hal_intc_decode dreg,state
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	613 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	614 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	615 stw \dreg,CYGARC_PPCREG_VECTOR(\state) # vector in state frame.
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	616 slwi \dreg,\dreg,2 # convert to word offset.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	617 .endm
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	618
72 da3908c9cd10 Merge from eCos master repository on 2000-02-17-18:56:14-GMT jlarmour parents: 70 diff changeset	619 #endif // CYGPKG_HAL_POWERPC_INTC_DEFINED
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	620
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	621 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	622 # Common interrupt handling code.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	623
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	624 .globl cyg_hal_default_interrupt_vsr
c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	625 cyg_hal_default_interrupt_vsr:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	626
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	627 # We come here with all register containing their
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	628 # pre-exception values except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	629 # R3 = ls 16 bits of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	630 # R4 = saved CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	631 # R5 = saved LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	632 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	633 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	634 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	635 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	636 # SRR0 = old PC
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	637 # SRR1 = old MSR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	638
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	639
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	640 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	641 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	642 # a safety margin
136 a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	643 #ifdef CYGPKG_HAL_POWERPC_PPC40x
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	644 // The caches on this processor are always enabled when the MMU is on
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	645 // (and disabled when off). Thus we need to be careful about cache
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	646 // polution and staleness when changing the MMU state.
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	647 // At this point, the MMU is off due to the exception. We need to
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	648 // flush the part of the cache which may be touched before the MMU
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	649 // is reenabled so that memory will be consistent when that happens.
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	650 // Of course, this is complicated by the fact that there are no "free"
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	651 // registers at this point in the code.
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	652 dcbf 0,sp // Flushes first line
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	653 stw r3,0(sp) // This is now safe
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	654 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	655 dcbf r3,sp
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	656 li r3,CYGARC_PPCREG_CR
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	657 dcbf r3,sp
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	658 li r3,CYGARC_PPCREG_LR
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	659 dcbf r3,sp
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	660 lwz r3,0(sp) // Restore register
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	661 #endif
a9ac27ec7abc Merge from eCos master repository on 2000-11-17-18:24:25-GMT jlarmour parents: 105 diff changeset	662
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	663 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	664 stw r4,CYGARC_PPCREG_CR(sp) # stash CR
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	665 stw r5,CYGARC_PPCREG_LR(sp) # stash LR
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	666
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	667 # Save exception PC and MSR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	668 mfsrr0 r3
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	669 stw r3,CYGARC_PPCREG_PC(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	670 mfsrr1 r3
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	671 stw r3,CYGARC_PPCREG_MSR(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	672
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	673 cyg_hal_default_interrupt_vsr_common:
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	674
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	675 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	676 # Mark this frame as an interrupt frame
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	677 lwi r3,0xDDDDDD10
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	678 stw r3,CYGARC_PPCREG_WALL_HEAD(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	679 lwi r3,0xDDDDDD11
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	680 stw r3,CYGARC_PPCREG_WALL_TAIL(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	681 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	682
1333 0e2485da1dbc Fix problem with [re]enable of FPU during interrupts gthomas parents: 1223 diff changeset	683 # Enable MMU & interrupt/FPU environment as configured
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	684 lwi r3,CYG_MSR
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	685 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	686 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	687 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	688
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	689 mfspr r3,SPRG1 # save original R3
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	690 stw r3,CYGARC_PPCREG_REGS+3*4(sp)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	691 mfspr r4,SPRG2 # save original R4
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	692 stw r4,CYGARC_PPCREG_REGS+4*4(sp)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	693 mfspr r5,SPRG3 # save original R5
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	694 stw r5,CYGARC_PPCREG_REGS+5*4(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	695
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	696 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	697 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	698
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	699 mr r3,sp # recreate original SP
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	700 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	701 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	702
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	703 # Save registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	704 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	705 .rept MAX_SAVE_REG+1-6
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	706 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	707 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	708 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	709
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	710 # Save registers used in vsr (r14+r15)
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	711 stw r14,CYGARC_PPCREG_REGS+14*4(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	712 stw r15,CYGARC_PPCREG_REGS+15*4(sp)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	713
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	714 # get remaining family CPU registers
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	715 mfxer r3
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	716 mfctr r4
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	717
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	718 # and store them
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	719 stw r3,CYGARC_PPCREG_XER(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	720 stw r4,CYGARC_PPCREG_CTR(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	721
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	722 # Save variant registers
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	723 hal_variant_save sp
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	724
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	725 # Save FPU registers
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	726 hal_fpu_save sp
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	727
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	728 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	729 # increment the scheduler lock and call the ISR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	730 # for this vector.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	731
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	732 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	733 .extern cyg_scheduler_sched_lock
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	734 lwi r3,cyg_scheduler_sched_lock
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	735 lwz r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	736 addi r4,r4,1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	737 stw r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	738 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	739
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	740 mr r14,sp # r14 = register dump
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	741
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	742 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	743 lwi r3,__interrupt_stack # stack top
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	744 lwi r4,__interrupt_stack_base # stack base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	745 sub. r5,sp,r4 # sp - base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	746 blt 1f # if < 0 - not on istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	747 sub. r5,r3,sp # top - sp
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	748 bgt 2f # if > 0 - already on istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	749
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	750 1: mr sp,r3 # switch to istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	751
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	752 2: stwu r14,-4(sp) # save old SP on stack
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	753
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	754 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	755
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	756 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	757
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	758 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	759 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	760 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	761
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	762 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	763 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	764
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	765 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	766
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	767 lwi r3,0x0301 # r3 = type = INTR,RAISE
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	768 lwz r4,CYGARC_PPCREG_VECTOR(r14) # arg1 = vector address
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	769 srwi r4,r4,8 # arg1 = vector number
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	770 xor r5,r5,r5 # arg2 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	771 bl cyg_instrument # call instrument function
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	772
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	773 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	774
70 c5536bad4c24 Merge from eCos master repository on 2000-02-11-15:46:40-GMT jlarmour parents: 68 diff changeset	775 hal_intc_decode r15,r14 # get table index
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	776
101 c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	777 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	778 \|\| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	779 # If we are supporting Ctrl-C interrupts from GDB, we must squirrel
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	780 # away a pointer to the save interrupt state here so that we can
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	781 # plant a breakpoint at some later time.
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	782
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	783 .extern hal_saved_interrupt_state
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	784 lwi r3,hal_saved_interrupt_state
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	785 stw r14,0(r3)
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	786
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	787 #endif
c37d3a9e1b28 Merge from eCos master repository on 2000-06-16-07:47:03-BST jlarmour parents: 82 diff changeset	788
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	789 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	790
68 f74b2666b30d Merge from eCos master repository on 2000-02-04-07:47:04-GMT jlarmour parents: 66 diff changeset	791 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	792 # The CPM controller allows nested interrupts. However,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	793 # it sits on the back of the SIU controller which has no
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	794 # HW support for this. In effect, SW masking of lower
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	795 # priority IRQs in the SIU would be required for this to work.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	796 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	797
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	798 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	799
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	800 lwz r3,CYGARC_PPCREG_VECTOR(r14) # retrieve decoded vector #
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	801
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	802 lwi r6,hal_interrupt_handlers # get interrupt handler table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	803 lwzx r6,r6,r15 # load routine pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	804
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	805 lwi r4,hal_interrupt_data # get interrupt data table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	806 lwzx r4,r4,r15 # load data pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	807 # R4 = data argument
423 d175f4be3ab6 Support for application profiling. gthomas parents: 210 diff changeset	808 mr r5,r14 # R5 = saved registers
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	809
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	810 mtctr r6 # put isr address in ctr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	811
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	812 bctrl # branch to ctr reg and link
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	813
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	814 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	815
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	816 # If we are returning from the last nested interrupt, move back
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	817 # to the thread stack. interrupt_end() must be called on the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	818 # thread stack since it potentially causes a context switch.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	819 # Since we have arranged for the top of stack location to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	820 # contain the sp we need to go back to here, just pop it off
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	821 # and put it in SP.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	822
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	823
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	824 lwz sp,CYGARC_PPC_STACK_FRAME_SIZE2(sp) # sp = sp
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	825
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	826 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	827
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	828 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	829 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	830 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	831
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	832 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	833 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	834 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	835
1157 aacbd943879a * src/vectors.S (cyg_hal_default_interrupt_vsr): Removed ifdef on nickg parents: 473 diff changeset	836 # On return r3 bit 1 will indicate whether a DSR is
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	837 # to be posted. Pass this together with a pointer to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	838 # the interrupt object we have just used to the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	839 # interrupt tidy up routine.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	840
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	841 # Note that r14 and r15 are defined to be preserved across
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	842 # calls by the calling convention, so they still contain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	843 # the register dump and the vector number respectively.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	844
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	845 lwi r4,hal_interrupt_objects # get interrupt object table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	846 lwzx r4,r4,r15 # load object pointer
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	847 mr r5,r14 # arg3 = saved register dump
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	848
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	849 .extern interrupt_end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	850 bl interrupt_end # call into C to finish off
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	851
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	852 restore_state:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	853 # All done, restore CPU state and continue
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	854
82 6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	855 # retrieve CPU state pointer
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	856 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE*2
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	857
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	858 # Restore FPU registers
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	859 hal_fpu_load sp
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	860
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	861 # Restore variant registers
6736c52df507 Merge from eCos master repository on 2000-04-14-13:35:46-BST jlarmour parents: 76 diff changeset	862 hal_variant_load sp
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	863
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	864 # get sprs we want to restore
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	865 # stuff some of them into the CPU
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	866 lwz r3,CYGARC_PPCREG_XER(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	867 lwz r4,CYGARC_PPCREG_LR(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	868 lwz r5,CYGARC_PPCREG_CTR(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	869 mtxer r3
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	870 mtlr r4
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	871 mtctr r5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	872
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	873 # Restore registers used in vsr (r14+r15)
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	874 lwz r14,CYGARC_PPCREG_REGS+14*4(r1)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	875 lwz r15,CYGARC_PPCREG_REGS+15*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	876
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	877 # restore registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	878 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	879 .rept MAX_SAVE_REG+1-6
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	880 lwz _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	881 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	882 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	883
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	884 hal_cpu_int_disable
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	885
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	886 # restore R0 and R2
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	887 lwz r0,CYGARC_PPCREG_REGS+0*4(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	888 lwz r2,CYGARC_PPCREG_REGS+2*4(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	889
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	890 # Here all the registers are loaded except
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	891 # sp = HAL_SavedRegisters
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	892 # r3 = ccr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	893 # r4 = srr0 = pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	894 # r5 = srr1 = msr
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	895 #
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	896 # We have to disable interrupts while srr0 and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	897 # srr1 are loaded, since another interrupt will
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	898 # destroy them.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	899
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	900 lwz r3,CYGARC_PPCREG_CR(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	901 lwz r4,CYGARC_PPCREG_PC(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	902 lwz r5,CYGARC_PPCREG_MSR(sp)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	903 mtcr r3 # set ccr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	904 mtsrr0 r4 # load old pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	905 mtsrr1 r5 # load old msr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	906
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	907 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	908 # Mark this frame as (almost) dead.
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	909 lwi r3,0xDDDDDDD0
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	910 stw r3,CYGARC_PPCREG_WALL_HEAD(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	911 lwi r3,0xDDDDDDD1
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	912 stw r3,CYGARC_PPCREG_WALL_TAIL(sp)
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	913 #endif
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	914
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	915 lwz r3,CYGARC_PPCREG_REGS+3*4(sp) # load r3 value
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	916 lwz r4,CYGARC_PPCREG_REGS+4*4(sp) # load r4 value
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	917 lwz r5,CYGARC_PPCREG_REGS+5*4(sp) # load r5 value
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	918 lwz sp,CYGARC_PPCREG_REGS+1*4(sp) # restore sp
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	919
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	920 sync # settle things down
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	921 isync
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	922 rfi # and return
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	923
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	924 #if defined(CYGHWR_HAL_POWERPC_BOOK_E)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	925 ##---------------------------------------------------------------------------
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	926 ## Critical interrupt handling code.
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	927 ##
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	928 ## Book E processors save the old PC and MSR in CSRR0/1 for certain
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	929 ## exceptions. This VSR saves the values from these registers before
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	930 ## branching to the common VSR code.
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	931
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	932 .globl cyg_hal_default_interrupt_vsr
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	933 cyg_hal_default_critical_interrupt_vsr:
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	934
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	935 # We come here with all register containing their
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	936 # pre-exception values except:
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	937 # R3 = ls 16 bits of vector address
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	938 # R4 = saved CR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	939 # R5 = saved LR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	940 # LR = VSR address
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	941 # SPRG1 = old R3
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	942 # SPRG2 = old R4
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	943 # SPRG3 = old R5
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	944 # CSRR0 = old PC
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	945 # CSRR1 = old MSR
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	946
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	947
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	948 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	949 # leave space for registers and
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	950 # a safety margin
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	951
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	952 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	953 stw r4,CYGARC_PPCREG_CR(sp) # stash CR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	954 stw r5,CYGARC_PPCREG_LR(sp) # stash LR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	955
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	956 # Save exception PC and MSR
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	957 mfspr r3,58 # Get CSSR0
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	958 stw r3,CYGARC_PPCREG_PC(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	959 mfspr r3,59 # Get CSSR1
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	960 stw r3,CYGARC_PPCREG_MSR(sp)
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	961
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	962 b cyg_hal_default_interrupt_vsr_common
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	963
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	964 #endif
842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	965
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	966 ##-----------------------------------------------------------------------------
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	967 ## Execute pending DSRs on the interrupt stack with interrupts enabled.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	968 ## Note: this can only be called from code running on a thread stack
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	969
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	970 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	971 .extern cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	972
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	973 FUNC_START(hal_interrupt_stack_call_pending_DSRs)
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	974 # Change to interrupt stack, save state and set up stack for
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	975 # calls to C code.
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	976 mr r3,sp
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	977 lwi r4,__interrupt_stack
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	978 subi r4,r4,24 # make space on stack
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	979 mr sp,r4
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	980 stw r3,12(sp) # save old sp
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	981 mfmsr r3
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	982 stw r3,16(sp) # save old MSR
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	983 mflr r3
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	984 stw r3,20(sp) # save old LR
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	985
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	986 li r0,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	987 stw r0,0(sp) # clear back chain
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	988 stw r0,8(sp) # zero return pc
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	989
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	990 hal_cpu_int_enable
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	991
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	992 # Call into kernel which will execute DSRs
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	993 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp)
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	994 bl cyg_interrupt_call_pending_DSRs
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	995 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	996
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	997 lwz r3,20(sp) # restore LR
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	998 mtlr r3
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	999 lwz r5,12(sp) # get SP from saved state
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	1000 lwz r3,16(sp) # restore interrupt setting
2883 842a82a508f3 Add Book E architecture support. See the ChangeLog for full details. nickg parents: 2729 diff changeset	1001 hal_cpu_int_merge r3,r4
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	1002
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	1003 mr sp,r5 # restore stack pointer
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	1004 blr # and return to caller
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 72 diff changeset	1005 #endif
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	1006
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	1007 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1008 ## Temporary interrupt stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1009
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1010 .section ".bss"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1011
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1012 .balign 16
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1013 .global cyg_interrupt_stack_base
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1014 cyg_interrupt_stack_base:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1015 __interrupt_stack_base:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1016 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1017 .byte 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1018 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1019 .balign 16
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1020 .global cyg_interrupt_stack
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	1021 cyg_interrupt_stack:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1022 __interrupt_stack:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1023
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1024 .long 0,0,0,0,0,0,0,0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1025
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	1026 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1027 # end of vectors.S

Mercurial > nand-ecoscentric

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 3403:8c8767bb9a62 default tip