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devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.
author Ross Younger <wry@ecoscentric.com>
date Sun, 18 Jan 2015 17:59:01 +1300
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 ##=============================================================================
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2 ##
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3 ## mbx.S
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4 ##
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5 ## MBX board hardware setup
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6 ##
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7 ##=============================================================================
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8 ## ####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later
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16 ## version.
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17 ##
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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19 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 ## for more details.
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22 ##
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23 ## You should have received a copy of the GNU General Public License
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24 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 ##
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27 ## As a special exception, if other files instantiate templates or use
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28 ## macros or inline functions from this file, or you compile this file
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29 ## and link it with other works to produce a work based on this file,
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30 ## this file does not by itself cause the resulting work to be covered by
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31 ## the GNU General Public License. However the source code for this file
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32 ## must still be made available in accordance with section (3) of the GNU
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33 ## General Public License v2.
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34 ##
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35 ## This exception does not invalidate any other reasons why a work based
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36 ## on this file might be covered by the GNU General Public License.
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37 ## -------------------------------------------
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38 ## ####ECOSGPLCOPYRIGHTEND####
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39 ##=============================================================================
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40 #######DESCRIPTIONBEGIN####
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41 ##
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42 ## Author(s): hmt
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43 ## Contributors:hmt
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44 ## Date: 1999-06-08
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45 ## Purpose: MBX board hardware setup
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46 ## Description: This file contains any code needed to initialize the
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47 ## hardware on a MBX860 or 821 PowerPC board.
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48 ##
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49 ######DESCRIPTIONEND####
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50 ##
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51 ##=============================================================================
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52
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53 #include <pkgconf/system.h>
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54 #include <pkgconf/hal.h>
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55 #include <pkgconf/hal_powerpc.h>
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56 #include <pkgconf/hal_powerpc_mbx.h>
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57
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58 #include <cyg/hal/arch.inc> /* register symbols et al */
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59 #include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
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60 /* registers, IMM layout... */
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61 #include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
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62
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63 #------------------------------------------------------------------------------
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64 # this is kept thus for commonality with CygMon code
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66 #if 40 == CYGHWR_HAL_POWERPC_BOARD_SPEED
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67 # define __40MHZ 1
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68 #elif 50 == CYGHWR_HAL_POWERPC_BOARD_SPEED
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69 # define __50MHZ 1
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70 #else
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71 # error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H
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72 #endif
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73
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74 #------------------------------------------------------------------------------
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75 # this is controlled with one define for tidiness:
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76 # (and it is undefined by default)
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77
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78 //#define CYGPRI_RAM_START_PROGRAMS_UPMS
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79
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80 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
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81 # define CYGPRI_DO_PROGRAM_UPMS
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82 #endif
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83
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84 #if defined(CYGPRI_RAM_START_PROGRAMS_UPMS) && defined(CYGSEM_HAL_ROM_MONITOR)
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85 /* use old tables in a StubROM build iff RAM start will reprogram them */
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86 # define CYGPRI_USE_OLD_UPM_TABLES
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87 #endif
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88
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89 /* The intention is that we only set up the UPMs in ROM start, be it actual
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90 * ROM application start or Stub ROMs that we built from the same sources.
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91 *
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92 * The alternative approach - in which we have reliability doubts - is to
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93 * program the UPMs with *old* timing data in StubROM start, then
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94 * *reprogram* them with *new* timing data in RAM start - and of course
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95 * program with *new* timing data in plain ROM application start.
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96 * (Re-programming from new to new timing data fails - hence the suspicion
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97 * of reprogramming _at_all_, hence this private configuration)
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98 *
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99 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
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100 * - programming the UPMs exactly once - is obtained. Define it to get the
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101 * latter, untrusted behaviour.
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102 */
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103
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104 #------------------------------------------------------------------------------
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105
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106 // LED macro uses r3, r5: r4 left alone
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107 #define LED( x ) \
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108 lwi r5,0xfa100001; \
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109 lwi r3,((x) & 0xe); \
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110 stb r3,0(r5)
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111
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112
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113 #------------------------------------------------------------------------------
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114
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115 FUNC_START( hal_hardware_init )
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116
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117 # Throughout this routine, r4 is the base address of the control
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118 # registers. r3 and r5 are scratch in general.
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119
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120 lwi r4,CYGARC_REG_IMM_BASE # base address of control registers
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121 mtspr CYGARC_REG_IMMR,r4
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122
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123 LED( 0 ) # turn all LEDs on
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124
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125 #define CACHE_UNLOCKALL 0x0a00
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126 #define CACHE_DISABLE 0x0400
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127 #define CACHE_INVALIDATEALL 0x0c00
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128 #define CACHE_ENABLE 0x0200
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129 #define CACHE_ENABLEBIT 0x8000
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130
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131 #define CACHE_FORCEWRITETHROUGH 0x0100
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132 #define CACHE_NOWRITETHROUGH 0x0300
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133 #define CACHE_CLEAR_LE_SWAP 0x0700
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134
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135 # DATA CACHE
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136 mfspr r3,CYGARC_REG_DC_CST /* clear error bits */
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137 lis r3,CACHE_UNLOCKALL
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138 sync
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139 mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */
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140
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141 lis r3,CACHE_INVALIDATEALL
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142 sync
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143 mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */
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144
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145 lis r3,CACHE_DISABLE
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146 sync
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147 mtspr CYGARC_REG_DC_CST,r3 /* disable */
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148
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149 lis r3,CACHE_FORCEWRITETHROUGH
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150 sync
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151 mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */
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152
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153 lis r3,CACHE_CLEAR_LE_SWAP
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154 sync
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155 mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */
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156 /* (dunno what this is, but it sounds like a bad thing) */
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157
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158 # INSTRUCTION CACHE (no writeback modes)
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159 mfspr r3,CYGARC_REG_IC_CST /* clear error bits */
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160 lis r3,CACHE_UNLOCKALL
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161 mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */
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162 isync
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163 lis r3,CACHE_INVALIDATEALL
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164 mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */
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165 isync
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166 lis r3,CACHE_DISABLE
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167 mtspr CYGARC_REG_IC_CST,r3 /* disable */
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168 isync
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169
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170 sync
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171
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172 /*
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173 * SIU Initialization.
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174 */
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175 /* lwi r3,0x0062A900*/
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176 /* lwi r3,0x006A2900*/
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177 lwi r3,0x00602400
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178 stw r3,SIUMCR(r4)
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179
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180 /*
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181 * Enable bus monitor. Disable Watchdog timer.
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182 */
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183 lwi r3,0xffffff88
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184 stw r3,SYPCR(r4)
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185
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186 /*
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187 * Clear REFA & REFB. Enable but freeze timebase.
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188 */
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189 lwi r3,0x00c2
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190 sth r3,TBSCR(r4)
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191
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192 /*
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193 * Unlock some RTC registers (see section 5.11.2)
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194 */
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195 lwi r3,0x55ccaa33
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196 stw r3,RTCSCK(r4)
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197 stw r3,RTCK(r4)
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198 stw r3,RTSECK(r4)
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199 stw r3,RTCALK(r4)
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200
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201 /*
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202 * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
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203 */
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204 li r3,0x00c3
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205 sth r3,RTCSC(r4)
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206
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207 /*
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208 * Clear periodic timer interrupt status.
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209 * Enable periodic timer and stop it on freeze.
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210 */
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211 li r3,0x0083
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212 sth r3,PISCR(r4)
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213
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214 #ifdef CYGPRI_DO_PROGRAM_UPMS
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215 /*
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216 * Perform UPM programming by writing to its 64 RAM locations.
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217 * Note that UPM initialization must be done before the Bank Register
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218 * initialization. Otherwise, system may hang when writing to Bank
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219 * Registers in certain cases.
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220 */
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221 lis r5,__upmtbl_start@h
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222 ori r5,r5,__upmtbl_start@l
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223 lis r6,__upmtbl_end@h
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224 ori r6,r6,__upmtbl_end@l
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225 sub r7,r6,r5 /* size of table */
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226 srawi r7,r7,2 /* in words */
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227
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228 li r6,0x0000 /* Command - OP=Write, UPMA, MAD=0 */
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229 1:
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230 lwz r3,0(r5) /* get data from table */
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231 stw r3,MDR(r4) /* store the data to MD register */
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232 stw r6,MCR(r4) /* issue command to MCR register */
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233 addi r5,r5,4 /* next entry in the table */
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234 addi r6,r6,1 /* next MAD address */
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235 cmpw r6,r7 /* done yet ? */
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236 blt 1b
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237 #endif // CYGPRI_DO_PROGRAM_UPMS
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238
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239 /*
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240 * Set refresh timer prescaler to divide by 8.
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241 */
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242 li r3,PTP_DIV32
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243 sth r3,MPTPR(r4)
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244
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245 /*
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246 * See Table 15-16 MPC860 User's Manual.
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247 *
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248 * PTA = 0x13 (clock dependent)
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249 * PTAE = enabled
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250 * AMA = 0
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251 * DSA = 2 cycle disable
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252 * G0CLA = A12
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253 * GPL_A4DIS = 0
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254 * RLFA = 0
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255 * WLFA = 0
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256 * TLFA = 0
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257 */
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258 #ifdef __50MHZ
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259 lwi r3,0x18801000
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260 #else
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261 lwi r3,0x13801000
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262 #endif
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263 stw r3,MAMR(r4)
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264
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265 /*
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266 * Base Register initialization.
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267 */
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268 /* BOOT ROM */
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269 lwi r3,0xfe000401 # 8-bit, GPCM
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270 #ifdef __50MHZ
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271 lwi r5,0xff800960 /* for 120nS devices, else 0xff800940 */
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272 #else
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273 lwi r5,0xff800930
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274 #endif
38
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275 #ifdef CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH
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276 // Then the 32-bit FLASH device is on CS0, the "ROM" is on CS7
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277 stw r3,BR7(r4)
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278 stw r5,OR7(r4)
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279 #else // Boot from 8-bit ROM - the default, on CS0
32
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280 stw r3,BR0(r4)
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281 stw r5,OR0(r4)
38
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282 #endif
32
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283 /* ONBOARD DRAM */
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284 lwi r3,0x00000081 # 32-bit, UPMA
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285 lwi r5,0xffc00400
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286 stw r3,BR1(r4)
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287 stw r5,OR1(r4)
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288
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289 /* DRAM DIMM BANK0 */
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290 lwi r3,0x00000080 # 32-bit, UPMA, INVALID
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291 lwi r5,0x00000400
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292 stw r3,BR2(r4)
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293 stw r5,OR2(r4)
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294
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295 /* DRAM DIMM BANK1 */
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296 lwi r3,0x00000080 # 32-bit, UPMA, INVALID
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297 lwi r5,0x00000400
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298 stw r3,BR3(r4)
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299 stw r5,OR3(r4)
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300
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301 /* NVRAM */
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302 lwi r3,0xfa000401 # 8-bit, GPCM
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303 #ifdef __50MHZ
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304 lwi r5,0xffe00930
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305 #else
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306 lwi r5,0xffe00920
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307 #endif
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308 stw r3,BR4(r4)
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309 stw r5,OR4(r4)
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310
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311 /* PCI BRIDGE MEM/IO */
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312 lwi r3,0x80000001 # 32-bit, GPCM
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313 lwi r5,0xa0000108
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314 stw r3,BR5(r4)
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315 stw r5,OR5(r4)
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316
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317 /* PCI BRIDGE REGISTERS */
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318 lwi r3,0xfa210001 # 32-bit, GPCM
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319 lwi r5,0xffff0108
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320 stw r3,BR6(r4)
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321 stw r5,OR6(r4)
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322
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323 /* FLASH */
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324 lwi r3,0xfc000001 # 32-bit, GPCM
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325 #ifdef __50MHZ
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326 lwi r5,0xff800940
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327 #else
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328 lwi r5,0xff800930
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329 #endif
38
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330 #ifdef CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH
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331 // Then the 32-bit FLASH device is on CS0, the "ROM" is on CS7
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332 stw r3,BR0(r4)
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333 stw r5,OR0(r4)
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334 #else // Boot from 8-bit ROM - so the 32-bit FLASH is on CS7
32
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335 stw r3,BR7(r4)
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336 stw r5,OR7(r4)
38
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337 #endif
32
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338 /*
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339 * SYSTEM CLOCK CONTROL REGISTER
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340 *
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341 * COM (1:2) = 0
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342 * TBS (6) = 1
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343 * RTDIV (7) = 0
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344 * RTSEL (8) = 0
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345 * CRQEN (9) = 0
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346 * PRQEN (10) = 0
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347 * EBDF (13:14) = 0
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348 * DFSYNC(17:18) = 0
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349 * DFBRG (19:20) = 0
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350 * DFNL (21:23) = 0
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351 * DFNH (24:26) = 0
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352 */
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353 lwi r3,0x02000000
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354 stw r3,SCCR(r4)
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355
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356 /*
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357 * The following sets up a 40MHz CPU clock.
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358 * I've seen 2 variations of MBX boards. One
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359 * uses a direct feed (1:1) 40MHz clock on
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360 * EXTCLK inputs. The other uses a 32KHz
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361 * oscillator on the OSCM inputs.
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362 */
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363 lwz r3,PLPRCR(r4)
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364 rlwinm r3,r3,12,20,31
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365 cmpwi r3,0
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366 beq 1f
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367
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368 /*
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369 * PLL, LOW POWER, AND RESET CONTROL REGISTER
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370 *
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371 * MF (0:11) = depends on source clock
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372 * SPLSS (16) = 1
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373 * TEXPS (17) = 1
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374 * TMIST (19) = 1
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375 * CSRC (21) = 0
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376 * LPM (22:23) = 0
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377 * CSR (24) = 0
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378 * LOLRE (25) = 0
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379 * FIOPD (26) = 0
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380 */
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381 /* MF (0:11) = 0x4c4 = 1220 = (40MHz/32.768KHz) */
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382 #ifdef __50MHZ
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383 lwi r3,0x5f50d000
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384 #else
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385 lwi r3,0x4c40d000
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386 #endif
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387 b 2f
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388 1:
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389 /* MF (0:11) = 0x000 = 1 = (1:1) */
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390 lwi r3,0x0000d000
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391 2:
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392 stw r3,PLPRCR(r4)
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393
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394 # mask interrupt sources in the SIU
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395 lis r2,0
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396 lwi r3,CYGARC_REG_IMM_SIMASK
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397 stw r2,0(r3)
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398
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399 # set the decrementer to maxint
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400 lwi r2,0
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401 not r2,r2
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402 mtdec r2
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403
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404 # and enable the timebase and decrementer to make sure
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405 li r2,1 # TBEnable and not TBFreeze
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406 lwi r3,CYGARC_REG_IMM_TBSCR
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407 sth r2,0(r3)
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408
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409 LED( 8 ) # turn red led off
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410
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411 #ifdef CYG_HAL_STARTUP_ROM
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412 # move return address to where the ROM is
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413 mflr r3
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414 andi. r3,r3,0xffff
115
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415 oris r3,r3,CYGMEM_REGION_rom>>16
32
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416 mtlr r3
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417 #endif
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418
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419 blr
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420 FUNC_END( hal_hardware_init )
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421
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422
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423 #ifdef CYGPRI_DO_PROGRAM_UPMS
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424 # -------------------------------------------------------------------------
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425 # this table initializes the User Programmable Machine (UPM) nastiness
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426 # in the QUICC to control DRAM timing.
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427
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428 __upmtbl_start:
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429
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430 #ifdef __25MHZ
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431 /* UPM contents for 25MHz clk. DRAM: EDO,4K,60ns */
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432
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433 /* Single read. (offset 0 in upm RAM) */
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434 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
435 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
436
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
437 /* Burst read. (offset 8 in upm RAM) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
438 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
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jlarmour
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diff changeset
439 .long 0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
440 .long 0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
441 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
442
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
443 /* Single write. (offset 18 in upm RAM) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
444 .long 0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x33ff6c0f
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jlarmour
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diff changeset
445 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
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diff changeset
446
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jlarmour
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diff changeset
447 /* Burst write. (offset 20 in upm RAM) */
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diff changeset
448 .long 0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x03ff2c0c
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449 .long 0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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450 .long 0x08ff2c00, 0x33ff6c0f, 0xffffec07, 0xffffec07
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451 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
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452
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jlarmour
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diff changeset
453 /* Refresh (offset 30 in upm RAM) */
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diff changeset
454 .long 0xc0ffec04, 0x07ffec04, 0x3fffec07, 0xffffec07
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455 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
456 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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457
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458 /* Exception. (offset 3c in upm RAM) */
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diff changeset
459 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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460 #endif
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461
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462 #ifdef __33MHZ
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463 /* UPM contents for 33MHz clk. DRAM: EDO,4K,60ns */
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diff changeset
464
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jlarmour
parents:
diff changeset
465 /* Single read. (offset 0 in upm RAM) */
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diff changeset
466 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
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467 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
468
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jlarmour
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diff changeset
469 /* Burst read. (offset 8 in upm RAM) */
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diff changeset
470 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
471 .long 0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
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472 .long 0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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473 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
474
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jlarmour
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diff changeset
475 /* Single write. (offset 18 in upm RAM) */
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diff changeset
476 .long 0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x33ff6c07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
477 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
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diff changeset
478
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jlarmour
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diff changeset
479 /* Burst write. (offset 20 in upm RAM) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
480 .long 0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x03ff2c0c
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diff changeset
481 .long 0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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482 .long 0x08ff2c00, 0x33ff6c07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
483 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
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diff changeset
484
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parents:
diff changeset
485 /* Refresh (offset 30 in upm RAM) */
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diff changeset
486 .long 0xc0ffec04, 0x03ffec04, 0x1fffec07, 0xffffec07
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487 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
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diff changeset
488 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
489
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jlarmour
parents:
diff changeset
490 /* Exception. (offset 3c in upm RAM) */
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diff changeset
491 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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492 #endif
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493
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diff changeset
494 #ifdef CYGPRI_USE_OLD_UPM_TABLES
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495
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jlarmour
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diff changeset
496 // BUT new tables received from motorola are further down
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jlarmour
parents:
diff changeset
497
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diff changeset
498 // And I just discovered a good reason for using the NEW TABLES:
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
499 // with the old tables, the cache zero-a-line command does not
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
500 // work. It only zeros the first 12 bytes of the line, not all 16.
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
501 // This may be related to having the cache set up write-through, as
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
502 // seems necessary to have it work on this platform.
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parents:
diff changeset
503
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diff changeset
504 #ifdef __40MHZ
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505 /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
506
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jlarmour
parents:
diff changeset
507 /* Single read. (offset 0 in upm RAM) */
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diff changeset
508 .long 0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
509 .long 0x03af2c08, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
510
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jlarmour
parents:
diff changeset
511 /* Burst read. (offset 8 in upm RAM) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
512 .long 0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
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jlarmour
parents:
diff changeset
513 .long 0x03af2c08, 0x0caf2c04, 0x00af2c04, 0x03af2c08
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
514 .long 0x0caf2c04, 0x00af2c04, 0x03af2c08, 0x0caf2c04
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
515 .long 0x00af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
516
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jlarmour
parents:
diff changeset
517 /* Single write. (offset 18 in upm RAM) */
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jlarmour
parents:
diff changeset
518 .long 0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
519 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
520
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
521 /* Burst write. (offset 20 in upm RAM) */
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diff changeset
522 .long 0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
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diff changeset
523 .long 0x0fff2c0c, 0x0cff2c00, 0x03ff2c0c, 0x0cff2c00
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
524 .long 0x03ff2c0c, 0x0cff2c00, 0x33ff6c07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
525 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
526
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jlarmour
parents:
diff changeset
527 /* Refresh (offset 30 in upm RAM) */
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jlarmour
parents:
diff changeset
528 .long 0xf0ffec04, 0x00ffec04, 0x0fffec04, 0x0fffec04
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jlarmour
parents:
diff changeset
529 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
530 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
531
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jlarmour
parents:
diff changeset
532 /* Exception. (offset 3c in upm RAM) */
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jlarmour
parents:
diff changeset
533 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
534 #endif
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jlarmour
parents:
diff changeset
535
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jlarmour
parents:
diff changeset
536 #ifdef __50MHZ
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jlarmour
parents:
diff changeset
537 /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
538
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
539 /* Single read. (offset 0 in upm RAM) */
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jlarmour
parents:
diff changeset
540 .long 0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
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jlarmour
parents:
diff changeset
541 .long 0x00af2c04, 0x0faf2c08, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
542
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jlarmour
parents:
diff changeset
543 /* Burst read. (offset 8 in upm RAM) */
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jlarmour
parents:
diff changeset
544 .long 0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
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diff changeset
545 .long 0x00af2c04, 0x0faf2c08, 0x0caf2c04, 0x00af2c04
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
546 .long 0x0faf2c08, 0x0caf2c04, 0x00af2c04, 0x0faf2c08
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
547 .long 0x0caf2c04, 0x00af2c04, 0x0faf2c08, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
548
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
549 /* Single write. (offset 18 in upm RAM) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
550 .long 0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
551 .long 0x00ff2c00, 0xffffec07, 0xffffec07, 0xffffec07
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
552
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
553 /* Burst write. (offset 20 in upm RAM) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
554 .long 0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
555 .long 0x00ff2c00, 0x0fff2c08, 0x0cff2c04, 0x00ff2c00
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
556 .long 0x0fff2c00, 0x0cff2c04, 0x00ff2c00, 0x0fff2c08
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
557 .long 0x0cff2c04, 0x00ff2c00, 0xffffec07, 0xffffec07
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jlarmour
parents:
diff changeset
558
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jlarmour
parents:
diff changeset
559 /* Refresh (offset 30 in upm RAM) */
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jlarmour
parents:
diff changeset
560 .long 0xf0ffec04, 0xc0ffec04, 0x00ffec04, 0x0fffec04
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561 .long 0x1fffec07, 0xffffec07, 0xffffec07, 0xffffec07
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562 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
563
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diff changeset
564 /* Exception. (offset 3c in upm RAM) */
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565 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
566 #endif
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567
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568 #else // !CYGPRI_USE_OLD_UPM_TABLES: use the NEW TABLES
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diff changeset
569
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570 // for RAM startup or ROM application when NOT making a stub rom,
62
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diff changeset
571 // ie. CYGSEM_HAL_ROM_MONITOR not defined.
32
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572
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573 #ifdef __40MHZ
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574 /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
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575 .long 0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x30af0c00
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576 .long 0xf1bf4805, 0xffffc005, 0xffffc005, 0xffffc005
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577
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578 .long 0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x03af0c08
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579 .long 0x0caf0c04, 0x03af0c08, 0x0caf0c04, 0x03af0c08
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580 .long 0x0caf0c04, 0x30af0c00, 0xf3bf4805, 0xffffc005
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diff changeset
581 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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582
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583 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x33ff4804
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diff changeset
584 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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585
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diff changeset
586 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
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587 .long 0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
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diff changeset
588 .long 0x0cff0c00, 0x33ff4804, 0xffffc005, 0xffffc005
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589 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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590
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591 .long 0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
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592 .long 0x3fffc004, 0xffffc005, 0xffffc005, 0xffffc005
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593 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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diff changeset
594
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diff changeset
595 .long 0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
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596 #endif
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597
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598 #ifdef __50MHZ
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599 /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
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600
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601 .long 0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x10af0c04
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diff changeset
602 .long 0xf0af0c00, 0xf3bf4805, 0xffffc005, 0xffffc005
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diff changeset
603
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604 .long 0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x00af0c04
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diff changeset
605 .long 0x07af0c08, 0x0caf0c04, 0x01af0c04, 0x0faf0c08
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diff changeset
606 .long 0x0caf0c04, 0x01af0c04, 0x0faf0c08, 0x0caf0c04
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diff changeset
607 .long 0x10af0c04, 0xf0afc000, 0xf3bf4805, 0xffffc005
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diff changeset
608
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609 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x13ff4804
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diff changeset
610 .long 0xffffc004, 0xffffc005, 0xffffc005, 0xffffc005
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611
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612 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
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613 .long 0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
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diff changeset
614 .long 0x0cff0c00, 0x13ff4804, 0xffffc004, 0xffffc005
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615 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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616
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617 .long 0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
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618 .long 0x1fffc004, 0xffffc004, 0xffffc005, 0xffffc005
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619 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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620
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621 .long 0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
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622 #endif
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623 #endif // OLD/NEW TABLES == CYGPRI_USE_OLD_UPM_TABLES or not.
62
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diff changeset
624 // depending on CYGSEM_HAL_ROM_MONITOR and whether RAM
32
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625 // start re-initializes.
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626
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627 __upmtbl_end:
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628 #endif // CYGPRI_DO_PROGRAM_UPMS
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629
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630 FUNC_START(hal_mbx_set_led)
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631 andi. r3,r3,0x0e
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632 lwi r4,0xfa100001
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633 stb r3,0(r4)
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634 blr
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635 FUNC_END(hal_mbx_set_led)
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636
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637 FUNC_START(hal_mbx_flash_led)
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diff changeset
638 lwi r4,0xfa100001
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639 1:
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640 li r5,10
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641 stb r5,0(r4)
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642
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643 lis r5,10
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644 mtctr r5
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645 2:
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646 bdnz 2b
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647
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648 li r5,12
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649 stb r5,0(r4)
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650
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651 lis r5,10
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diff changeset
652 mtctr r5
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653 3:
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654 bdnz 3b
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655
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656 subi r3,r3,1
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657 cmpwi r3,0
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658 bge 1b
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diff changeset
659
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diff changeset
660 li r5,6
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diff changeset
661 stb r5,0(r4)
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diff changeset
662
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663 lis r5,20
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664 mtctr r5
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665 4:
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666 bdnz 4b
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667
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668 blr
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669 FUNC_END(hal_mbx_flash_led)
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diff changeset
670
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671
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672 #------------------------------------------------------------------------------
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diff changeset
673 # end of mbx.S