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devs/nand/micron_mt29: Remove defunct references (in comments) to mt29f2g08_oob_ecc.
author Ross Younger <wry@ecoscentric.com>
date Sun, 18 Jan 2015 17:59:01 +1300
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_HAL_INTR_H
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2 #define CYGONCE_HAL_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // hal_intr.h
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7 //
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8 // HAL Interrupt and clock support
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9 //
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10 //==========================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
208
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): jskov
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46 // Contributors: jskov,
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47 // Date: 1999-04-24
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48 // Purpose: Define Interrupt support
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // interrupts and the clock.
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51 //
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52 // Usage:
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53 // #include <cyg/hal/hal_intr.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //==========================================================================
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60
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61 #include <pkgconf/hal.h>
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62
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63 #include <cyg/hal/var_intr.h>
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65 // More include statements below. First part of this file must be
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66 // usable for both assembly and C files, so only use defines here.
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67
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68 #include CYGBLD_HAL_VAR_INTR_MODEL_H
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70 #ifndef __ASSEMBLER__
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71
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72 #include <cyg/infra/cyg_type.h>
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73
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74 #include <cyg/hal/sh_regs.h> // register definitions
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75 #include <cyg/hal/hal_io.h> // io macros
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76 #include <cyg/infra/cyg_ass.h> // CYG_FAIL
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77
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78 //--------------------------------------------------------------------------
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79 // Static data used by HAL
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80
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81 // ISR tables
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82 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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83 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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84 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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85 // VSR table
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86 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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87
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88 //--------------------------------------------------------------------------
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89 // Default ISR
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90 // The #define is used to test whether this routine exists, and to allow
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91 // us to call it.
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93 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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95 #define HAL_DEFAULT_ISR hal_default_isr
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96
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97 //--------------------------------------------------------------------------
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98 // Interrupt state storage
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99
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100 typedef cyg_uint32 CYG_INTERRUPT_STATE;
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101
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102 //--------------------------------------------------------------------------
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103 // Interrupt control macros
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104 //
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105 // Note that these macros control interrupt state by setting the Imask
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106 // of the SR rather than the (more obvious) BL. This is because a CPU
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107 // reset is forced if execptions (such as breakpoints) are generated
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108 // while the BL flag is set.
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109
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110 #define HAL_DISABLE_INTERRUPTS(_old_) \
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111 CYG_MACRO_START \
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112 cyg_uint32 _tmp_; \
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113 asm volatile ( \
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114 "stc sr,%1 \n\t" \
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115 "mov %2,%0 \n\t" \
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116 "and %1,%0 \n\t" \
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117 "or %2,%1 \n\t" \
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118 "ldc %1,sr \n\t" \
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119 : "=&r"(_old_), "=&r" (_tmp_) \
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120 : "r" (CYGARC_REG_SR_IMASK) \
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121 ); \
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122 CYG_MACRO_END
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123
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124 #define HAL_ENABLE_INTERRUPTS() \
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125 CYG_MACRO_START \
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126 cyg_uint32 _tmp_; \
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127 asm volatile ( \
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128 "stc sr,%0 \n\t" \
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129 "and %1,%0 \n\t" \
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130 "ldc %0,sr \n\t" \
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131 : "=&r" (_tmp_) \
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132 : "r" (~CYGARC_REG_SR_IMASK) \
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133 ); \
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134 CYG_MACRO_END
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135
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136 #define HAL_RESTORE_INTERRUPTS(_old_) \
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137 CYG_MACRO_START \
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138 cyg_uint32 _tmp1_, _tmp2_; \
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139 asm volatile ( \
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140 "stc sr,%0 \n\t" \
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141 "and %3,%0 \n\t" \
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142 "not %3,%1 \n\t" \
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143 "and %2,%1 \n\t" \
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144 "or %1,%0 \n\t" \
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145 "ldc %0,sr \n\t" \
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146 : "=&r" (_tmp1_), "=&r" (_tmp2_) \
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147 : "r" (_old_), "r" (~CYGARC_REG_SR_IMASK) \
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148 ); \
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149 CYG_MACRO_END
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150
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151 #define HAL_QUERY_INTERRUPTS(_old_) \
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152 CYG_MACRO_START \
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153 asm volatile ( \
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154 "stc sr,%0 \n\t" \
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155 "and %1,%0 \n\t" \
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156 : "=&r"(_old_) \
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157 : "r" (CYGARC_REG_SR_IMASK) \
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158 ); \
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159 CYG_MACRO_END
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160
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161 //--------------------------------------------------------------------------
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162 // Vector translation.
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163
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164 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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165
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166 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
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167
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168 #else
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169
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170 # define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
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171
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172 #endif
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173
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174 //--------------------------------------------------------------------------
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175 // Routine to execute DSRs using separate interrupt stack
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176
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177 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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178
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179 externC void hal_interrupt_stack_call_pending_DSRs(void);
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180 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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181 hal_interrupt_stack_call_pending_DSRs()
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182
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183 // these are offered solely for stack usage testing
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184 // if they are not defined, then there is no interrupt stack.
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185 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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186 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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187 // use them to declare these extern however you want:
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188 // extern char HAL_INTERRUPT_STACK_BASE[];
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189 // extern char HAL_INTERRUPT_STACK_TOP[];
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190 // is recommended
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191 #endif
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192
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193 //--------------------------------------------------------------------------
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194 // Interrupt and VSR attachment macros
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195
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196 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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197 CYG_MACRO_START \
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198 cyg_uint32 _index_; \
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199 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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200 \
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201 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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202 (_state_) = 0; \
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203 else \
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204 (_state_) = 1; \
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205 CYG_MACRO_END
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206
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207 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
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208 CYG_MACRO_START \
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209 cyg_uint32 _index_; \
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210 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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211 \
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212 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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213 { \
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214 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
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215 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
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216 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
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217 } \
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218 CYG_MACRO_END
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219
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220 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
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221 CYG_MACRO_START \
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222 cyg_uint32 _index_; \
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223 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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224 \
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225 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
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226 { \
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227 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
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228 hal_interrupt_data[_index_] = 0; \
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229 hal_interrupt_objects[_index_] = 0; \
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230 } \
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231 CYG_MACRO_END
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232
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233 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
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234 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
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235
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236
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237 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
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238 CYG_MACRO_START \
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239 if( _poldvsr_ != NULL ) \
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240 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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241 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
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242 CYG_MACRO_END
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243
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244 // This is an ugly name, but what it means is: grab the VSR back to eCos
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245 // internal handling, or if you like, the default handler. But if
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246 // cooperating with GDB and CygMon, the default behaviour is to pass most
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247 // exceptions to CygMon. This macro undoes that so that eCos handles the
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248 // exception. So use it with care.
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249
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250 externC void cyg_hal_default_interrupt_vsr( void );
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251 externC void cyg_hal_default_exception_vsr( void );
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252 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) \
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253 CYG_MACRO_START \
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254 if( (void*)_poldvsr_ != (void*)NULL ) \
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255 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
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256 hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
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257 ? (CYG_ADDRESS)cyg_hal_default_interrupt_vsr \
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258 : (CYG_ADDRESS)cyg_hal_default_exception_vsr ); \
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259 CYG_MACRO_END
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260
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261
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262 //--------------------------------------------------------------------------
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263 // Interrupt controller(s) access
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264 //
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265
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266 externC void hal_interrupt_set_level(int, int);
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267 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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268 hal_interrupt_set_level(_vector_, _level_);
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269
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270 externC void hal_interrupt_mask(int);
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271 #define HAL_INTERRUPT_MASK( _vector_ ) \
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272 hal_interrupt_mask(_vector_);
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273
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274 externC void hal_interrupt_unmask(int);
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275 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
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276 hal_interrupt_unmask(_vector_);
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277
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278 externC void hal_interrupt_acknowledge(int);
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279 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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280 hal_interrupt_acknowledge(_vector_);
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281
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282 externC void hal_interrupt_configure(int, int, int);
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283 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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284 hal_interrupt_configure(_vector_, _level_, _up_);
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285
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286 #endif // __ASSEMBLER__
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287
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288 //--------------------------------------------------------------------------
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289 #endif // ifndef CYGONCE_HAL_INTR_H
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290 // End of hal_intr.h