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comparison packages/hal/mips/arch/current/include/hal_arch.h @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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children 443894e2e912
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1 #ifndef CYGONCE_HAL_HAL_ARCH_H
2 #define CYGONCE_HAL_HAL_ARCH_H
3
4 //=============================================================================
5 //
6 // hal_arch.h
7 //
8 // Architecture specific abstractions
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): nickg
36 // Contributors: nickg
37 // Date: 1998-02-05
38 // Purpose: Define architecture abstractions
39 // Usage: #include <cyg/hal/hal_arch.h>
40 //
41 //####DESCRIPTIONEND####
42 //
43 //=============================================================================
44
45 #include <cyg/infra/cyg_type.h>
46
47 //-----------------------------------------------------------------------------
48 // Processor saved states:
49 // The layout of this structure is also defined in "mips.inc", for assembly
50 // code. Do not change this without changing that (or vice versa).
51
52 typedef struct
53 {
54 // These are common to all saved states
55 cyg_uint32 d[32]; /* Data regs */
56 cyg_uint32 hi; /* hi word of mpy/div reg */
57 cyg_uint32 lo; /* lo word of mpy/div reg */
58
59 // These are only saved for exceptions and interrupts
60 cyg_uint32 vector; /* Vector number */
61 cyg_uint32 pc; /* Program Counter */
62 cyg_uint32 sr; /* Status Reg */
63 cyg_uint32 cache; /* Cache control register */
64
65
66 // These are only saved for exceptions, and are not restored
67 // when continued.
68 cyg_uint32 cause; /* Exception cause register */
69 cyg_uint32 badvr; /* Bad virtual address reg */
70 cyg_uint32 prid; /* Processor Version */
71 cyg_uint32 config; /* Config register */
72 } HAL_SavedRegisters;
73
74 //-----------------------------------------------------------------------------
75 // Exception handling function.
76 // This function is defined by the kernel according to this prototype. It is
77 // invoked from the HAL to deal with any CPU exceptions that the HAL does
78 // not want to deal with itself. It usually invokes the kernel's exception
79 // delivery mechanism.
80
81 externC void deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
82
83 //-----------------------------------------------------------------------------
84 // Bit manipulation macros
85
86 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
87 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
88
89 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
90
91 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
92
93 //-----------------------------------------------------------------------------
94 // Context Initialization
95 // Initialize the context of a thread.
96 // Arguments:
97 // _sparg_ name of variable containing current sp, will be written with new sp
98 // _thread_ thread object address, passed as argument to entry point
99 // _entry_ entry point address.
100 // _id_ bit pattern used in initializing registers, for debugging.
101
102 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
103 { \
104 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56; \
105 register HAL_SavedRegisters *_regs_; \
106 int _i_; \
107 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
108 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \
109 (_regs_)->d[29] = (CYG_WORD)(_sp_); /* SP = top of stack */ \
110 (_regs_)->d[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \
111 (_regs_)->lo = 0; /* LO = 0 */ \
112 (_regs_)->hi = 0; /* HI = 0 */ \
113 (_regs_)->d[30] = (CYG_WORD)(_sp_); /* FP = top of stack */ \
114 (_regs_)->d[31] = (CYG_WORD)(_entry_); /* LR(d[31]) = entry point */ \
115 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \
116 _sparg_ = (CYG_ADDRESS)_regs_; \
117 }
118
119 //-----------------------------------------------------------------------------
120 // Context switch macros.
121 // The arguments are pointers to locations where the stack pointer
122 // of the current thread is to be stored, and from where the sp of the
123 // next thread is to be fetched.
124
125 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
126 externC void hal_thread_load_context( CYG_ADDRESS to )
127 __attribute__ ((noreturn));
128
129 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
130 hal_thread_switch_context((CYG_ADDRESS)_tspptr_,(CYG_ADDRESS)_fspptr_);
131
132 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
133 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
134
135 //-----------------------------------------------------------------------------
136 // Execution reorder barrier.
137 // When optimizing the compiler can reorder code. In multithreaded systems
138 // where the order of actions is vital, this can sometimes cause problems.
139 // This macro may be inserted into places where reordering should not happen.
140 // The "memory" keyword is potentially unnecessary, but it is harmless to
141 // keep it.
142
143 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
144
145 //-----------------------------------------------------------------------------
146 // Breakpoint support
147 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen if
148 // executed.
149 // HAL_BREAKINST is the value of the breakpoint instruction and HAL_BREAKINST_SIZE
150 // is its size in bytes.
151
152 #define HAL_BREAKPOINT(_label_) \
153 asm volatile (" .globl " #_label_ ";" \
154 #_label_":" \
155 " break 5" \
156 );
157
158 #define HAL_BREAKINST 0x0005000d
159
160 #define HAL_BREAKINST_SIZE 4
161
162 //-----------------------------------------------------------------------------
163 // Thread register state manipulation for GDB support.
164
165 // Translate a stack pointer as saved by the thread context macros above into
166 // a pointer to a HAL_SavedRegisters structure.
167 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
168 (_regs_) = (HAL_SavedRegisters *)(_sp_)
169
170 // Copy a set of registers from a HAL_SavedRegisters structure into a
171 // GDB ordered array.
172 #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
173 { \
174 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
175 int _i_; \
176 \
177 for( _i_ = 0; _i_ < 32; _i_++ ) \
178 _regval_[_i_] = (_regs_)->d[_i_]; \
179 \
180 _regval_[32] = (_regs_)->sr; \
181 _regval_[33] = (_regs_)->lo; \
182 _regval_[34] = (_regs_)->hi; \
183 _regval_[35] = (_regs_)->badvr; \
184 _regval_[36] = (_regs_)->cause; \
185 _regval_[37] = (_regs_)->pc; \
186 }
187
188 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
189 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
190 { \
191 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
192 int _i_; \
193 \
194 for( _i_ = 0; _i_ < 32; _i_++ ) \
195 (_regs_)->d[_i_] = _regval_[_i_]; \
196 \
197 (_regs_)->sr = _regval_[32]; \
198 (_regs_)->lo = _regval_[33]; \
199 (_regs_)->hi = _regval_[34]; \
200 (_regs_)->badvr = _regval_[35]; \
201 (_regs_)->cause = _regval_[36]; \
202 (_regs_)->pc = _regval_[37]; \
203 }
204
205 //-----------------------------------------------------------------------------
206 // HAL setjmp
207
208 #define HAL_JMP_BUF_SIZE 11
209
210 typedef cyg_uint32 hal_jmp_buf[HAL_JMP_BUF_SIZE];
211
212 externC int hal_setjmp(hal_jmp_buf env);
213 externC void hal_longjmp(hal_jmp_buf env, int val);
214
215 //-----------------------------------------------------------------------------
216 // Idle thread code.
217 // This macro is called in the idle thread loop, and gives the HAL the
218 // chance to insert code. Typical idle thread behaviour might be to halt the
219 // processor.
220
221 externC void hal_idle_thread_action(cyg_uint32 loop_count);
222
223 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
224
225 //-----------------------------------------------------------------------------
226 #endif // CYGONCE_HAL_HAL_ARCH_H
227 // End of hal_arch.h
228
229