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comparison packages/hal/powerpc/arch/current/include/hal_intr.h @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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1 #ifndef CYGONCE_HAL_INTR_H
2 #define CYGONCE_HAL_INTR_H
3
4 //=============================================================================
5 //
6 // hal_intr.h
7 //
8 // HAL Interrupt and clock support
9 //
10 //=============================================================================
11 //####COPYRIGHTBEGIN####
12 //
13 // -------------------------------------------
14 // The contents of this file are subject to the Cygnus eCos Public License
15 // Version 1.0 (the "License"); you may not use this file except in
16 // compliance with the License. You may obtain a copy of the License at
17 // http://sourceware.cygnus.com/ecos
18 //
19 // Software distributed under the License is distributed on an "AS IS"
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
21 // License for the specific language governing rights and limitations under
22 // the License.
23 //
24 // The Original Code is eCos - Embedded Cygnus Operating System, released
25 // September 30, 1998.
26 //
27 // The Initial Developer of the Original Code is Cygnus. Portions created
28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
29 // -------------------------------------------
30 //
31 //####COPYRIGHTEND####
32 //=============================================================================
33 //#####DESCRIPTIONBEGIN####
34 //
35 // Author(s): nickg
36 // Contributors: nickg
37 // Date: 1998-02-17
38 // Purpose: Define Interrupt support
39 // Description: The macros defined here provide the HAL APIs for handling
40 // interrupts and the clock.
41 //
42 // Usage:
43 // #include <cyg/hal/hal_intr.h>
44 // ...
45 //
46 //
47 //####DESCRIPTIONEND####
48 //
49 //=============================================================================
50
51 #include <pkgconf/hal.h>
52
53 #include <cyg/infra/cyg_type.h>
54
55 //-----------------------------------------------------------------------------
56 // PowerPC exception vectors.
57
58 #define CYG_VECTOR_RESERVED_0 0
59 #define CYG_VECTOR_RESET 1
60 #define CYG_VECTOR_MACHINE_CHECK 2
61 #define CYG_VECTOR_DSI 3
62 #define CYG_VECTOR_ISI 4
63 #define CYG_VECTOR_INTERRUPT 5
64 #define CYG_VECTOR_ALIGNMENT 6
65 #define CYG_VECTOR_PROGRAM 7
66 #define CYG_VECTOR_FP_UNAVAILABLE 8
67 #define CYG_VECTOR_DECREMENTER 9
68 #define CYG_VECTOR_RESERVED_A 10
69 #define CYG_VECTOR_RESERVED_B 11
70 #define CYG_VECTOR_SYSTEM_CALL 12
71 #define CYG_VECTOR_TRACE 13
72 #define CYG_VECTOR_FP_ASSIST 14
73
74 #ifdef CYG_HAL_POWERPC_MP860
75 #define CYG_VECTOR_RESERVED_F 15
76 #define CYG_VECTOR_SW_EMUL 16
77 #define CYG_VECTOR_ITLB_MISS 17
78 #define CYG_VECTOR_DTLB_MISS 18
79 #define CYG_VECTOR_ITLB_ERROR 19
80 #define CYG_VECTOR_DTLB_ERROR 20
81 #define CYG_VECTOR_RESERVED_15 21
82 #define CYG_VECTOR_RESERVED_16 22
83 #define CYG_VECTOR_RESERVED_17 23
84 #define CYG_VECTOR_RESERVED_18 24
85 #define CYG_VECTOR_RESERVED_19 25
86 #define CYG_VECTOR_RESERVED_1A 26
87 #define CYG_VECTOR_RESERVED_1B 27
88 #define CYG_VECTOR_DATA_BP 28
89 #define CYG_VECTOR_INSTRUCTION_BP 29
90 #define CYG_VECTOR_PERIPHERAL_BP 30
91 #define CYG_VECTOR_NMI 31
92 #endif
93
94
95
96 #define CYG_VSR_MIN 0
97 #define CYG_VSR_MAX 14
98 #define CYG_VSR_COUNT 15
99
100 #define CYG_ISR_MIN 0
101 #define CYG_ISR_MAX 14
102 #define CYG_ISR_COUNT 15
103
104 #ifdef CYG_HAL_POWERPC_MP860
105 #define CYG_EXCEPTION_MIN 0
106 #define CYG_EXCEPTION_MAX 31
107 #define CYG_EXCEPTION_COUNT 32
108 #else
109 #define CYG_EXCEPTION_MIN 0
110 #define CYG_EXCEPTION_MAX 14
111 #define CYG_EXCEPTION_COUNT 15
112 #endif
113
114
115 // The vector used by the Real time clock
116 #define CYG_VECTOR_RTC CYG_VECTOR_DECREMENTER
117
118 //-----------------------------------------------------------------------------
119 // Static data used by HAL
120
121 // ISR tables
122 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYG_ISR_COUNT];
123 externC volatile CYG_ADDRWORD hal_interrupt_data[CYG_ISR_COUNT];
124 externC volatile CYG_ADDRESS hal_interrupt_objects[CYG_ISR_COUNT];
125
126 // VSR table
127 externC volatile CYG_ADDRESS hal_vsr_table[CYG_VSR_COUNT];
128
129 //-----------------------------------------------------------------------------
130 // Default ISR
131
132 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
133
134 //-----------------------------------------------------------------------------
135 // Interrupt state storage
136
137 typedef cyg_uint32 CYG_INTERRUPT_STATE;
138
139 //-----------------------------------------------------------------------------
140 // Interrupt control macros
141
142 #define HAL_DISABLE_INTERRUPTS(_old_) \
143 asm volatile ( \
144 "mfmsr %0;" \
145 "lis 4,0;" \
146 "ori 4,4,0x8000 ;" \
147 "not 5,4;" \
148 "and 5,%0,5;" \
149 "mtmsr 5;" \
150 "and %0,%0,4" \
151 : "=r"(_old_) \
152 : \
153 : "r4", "r5" \
154 );
155
156 #define HAL_ENABLE_INTERRUPTS() \
157 asm volatile ( \
158 "mfmsr 3;" \
159 "lis 4,0;" \
160 "ori 4,4,0x8000 ;" \
161 "or 3,3,4;" \
162 "mtmsr 3;" \
163 : \
164 : \
165 : "r3", "r4" \
166 );
167
168 #define HAL_RESTORE_INTERRUPTS(_old_) \
169 asm volatile ( \
170 "mfmsr 3;" \
171 "lis 4,0;" \
172 "ori 4,4,0x8000 ;" \
173 "and 4,%0,4;" \
174 "or 4,3,4;" \
175 "mtmsr 4;" \
176 : \
177 : "r"(_old_) \
178 : "r3", "r4" \
179 );
180
181 // FIXME: using andi with side-effect on cc would be better but causes
182 // compiler problem.
183 #define HAL_QUERY_INTERRUPTS(_old_) \
184 asm volatile ( \
185 "mfmsr %0;" \
186 "lis 4,0;" \
187 "ori 4,4,0x8000;" \
188 "and %0,%0,4;" \
189 : "=r"(_old_) \
190 : \
191 : "r4" \
192 );
193
194 //-----------------------------------------------------------------------------
195 // Vector translation.
196 // Only one vector is available for external interrupts. No translation
197 // required.
198
199 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
200
201
202 //-----------------------------------------------------------------------------
203 // Interrupt and VSR attachment macros
204
205 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
206 CYG_MACRO_START \
207 cyg_uint32 _index_ = ((_vector_)>>3)&1; \
208 \
209 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
210 { \
211 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
212 hal_interrupt_data[_index_] = (CYG_ADDRWORD) _data_; \
213 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
214 } \
215 CYG_MACRO_END
216
217 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
218 CYG_MACRO_START \
219 cyg_uint32 _index_ = ((_vector_)>>3)&1; \
220 \
221 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
222 { \
223 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)hal_default_isr; \
224 hal_interrupt_data[_index_] = 0; \
225 hal_interrupt_objects[_index_] = 0; \
226 } \
227 CYG_MACRO_END
228
229 #define HAL_VSR_GET( _vector_, _pvsr_ ) \
230 *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
231
232
233 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
234 CYG_MACRO_START \
235 if( _poldvsr_ != NULL ) \
236 *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
237 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
238 CYG_MACRO_END
239
240 //-----------------------------------------------------------------------------
241 // Interrupt controller access
242
243 // These are not defined since individual interrupts cannot be masked
244 // without the help of an external interrupt controller.
245
246 #define HAL_INTERRUPT_MASK( _vector_ )
247
248 #define HAL_INTERRUPT_UNMASK( _vector_ )
249
250 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
251
252 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
253
254 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
255
256 //-----------------------------------------------------------------------------
257 // Clock control
258
259 #define HAL_CLOCK_INITIALIZE( _period_ ) \
260 CYG_MACRO_START \
261 cyg_uint32 period = _period_; \
262 asm volatile ( \
263 "mtdec %0;" \
264 : \
265 : "r"(period) \
266 ); \
267 CYG_MACRO_END
268
269 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
270 CYG_MACRO_START \
271 cyg_uint32 period = _period_; \
272 asm volatile ( \
273 "mtdec %0;" \
274 : \
275 : "r"(period) \
276 ); \
277 CYG_MACRO_END
278
279 #define HAL_CLOCK_READ( _pvalue_ ) \
280 CYG_MACRO_START \
281 register cyg_uint32 result; \
282 asm volatile( \
283 "mfdec %0;" \
284 : "=r"(result) \
285 ); \
286 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD-result; \
287 CYG_MACRO_END
288
289 //-----------------------------------------------------------------------------
290 #endif // ifndef CYGONCE_HAL_INTR_H
291 // End of hal_intr.h