Mercurial > nand-ecoscentric

comparison packages/hal/mn10300/arch/current/include/hal_cache.h @ 30:641b639be825 ecos-sw-1999-08-16

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Merge from eCos master repository on 1999-08-16-22:01:37-BST
author jlarmour
date Mon, 16 Aug 1999 22:10:49 +0000
parents 01ce82f3e11a
children e97d78785e2d
comparison
equal deleted inserted replaced
29:093762bd6ba9 30:641b639be825
47 // 47 //
48 //============================================================================= 48 //=============================================================================
49 49
50 #include <pkgconf/hal.h> 50 #include <pkgconf/hal.h>
51 #include <cyg/infra/cyg_type.h> 51 #include <cyg/infra/cyg_type.h>
52
53 #include <cyg/hal/var_cache.h>
52 54
53 //============================================================================= 55 //=============================================================================
54 // MN10300 Simulator 56 // MN10300 Simulator
55 57
56 #if defined(CYG_HAL_MN10300_SIM) 58 #if defined(CYG_HAL_MN10300_SIM)
165 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) 167 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
166 168
167 #endif 169 #endif
168 170
169 171
170 //=============================================================================
171 // MN103002 implementation
172
173 #if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002)
174
175 //-----------------------------------------------------------------------------
176 // Cache dimensions
177
178
179 // Data cache
180 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
181 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
182 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
183
184 // Instruction cache
185 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
186 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
187 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
188
189 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
190 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
191
192 //-----------------------------------------------------------------------------
193 // Control registers
194
195 #define HAL_CHCTR ((volatile CYG_ADDRWORD *)0x20000070)
196
197 #define HAL_CHCTR_ICEN 0x0001
198 #define HAL_CHCTR_DCEN 0x0002
199 #define HAL_CHCTR_ICBUSY 0x0004
200 #define HAL_CHCTR_DCBUSY 0x0008
201 #define HAL_CHCTR_ICINV 0x0010
202 #define HAL_CHCTR_DCINV 0x0020
203 #define HAL_CHCTR_DCWTMD 0x0040
204 #define HAL_CHCTR_ICWMD 0x0300
205 #define HAL_CHCTR_DCWMD 0x3000
206
207 #define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0x28400000)
208 #define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0x28401000)
209
210 //-----------------------------------------------------------------------------
211 // Global control of data cache
212
213 // Enable the data cache
214 #define HAL_DCACHE_ENABLE() \
215 { \
216 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
217 chctr |= HAL_CHCTR_DCEN; \
218 *HAL_CHCTR = chctr; \
219 }
220
221 // Disable the data cache
222 #define HAL_DCACHE_DISABLE() \
223 { \
224 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
225 chctr &= ~HAL_CHCTR_DCEN; \
226 *HAL_CHCTR = chctr; \
227 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
228 }
229
230 // Query the state of the data cache
231 #define HAL_DCACHE_IS_ENABLED(_state_) \
232 { \
233 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
234 _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \
235 }
236
237 // Invalidate the entire cache
238 #define HAL_DCACHE_INVALIDATE_ALL() \
239 { \
240 register CYG_ADDRWORD chctr; \
241 register CYG_ADDRWORD state; \
242 HAL_DCACHE_IS_ENABLED(state); \
243 if (state) \
244 HAL_DCACHE_DISABLE(); \
245 chctr = *HAL_CHCTR; \
246 chctr |= HAL_CHCTR_DCINV; \
247 *HAL_CHCTR = chctr; \
248 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
249 if (state) \
250 HAL_DCACHE_ENABLE(); \
251 }
252
253 // Synchronize the contents of the cache with memory.
254 #define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE/HAL_DCACHE_WAYS )
255
256 // Set the data cache refill burst size
257 //#define HAL_DCACHE_BURST_SIZE(_size_)
258
259 // Set the data cache write mode
260 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
261 { \
262 register CYG_ADDRWORD chctr; \
263 register CYG_ADDRWORD state; \
264 HAL_DCACHE_IS_ENABLED(state); \
265 if (state) \
266 HAL_DCACHE_DISABLE(); \
267 chctr = *HAL_CHCTR; \
268 chctr |= HAL_CHCTR_DCWTMD*(_mode_); \
269 *HAL_CHCTR = chctr; \
270 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
271 if (state) \
272 HAL_DCACHE_ENABLE(); \
273 }
274
275 #define HAL_DCACHE_WRITEBACK_MODE 0
276 #define HAL_DCACHE_WRITETHRU_MODE 1
277
278 // Load the contents of the given address range into the data cache
279 // and then lock the cache so that it stays there.
280 //#define HAL_DCACHE_LOCK(_base_, _size_)
281
282 // Undo a previous lock operation
283 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
284
285 // Unlock entire cache
286 //#define HAL_DCACHE_UNLOCK_ALL()
287
288 //-----------------------------------------------------------------------------
289 // Data cache line control
290
291 // Allocate cache lines for the given address range without reading its
292 // contents from memory.
293 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
294
295 // Write dirty cache lines to memory and invalidate the cache entries
296 // for the given address range.
297 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
298
299 // Invalidate cache lines in the given range without writing to memory.
300 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
301
302 // Write dirty cache lines to memory for the given address range.
303
304 // This functionality requires 4 register variables. To prevent register
305 // spilling, put the code in a separate function.
306 externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size);
307
308 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
309 cyg_hal_dcache_store((_base_), (_size_))
310
311 // Preread the given range into the cache with the intention of reading
312 // from it later.
313 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
314
315 // Preread the given range into the cache with the intention of writing
316 // to it later.
317 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
318
319 // Allocate and zero the cache lines associated with the given range.
320 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
321
322 //-----------------------------------------------------------------------------
323 // Global control of Instruction cache
324
325 // Enable the instruction cache
326 #define HAL_ICACHE_ENABLE() \
327 { \
328 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
329 chctr |= HAL_CHCTR_ICEN; \
330 *HAL_CHCTR = chctr; \
331 }
332
333 // Disable the instruction cache
334 #define HAL_ICACHE_DISABLE() \
335 { \
336 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
337 chctr &= ~HAL_CHCTR_ICEN; \
338 *HAL_CHCTR = chctr; \
339 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
340 }
341
342 // Query the state of the instruction cache
343 #define HAL_ICACHE_IS_ENABLED(_state_) \
344 { \
345 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
346 _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \
347 }
348
349 // Invalidate the entire cache
350 #define HAL_ICACHE_INVALIDATE_ALL() \
351 { \
352 register CYG_ADDRWORD chctr; \
353 register CYG_ADDRWORD state; \
354 HAL_ICACHE_IS_ENABLED(state); \
355 if (state) \
356 HAL_ICACHE_DISABLE(); \
357 chctr = *HAL_CHCTR; \
358 chctr |= HAL_CHCTR_ICINV; \
359 *HAL_CHCTR = chctr; \
360 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
361 if (state) \
362 HAL_ICACHE_ENABLE(); \
363 }
364
365 // Synchronize the contents of the cache with memory.
366 #define HAL_ICACHE_SYNC()
367
368 // Set the instruction cache refill burst size
369 //#define HAL_ICACHE_BURST_SIZE(_size_)
370
371 // Load the contents of the given address range into the instruction cache
372 // and then lock the cache so that it stays there.
373 //#define HAL_ICACHE_LOCK(_base_, _size_)
374
375 // Undo a previous lock operation
376 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
377
378 // Unlock entire cache
379 //#define HAL_ICACHE_UNLOCK_ALL()
380
381 //-----------------------------------------------------------------------------
382 // Instruction cache line control
383
384 // Invalidate cache lines in the given range without writing to memory.
385 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
386
387 #endif
388
389 //----------------------------------------------------------------------------- 172 //-----------------------------------------------------------------------------
390 // Check that a supported configuration has actually defined some macros. 173 // Check that a supported configuration has actually defined some macros.
391 174
392 #ifndef HAL_DCACHE_ENABLE 175 #ifndef HAL_DCACHE_ENABLE
393 176