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* include/pkgconf/mlt_arm_lpc24xx_ea2468_rom.ldi: * include/pkgconf/mlt_arm_lpc24xx_ea2468_ram.ldi: Relocate fixed vectors to 0x40000020. Previously, the HAL_VSR_GET/SET macros accessed the wrong locations and didn't have any effect; now both hardware and software have the same idea of where the VSR table is. NOTE: that this renders RAM applications built with this layout incompatible with RedBoot built with the old layout. A new RedBoot needs to be installed. * cdl/hal_arm_lpc24xx_ea2468.cdl: * tests/fiq.c: Add FIQ test program.
author nickg
date Fri, 11 May 2012 10:25:27 +0000
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3250:afb59e9b7339 3251:7446751761c7
1 //==========================================================================
2 //
3 // fiq.c
4 //
5 // FIQ interrupt test
6 //
7 //==========================================================================
8 // ####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2012 Free Software Foundation, Inc.
12 //
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later
16 // version.
17 //
18 // eCos is distributed in the hope that it will be useful, but WITHOUT
19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
21 // for more details.
22 //
23 // You should have received a copy of the GNU General Public License
24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26 //
27 // As a special exception, if other files instantiate templates or use
28 // macros or inline functions from this file, or you compile this file
29 // and link it with other works to produce a work based on this file,
30 // this file does not by itself cause the resulting work to be covered by
31 // the GNU General Public License. However the source code for this file
32 // must still be made available in accordance with section (3) of the GNU
33 // General Public License v2.
34 //
35 // This exception does not invalidate any other reasons why a work based
36 // on this file might be covered by the GNU General Public License.
37 // -------------------------------------------
38 // ####ECOSGPLCOPYRIGHTEND####
39 //==========================================================================
40 //#####DESCRIPTIONBEGIN####
41 //
42 // Author(s): nickg
43 // Date: 2012-04-20
44 // Purpose:
45 // Description: FIQ test
46 //
47 //####DESCRIPTIONEND####
48 //
49 //==========================================================================
50
51 #include <pkgconf/system.h>
52 #include <pkgconf/hal.h>
53
54 #include <cyg/infra/cyg_type.h>
55 #include <cyg/infra/diag.h>
56
57 #include <cyg/hal/hal_arch.h>
58 #include <cyg/hal/hal_intr.h>
59
60 #include <cyg/infra/testcase.h>
61
62 #include <cyg/kernel/kapi.h>
63
64 //==========================================================================
65
66 volatile int fiq_count = 0;
67
68 void __attribute__ ((interrupt ("FIQ"))) fiq_vsr( void )
69 {
70 fiq_count++;
71
72 // Clear interrupt
73 HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_EINT0 );
74 }
75
76 //==========================================================================
77
78 void fiq_test(CYG_ADDRWORD p)
79 {
80 volatile int fiq_count0 = 0;
81 volatile int fiq_count1 = 0;
82 volatile cyg_uint32 val1 = 0;
83 cyg_uint32 pinsel = CYGARC_HAL_LPC24XX_REG_PIN_BASE;
84 cyg_uint32 pinsel4;
85 cyg_uint32 vic = CYGARC_HAL_LPC24XX_REG_VIC_BASE;
86 cyg_uint32 intsel;
87 cyg_uint32 gpio = CYGARC_HAL_LPC24XX_REG_FIO_BASE;
88
89 // Configure P2.10 as EINT0
90 HAL_READ_UINT32( pinsel+CYGARC_HAL_LPC24XX_REG_PINSEL4, pinsel4 );
91 pinsel4 &= ~(3<<20);
92 pinsel4 |= (1<<20);
93 HAL_WRITE_UINT32( pinsel+CYGARC_HAL_LPC24XX_REG_PINSEL4, pinsel4 );
94
95 // Configure EINT0 line for falling edge detection
96 HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_EINT0, false, false );
97
98 #if 1
99 // Route EINT0 to FIQ input
100 HAL_READ_UINT32( vic+CYGARC_HAL_LPC24XX_REG_VICINTSELECT, intsel );
101 intsel |= (1<<CYGNUM_HAL_INTERRUPT_EINT0);
102 HAL_WRITE_UINT32( vic+CYGARC_HAL_LPC24XX_REG_VICINTSELECT, intsel );
103 #endif
104
105 // Install and unmask FIQ VSR
106 HAL_VSR_SET( CYGNUM_HAL_VECTOR_FIQ, fiq_vsr, NULL );
107 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_EINT0 );
108
109 CYG_TEST_INFO("FIQ test starting");
110
111 // Enable FIQs
112 HAL_ENABLE_FIQ();
113
114 while(fiq_count1 < 20)
115 {
116 cyg_uint32 val;
117 cyg_uint8 pin;
118
119 HAL_READ_UINT8( gpio+CYGARC_HAL_LPC24XX_REG_FIO2PIN+1, pin );
120 val = 1&(pin>>2);
121
122 if( val != val1 )
123 {
124 cyg_uint32 qf;
125 HAL_QUERY_FIQ( qf );
126 //diag_printf("P2.10 %d fiq_count %d qf %08x\n", val, fiq_count, qf );
127 val1 = val;
128 }
129
130
131 if( fiq_count0 != fiq_count )
132 {
133 int dbcount = 10000;
134 int i = dbcount;
135
136 // Crude debouncing: loop here while fiq_count is
137 // changing, only continue when it has been stable for
138 // dbcount loops.
139 while( i-- )
140 {
141 if( fiq_count0 != fiq_count )
142 {
143 fiq_count0 = fiq_count;
144 i = dbcount;
145 }
146 }
147
148 fiq_count1++;
149 diag_printf("FIQ count %3d debounced %2d\n", fiq_count, fiq_count1 );
150 }
151 }
152
153 CYG_TEST_PASS_FINISH("fiq");
154 }
155
156 //==========================================================================
157
158 #define STACK_SIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
159 static char stack[STACK_SIZE];
160 static cyg_thread thread_data;
161 static cyg_handle_t thread_handle;
162
163 void
164 cyg_start(void)
165 {
166 CYG_TEST_INIT();
167
168 cyg_thread_create(10, // Priority - just a number
169 fiq_test, // entry
170 0, // entry parameter
171 "FIQ test", // Name
172 &stack[0], // Stack
173 STACK_SIZE, // Size
174 &thread_handle, // Handle
175 &thread_data // Thread data structure
176 );
177 cyg_thread_resume(thread_handle); /* Start it */
178 cyg_scheduler_start();
179 }
180
181 //==========================================================================
182 // EOF