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comparison packages/hal/powerpc/mpc8xx/current/src/var_misc.c @ 103:95f3e12a6327 ecos-sw-2000-06-23

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Merge from eCos master repository on 2000-06-23-16:41:10-BST
author jlarmour
date Fri, 23 Jun 2000 17:06:31 +0000
parents 6736c52df507
children e0c0827131d1
comparison
equal deleted inserted replaced
102:6409b6d94dd7 103:95f3e12a6327
94 // use the MMU, so we can simulate BATs by using the TLBs. 94 // use the MMU, so we can simulate BATs by using the TLBs.
95 int 95 int
96 cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, 96 cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys,
97 cyg_int32 size, cyg_uint8 flags) 97 cyg_int32 size, cyg_uint8 flags)
98 { 98 {
99 cyg_uint32 epn, rpn, ctr, twc; 99 cyg_uint32 epn, rpn, twc, ctr = 0;
100 int max_tlbs; 100 int max_tlbs;
101 101
102 #if defined(CYGPKG_HAL_POWERPC_MPC860) 102 #if defined(CYGPKG_HAL_POWERPC_MPC860)
103 // There are 32 TLBs. 103 // There are 32 TLBs.
104 max_tlbs = 32; 104 max_tlbs = 32;
146 epn += 8*1024*1024; 146 epn += 8*1024*1024;
147 rpn += 8*1024*1024; 147 rpn += 8*1024*1024;
148 id++; 148 id++;
149 } 149 }
150 150
151 // Make caches default disabled when MMU is disabled.
152 CYGARC_MTSPR (MI_CTR, ctr | CYGARC_REG_MI_CTR_CIDEF);
153 CYGARC_MTSPR (MD_CTR, ctr | CYGARC_REG_MD_CTR_CIDEF);
154
151 return id; 155 return id;
152 } 156 }
153 157
154 158
155 // Initialize MMU to a sane (NOP) state. 159 // Initialize MMU to a sane (NOP) state.
156 // 160 //
157 // Initialize TLBs with 0, Valid bits unset. 161 // Initialize TLBs with 0, Valid bits unset.
158 void 162 void
159 cyg_hal_clear_MMU (void) 163 cyg_hal_clear_MMU (void)
160 { 164 {
161 cyg_uint32 ctr; 165 cyg_uint32 ctr = 0;
162 int id; 166 int id;
163 int max_tlbs; 167 int max_tlbs;
164 168
165 #if defined(CYGPKG_HAL_POWERPC_MPC860) 169 #if defined(CYGPKG_HAL_POWERPC_MPC860)
166 // There are 32 TLBs. 170 // There are 32 TLBs.
172 176
173 CYGARC_MTSPR (M_CASID, 0); 177 CYGARC_MTSPR (M_CASID, 0);
174 178
175 for (id = 0; id < max_tlbs; id++) { 179 for (id = 0; id < max_tlbs; id++) {
176 ctr = id << MI_CTR_INDX_SHIFT; 180 ctr = id << MI_CTR_INDX_SHIFT;
177 181
178 // Instruction TLBs. 182 // Instruction TLBs.
179 CYGARC_MTSPR (MI_TWC, 0); 183 CYGARC_MTSPR (MI_TWC, 0);
180 CYGARC_MTSPR (MI_CTR, ctr); 184 CYGARC_MTSPR (MI_CTR, ctr);
181 CYGARC_MTSPR (MI_EPN, 0); 185 CYGARC_MTSPR (MI_EPN, 0);
182 CYGARC_MTSPR (MI_RPN, 0); 186 CYGARC_MTSPR (MI_RPN, 0);
184 CYGARC_MTSPR (MD_TWC, 0); 188 CYGARC_MTSPR (MD_TWC, 0);
185 CYGARC_MTSPR (MD_CTR, ctr); 189 CYGARC_MTSPR (MD_CTR, ctr);
186 CYGARC_MTSPR (MD_EPN, 0); 190 CYGARC_MTSPR (MD_EPN, 0);
187 CYGARC_MTSPR (MD_RPN, 0); 191 CYGARC_MTSPR (MD_RPN, 0);
188 } 192 }
193
194 // Make caches default disabled when MMU is disabled.
195 CYGARC_MTSPR (MI_CTR, ctr | CYGARC_REG_MI_CTR_CIDEF);
196 CYGARC_MTSPR (MD_CTR, ctr | CYGARC_REG_MD_CTR_CIDEF);
189 } 197 }
190 198
191 //-------------------------------------------------------------------------- 199 //--------------------------------------------------------------------------
192 // End of var_misc.c 200 // End of var_misc.c