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comparison packages/hal/powerpc/arch/current/src/vectors.S @ 70:c5536bad4c24 ecos-sw-2000-02-11

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Merge from eCos master repository on 2000-02-11-15:46:40-GMT
author jlarmour
date Fri, 11 Feb 2000 16:47:32 +0000
parents f74b2666b30d
children da3908c9cd10
comparison
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69:9a9babddf7e7 70:c5536bad4c24
42 ## 42 ##
43 ######DESCRIPTIONEND#### 43 ######DESCRIPTIONEND####
44 ## 44 ##
45 ##========================================================================== 45 ##==========================================================================
46 46
47 #===========================================================================
48 #
49 # The PowerPC exception handling has changed as of version 1.3.1.
50 # The primary motivation for rewriting the code was to bring it more
51 # in line with the other HALs, in particular to allow a RAM application
52 # to cleanly take over only a subset of vectors from a running ROM
53 # monitor.
54 #
55 # GDB stubs (and CygMon, should it be ported to PPC) copies
56 # exception vector entry handler code to address 0. These vector entry
57 # handlers (defined by the exception_vector macro below) compute
58 # a vector index into the hal_vsr_table, fetch the pointer, and
59 # jump to the HAL vector service routine (VSR).
60 #
61 # The hal_vsr_table is located immediately after the vector
62 # handlers (at address 0x3000), allowing RAM applications to
63 # change VSRs as necessary, while still keeping desired ROM
64 # monitor functionality available for debugging.
65 #
66 # ROM applications can still be configured to leave the vector entry
67 # handlers at 0xff000000, but there is at the moment no
68 # provision for reclaiming the reserved vector space in RAM to
69 # application usage.
70 #
71 # RAM applications can also be configured to provide exception
72 # handlers which are copied to address 0 on startup, thus taking
73 # full control of the target.
74 #
75 #
76 # Default configuration is for RAM applications to rely on an
77 # existing ROM monitor to provide debugging functionality, and
78 # for ROM applications to copy vectors to address 0.
79 #
80 #
81 # Unfortunately the new exception scheme is not compatible with the
82 # old scheme. Stubs and applications must be compiled using the same
83 # scheme (i.e., old binaries will not run with new stubs, and new
84 # binaries will not run with old stubs).
85 #
86 #===========================================================================
87
47 #include <pkgconf/hal.h> 88 #include <pkgconf/hal.h>
48 89
49 #ifdef CYGPKG_KERNEL 90 #ifdef CYGPKG_KERNEL
50 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT 91 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT
51 #endif 92 #endif
52 93
53 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS 94 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
54 #include "cyg/hal/ppc_regs.h" 95 #include "cyg/hal/ppc_regs.h"
55 #include "cyg/hal/ppc.inc" 96 #include "cyg/hal/ppc.inc"
56 97
57 #=========================================================================== 98 #===========================================================================
58 99
59 .file "vectors.S" 100 .file "vectors.S"
60 101
102 .extern hal_interrupt_data
61 .extern hal_interrupt_handlers 103 .extern hal_interrupt_handlers
62 .extern hal_interrupt_data
63 .extern hal_interrupt_objects 104 .extern hal_interrupt_objects
64 105 .extern hal_vsr_table
106
107 .extern cyg_hal_invoke_constructors
65 .extern cyg_instrument 108 .extern cyg_instrument
66 109 .extern cyg_start
110 .extern hal_IRQ_init
111 .extern hal_MMU_init
112 .extern hal_enable_caches
67 .extern hal_hardware_init 113 .extern hal_hardware_init
114 .extern initialize_stub
115
116 .extern __bss_start
117 .extern __bss_end
118 .extern __sbss_start
119 .extern __sbss_end
68 120
69 #=========================================================================== 121 #===========================================================================
70 # MSR initialization value 122 # MSR initialization value
71 # zero all bits except: 123 # zero all bits except:
72 # FP = floating point available 124 # FP = floating point available
75 # IR = instruction address translation 127 # IR = instruction address translation
76 # DR = data address translation 128 # DR = data address translation
77 # RI = recoverable interrupt 129 # RI = recoverable interrupt
78 130
79 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI) 131 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI)
80 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) 132 #if defined(CYG_HAL_STARTUP_ROM)
81 # ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS 133 # ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
82 # define CYG_MSR CYG_MSR_COMMON 134 # define CYG_MSR CYG_MSR_COMMON
83 # else 135 # else
84 # define CYG_MSR (CYG_MSR_COMMON | MSR_IP) 136 # define CYG_MSR (CYG_MSR_COMMON | MSR_IP)
85 # endif 137 # endif
86 #endif 138 #elif defined(CYG_HAL_STARTUP_RAM)
87 #ifdef CYG_HAL_STARTUP_RAM 139 # define CYG_MSR CYG_MSR_COMMON
88 #define CYG_MSR CYG_MSR_COMMON 140 #endif
89 #endif 141
90 #ifdef CYGPKG_HAL_POWERPC_SIM 142 #ifdef CYGPKG_HAL_POWERPC_SIM
91 # When building for SIM, don~t enable MMU -- it~s not needed since caches 143 # When building for SIM, don~t enable MMU -- it~s not needed since caches
92 # are disabled, and there is a runtime simulation overhead. 144 # are disabled, and there is a runtime simulation overhead.
93 #undef CYG_MSR 145 #undef CYG_MSR
94 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR)) 146 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR))
95 #endif 147 #endif
96 148
97 #define CYG_MSR_NO_INTS (CYG_MSR & ~MSR_ME) 149 #define CYG_MSR_NO_INTS (CYG_MSR & ~MSR_ME)
98 150
151 # Include variant macros after MSR definition.
152 #include "cyg/hal/variant.inc"
153
154
99 #=========================================================================== 155 #===========================================================================
100 # If the following option is enabled, we only save registers up to R12. 156 # If the following option is enabled, we only save registers up to R12.
101 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do 157 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
102 # not need to save them when calling C functions. 158 # not need to save them when calling C functions.
103 159
104 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT 160 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
105 161 # define MAX_SAVE_REG 12
106 #define MAX_SAVE_REG 12
107
108 #else 162 #else
109 163 # define MAX_SAVE_REG 31
110 #define MAX_SAVE_REG 31
111
112 #endif 164 #endif
113 165
114 #=========================================================================== 166 #===========================================================================
115 # Start by defining the exceptions vectors that must be placed at 167 # Start by defining the exceptions vectors that must be placed at
116 # locations 0xFFF00000 and 0x00000000. The following code will normally 168 # locations 0xFFF00000 or 0x00000000. The following code will normally
117 # be located at 0xFFF00000 in the ROM. It may optionally be copied out 169 # be located at 0xFFF00000 in the ROM. It may optionally be copied out
118 # to 0x00000000 if we want to use the RAM vectors. For this reason this code 170 # to 0x00000000 if we want to use the RAM vectors. For this reason this code
119 # MUST BE POSITION INDEPENDENT. In RAM loaded configurations, this code may 171 # MUST BE POSITION INDEPENDENT.
120 # be placed at 0x00000000 during loading.
121 172
122 .section ".vectors","ax" 173 .section ".vectors","ax"
123 174
124 #--------------------------------------------------------------------------- 175 #---------------------------------------------------------------------------
125 # Unused first vector. Jump to special handler, trapping null-pointer calls. 176 # Macros for generating an exception vector service routine
126 177
127 rom_vectors: 178 # Reset vector macro
128 .extern hal_null_call 179
129 b hal_null_call 180 .macro reset_vector name
130
131 #---------------------------------------------------------------------------
132 # Reset vector.
133
134 .p2align 8 181 .p2align 8
135 .globl reset_vector 182 .globl __exception_\name
136 183 __exception_\name:
137 reset_vector:
138 lwi r3,_start 184 lwi r3,_start
139 mtlr r3 185 mtlr r3
140 blr 186 blr
141 187 .endm
142 #--------------------------------------------------------------------------- 188
143 # Macro for generating an exception vector service routine 189 # Generic vector macro
144 190
145 .macro exception_vector name 191 .macro exception_vector name
146 .p2align 8 192 .p2align 8
147 .globl __exception_\name 193 .globl __exception_\name
148 __exception_\name: 194 __exception_\name:
149 mtspr SPRG1,r3 # stash some work registers away 195 mtspr SPRG1,r3 # stash some work registers away
161 .endm 207 .endm
162 208
163 #--------------------------------------------------------------------------- 209 #---------------------------------------------------------------------------
164 # Define the exception vectors. 210 # Define the exception vectors.
165 211
212 rom_vectors:
166 # These are the architecture defined vectors that 213 # These are the architecture defined vectors that
167 # are always present. 214 # are always present.
168 215 exception_vector reserved_00000
216 reset_vector reset
169 exception_vector machine_check 217 exception_vector machine_check
170 exception_vector data_storage 218 exception_vector data_storage
171 exception_vector instruction_storage 219 exception_vector instruction_storage
172 exception_vector external 220 exception_vector external
173 exception_vector alignment 221 exception_vector alignment
174 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) \
175 || defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
176 exception_vector program 222 exception_vector program
177 #else
178 # Provide a crude hook to the GDB exception handler in ROM.
179 # This allows the testing infrastructure to rely on breakpoints
180 # to terminate tests, even when the tests are compiled without
181 # the GDB stub.
182 # It is _not_ a generic solution to the problem; in particular it
183 # is not possible to continue after a breakpoint is hit.
184 #
185 # Note that for platforms where StubROM vectors are copied into RAM
186 # at 0x00000000, simply skipping the copy of vector 0x700 is a
187 # better solution. See CYGPRI_STUBROM_HAS_RAM_VECTORS below.
188
189 .p2align 8
190 .globl __exception_program
191 __exception_program:
192 bl _init_CPU # disable caches.
193 lwi r3,0xfff00700 # address of trap handler
194 mtlr r3 # in ROM.
195 blr # jump to it.
196
197 #endif
198 exception_vector floatingpoint_unavailable 223 exception_vector floatingpoint_unavailable
199 exception_vector decrementer 224 exception_vector decrementer
200 exception_vector reserved_00a00 225 exception_vector reserved_00a00
201 exception_vector reserved_00b00 226 exception_vector reserved_00b00
202 exception_vector system_call 227 exception_vector system_call
203 exception_vector trace 228 exception_vector trace
204 exception_vector floatingpoint_assist 229 exception_vector floatingpoint_assist
205 exception_vector reserved_00f00 230 exception_vector reserved_00f00
206 231
207 # There are some additional vectors defined 232 # Variants may define extra vectors.
208 # on various implementations. 233 hal_extra_vectors
209 234
210 #ifdef CYGPKG_HAL_POWERPC_MPC8xx 235 rom_vectors_end:
211 # MPC8xx vectors
212
213 exception_vector software_emu
214 exception_vector instruction_tlb_miss
215 exception_vector data_tlb_miss
216 exception_vector instruction_tlb_error
217 exception_vector data_tlb_error
218 exception_vector reserved_01500
219 exception_vector reserved_01600
220 exception_vector reserved_01700
221 exception_vector reserved_01800
222 exception_vector reserved_01900
223 exception_vector reserved_01A00
224 exception_vector reserved_01B00
225 exception_vector data_breakpoint
226 exception_vector instruction_breakpoint
227 exception_vector peripheral_breakpoint
228 exception_vector NMI_port
229
230 #endif
231 rom_vectors_end:
232 236
233 #=========================================================================== 237 #===========================================================================
234 # Real startup code. We jump here from the various reset vectors to set up 238 # Real startup code. We jump here from the various reset vectors to set up
235 # the world. 239 # the world.
236 240
237 .text 241 .text
238 .globl _start 242 .globl _start
239
240 _start: 243 _start:
241 # Initialize CPU 244 # Initialize CPU to a post-reset state, ensuring the ground doesn''t
242 bl _init_CPU 245 # shift under us while we try to set things up.
243 246 hal_cpu_init
244 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
245 # Disable special MPC8xx "development support" which
246 # suppresses trace exceptions. The CPU seems to hang, not
247 # executing from offset 0x1e00(?) as expected.
248
249 lwi r3,0x00000007
250 mtspr ICTRL,r3
251
252 li r3,0
253 mtspr DER, r3
254 #endif
255 247
256 # Set up global offset table 248 # Set up global offset table
257 lwi r2,_GLOBAL_OFFSET_TABLE_ 249 lwi r2,_GLOBAL_OFFSET_TABLE_
258 250
259 # set up time base register to zero 251 # set up time base register to zero
269 261
270 # set up stack 262 # set up stack
271 lwi sp,__interrupt_stack 263 lwi sp,__interrupt_stack
272 mtspr SPRG0,sp # save in sprg0 for later use 264 mtspr SPRG0,sp # save in sprg0 for later use
273 265
274 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) 266 # Set up exception handlers and VSR table, taking care not to
267 # step on any ROM monitor''s toes.
268 hal_mon_init
269
270 #if defined(CYG_HAL_STARTUP_ROM)
275 271
276 # Copy data from ROM to ram 272 # Copy data from ROM to ram
277 lwi r3,__rom_data_start # r3 = rom start 273 lwi r3,__rom_data_start # r3 = rom start
278 lwi r4,__ram_data_start # r4 = ram start 274 lwi r4,__ram_data_start # r4 = ram start
279 lwi r5,__ram_data_end # r5 = ram end 275 lwi r5,__ram_data_end # r5 = ram end
288 addi r4,r4,4 # increment by 1 word 284 addi r4,r4,4 # increment by 1 word
289 cmplw r4,r5 # compare 285 cmplw r4,r5 # compare
290 blt 1b # loop if not yet done 286 blt 1b # loop if not yet done
291 2: 287 2:
292 #endif 288 #endif
293
294
295 #ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup
296
297 #ifdef CYGPKG_HAL_POWERPC_MBX
298 # define CYGPRI_STUBROM_HAS_RAM_VECTORS
299 #endif
300
301 #ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS
302 # ifdef CYG_HAL_STARTUP_RAM
303 # ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
304 # define CYGPRI_SKIP_BREAKPOINT_VECTOR
305 # endif // no stubs
306 # endif // RAM startup
307 #endif // Stubrom vectors are in RAM
308
309 # Copy RAM exception vectors from ROM (or load place) to RAM
310 lwi r3,rom_vectors # r3 = rom start
311 lwi r4,0 # r4 = ram start
312 #ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR
313 lwi r5,__exception_program # r5 = end of first leg of copy
314 #else
315 lwi r5,rom_vectors_end # r5 = rom end
316 #endif
317
318 cmplw r3,r5 # skip if no vectors
319 beq 2f
320
321 1:
322 lwz r0,0(r3) # get word from ROM
323 stw r0,0(r4) # store in RAM
324 addi r3,r3,4 # increment by 1 word
325 addi r4,r4,4 # increment by 1 word
326 cmplw r3,r5 # compare
327 blt 1b # loop if not yet done
328 2:
329 #ifdef CYGPRI_SKIP_BREAKPOINT_VECTOR
330 cmplwi r4,__exception_program@L
331 bne 3f # is it the breakpoint vector?
332 addi r4,r4,0x100 # if so, leave it well alone
333 addi r3,r3,0x100
334 lwi r5,rom_vectors_end # r5 = rom end
335 b 1b # and do the rest of the copy
336 3:
337 #endif // Skip copying the breakpoint vector
338 #endif
339 289
340 # clear BSS 290 # clear BSS
341 .extern __bss_start
342 .extern __bss_end
343 lwi r3,__bss_start # r3 = start 291 lwi r3,__bss_start # r3 = start
344 lwi r4,__bss_end # r4 = end 292 lwi r4,__bss_end # r4 = end
345 li r0,0 # r0 = 0 293 li r0,0 # r0 = 0
346 cmplw r3,r4 # skip if no bss 294 cmplw r3,r4 # skip if no bss
347 beq 2f 295 beq 2f
351 cmplw r3,r4 # compare 299 cmplw r3,r4 # compare
352 blt 1b # loop if not yet done 300 blt 1b # loop if not yet done
353 2: 301 2:
354 302
355 # clear SBSS 303 # clear SBSS
356 .extern __sbss_start
357 .extern __sbss_end
358 lwi r3,__sbss_start # r3 = start 304 lwi r3,__sbss_start # r3 = start
359 lwi r4,__sbss_end # r4 = end 305 lwi r4,__sbss_end # r4 = end
360 cmplw r3,r4 # skip if no sbss 306 cmplw r3,r4 # skip if no sbss
361 beq 2f 307 beq 2f
362 308
375 stw r0,0(sp) # clear back chain 321 stw r0,0(sp) # clear back chain
376 stw r0,8(sp) # zero return pc 322 stw r0,8(sp) # zero return pc
377 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame 323 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
378 324
379 # Initialize MMU. 325 # Initialize MMU.
380 .extern hal_MMU_init
381 bl hal_MMU_init 326 bl hal_MMU_init
382 327
383 # Enable MMU so we can safely enable caches. 328 # Enable MMU so we can safely enable caches.
384 lwi r3,CYG_MSR_NO_INTS # interrupts enabled later 329 lwi r3,CYG_MSR_NO_INTS # interrupts enabled later
385 sync 330 sync
386 mtmsr r3 331 mtmsr r3
387 sync 332 sync
388 333
389 # Enable caches 334 # Enable caches
390 .extern hal_enable_caches
391 bl hal_enable_caches 335 bl hal_enable_caches
392 336
393 # call c++ constructors 337 # call c++ constructors
394 .extern cyg_hal_invoke_constructors
395 bl cyg_hal_invoke_constructors 338 bl cyg_hal_invoke_constructors
396 339
397 # set up platform specific interrupt environment 340 # set up platform specific interrupt environment
398 .extern hal_IRQ_init
399 bl hal_IRQ_init 341 bl hal_IRQ_init
400 342
401 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS 343 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
402 .extern initialize_stub
403 bl initialize_stub 344 bl initialize_stub
404 #endif 345 #endif
405 346
406 .extern cyg_start
407 bl cyg_start # call cyg_start 347 bl cyg_start # call cyg_start
408 9: 348 9:
409 b 9b # if we return, loop 349 b 9b # if we return, loop
410 350
411 #--------------------------------------------------------------------------- 351 #---------------------------------------------------------------------------
415 # in thread switches, and changes to the saved state. When we return 355 # in thread switches, and changes to the saved state. When we return
416 # here the saved state is restored and execution is continued. 356 # here the saved state is restored and execution is continued.
417 357
418 .text 358 .text
419 359
420 .extern __default_exception_vsr 360 .globl cyg_hal_default_exception_vsr
421 __default_exception_vsr: 361 cyg_hal_default_exception_vsr:
422 362
423 # We come here with all register containing their 363 # We come here with all register containing their
424 # pre-exception values except: 364 # pre-exception values except:
425 # R3 = ls 16 bits of vector address 365 # R3 = ls 16 bits of vector address
426 # R4 = saved CR 366 # R4 = saved CR
518 ## system is using isr tables or chaining, and depending on the interrupt 458 ## system is using isr tables or chaining, and depending on the interrupt
519 ## controller in the system. 459 ## controller in the system.
520 460
521 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h. 461 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h.
522 462
523 #ifdef CYGPKG_HAL_POWERPC_MPC8xx 463 #ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED
524
525 ## First level decoding of MPC8xx SIU interrupt controller.
526
527 #define CYG_ISR_TABLE_SIZE 59
528
529 # decode the interrupt
530 .macro decode_interrupt dreg,state
531 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
532 rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
533 beq 0f # done if decrementer (vec 0)
534 lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU
535 lbz \dreg,0(\dreg) # vector.
536 srwi \dreg,\dreg,2
537 addi \dreg,\dreg,1 # Skip decrementer vector
538 0: stw \dreg,ppcreg_vector(\state) # update vector in state frame.
539 slwi \dreg,\dreg,2 # convert to byte offset.
540 .endm
541
542 #else
543 464
544 ## This is the simple version. No interrupt controller, ppcreg_vector 465 ## This is the simple version. No interrupt controller, ppcreg_vector
545 ## is updated with the decoded interrupt vector. Isr tables/chaining 466 ## is updated with the decoded interrupt vector. Isr tables/chaining
546 ## use same interrupt decoder. 467 ## use same interrupt decoder.
547 ## Bit 21 biffers between decrementer (0) and external (1). 468 ## Bit 21 biffers between decrementer (0) and external (1).
548 469
549 #define CYG_ISR_TABLE_SIZE 2 470 #define CYG_ISR_TABLE_SIZE 2
550 471
551 # decode the interrupt 472 # decode the interrupt
552 .macro decode_interrupt dreg,state 473 .macro hal_intc_decode dreg,state
553 lwz \dreg,ppcreg_vector(\state) # retrieve vector number, 474 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
554 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update 475 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update
555 stw \dreg,ppcreg_vector(\state) # vector in state frame. 476 stw \dreg,ppcreg_vector(\state) # vector in state frame.
556 slwi \dreg,\dreg,2 # convert to word offset. 477 slwi \dreg,\dreg,2 # convert to word offset.
557 .endm 478 .endm
558 479
559 #endif 480 #endif // CYGPKG_HAL_POWERPC_MPC8xx
560 481
561 #--------------------------------------------------------------------------- 482 #---------------------------------------------------------------------------
562 # Common interrupt handling code. 483 # Common interrupt handling code.
563 484
564 .extern __default_interrupt_vsr 485 .globl cyg_hal_default_interrupt_vsr
565 __default_interrupt_vsr: 486 cyg_hal_default_interrupt_vsr:
566 487
567 # We come here with all register containing their 488 # We come here with all register containing their
568 # pre-exception values except: 489 # pre-exception values except:
569 # R3 = ls 16 bits of vector address 490 # R3 = ls 16 bits of vector address
570 # R4 = saved CR 491 # R4 = saved CR
673 xor r5,r5,r5 # arg2 = 0 594 xor r5,r5,r5 # arg2 = 0
674 bl cyg_instrument # call instrument function 595 bl cyg_instrument # call instrument function
675 596
676 #endif 597 #endif
677 598
678 decode_interrupt r15,r14 # get table index 599 hal_intc_decode r15,r14 # get table index
679 600
680 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 601 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
681 .extern cyg_hal_gdb_isr 602 .extern cyg_hal_gdb_isr
682 lwz r3,ppcreg_pc(r14) # for serial receive irq. 603 lwz r3,ppcreg_pc(r14) # for serial receive irq.
683 bl cyg_hal_gdb_isr # (arg1 is PC) 604 bl cyg_hal_gdb_isr # (arg1 is PC)
889 mtmsr r4 810 mtmsr r4
890 811
891 blr 812 blr
892 #endif 813 #endif
893 814
894 #---------------------------------------------------------------------------
895 # Code for putting the CPU in a post-reset state; disabling MMU and caches.
896 _init_CPU:
897 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
898 lwi r3,CYGARC_REG_DC_CMD_CD
899 sync
900 mtspr CYGARC_REG_DC_CST,r3
901 lwi r3,CYGARC_REG_IC_CMD_CD
902 isync
903 mtspr CYGARC_REG_IC_CST,r3
904 isync
905 #endif
906
907 # Set up MSR (disable MMU for now)
908 lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
909 sync
910 mtmsr r3
911 sync
912 blr
913
914 #---------------------------------------------------------------------------
915 # This table contains a VSR pointer for each defined exception.
916 # All of these except 5 and 9 point to the __default_exception_vsr
917 # above, 5 and 9 point to the __default_interrupt_vsr. Entries in
918 # this table may be changed using Cyg_Interrupt::set_vsr().
919
920 .data
921
922 .globl hal_vsr_table
923 hal_vsr_table:
924 # Architecture defined vectors
925 .long __default_exception_vsr # reserved
926 .long __default_exception_vsr # system reset
927 .long __default_exception_vsr # machine check
928 .long __default_exception_vsr # data storage
929 .long __default_exception_vsr # instruction storage
930
931 .long __default_interrupt_vsr # external interrupt
932
933 .long __default_exception_vsr # alignment
934 .long __default_exception_vsr # program
935 .long __default_exception_vsr # floating point unavailable
936
937 .long __default_interrupt_vsr # decrementer
938
939 .long __default_exception_vsr # reserved 0x0a00
940 .long __default_exception_vsr # reserved 0x0b00
941 .long __default_exception_vsr # system call
942 .long __default_exception_vsr # trace
943 .long __default_exception_vsr # floating point assist
944 .long __default_exception_vsr # reserved 0x0f00
945
946 #ifdef CYGPKG_HAL_POWERPC_MPC8xx
947
948 # Implementation defined vectors
949 .long __default_exception_vsr # software emulation
950 .long __default_exception_vsr # instruction TLB miss
951 .long __default_exception_vsr # data TLB miss
952 .long __default_exception_vsr # instruction TLB error
953 .long __default_exception_vsr # data TLB error
954 .long __default_exception_vsr # reserved 0x1500
955 .long __default_exception_vsr # reserved 0x1600
956 .long __default_exception_vsr # reserved 0x1700
957 .long __default_exception_vsr # reserved 0x1800
958 .long __default_exception_vsr # reserved 0x1900
959 .long __default_exception_vsr # reserved 0x1a00
960 .long __default_exception_vsr # reserved 0x1b00
961 .long __default_exception_vsr # data breakpoint
962 .long __default_exception_vsr # instruction breakpoint
963 .long __default_exception_vsr # peripheral breakpoint
964 .long __default_exception_vsr # non maskable development port
965 #endif
966
967 #---------------------------------------------------------------------------
968 # Interrupt vector tables.
969 # These tables contain the isr, data and object pointers used to deliver
970 # interrupts to user code.
971
972 #if (CYG_ISR_TABLE_SIZE > 2)
973 .data
974 #else
975 .section ".sdata","aw"
976 #endif
977
978 .extern hal_default_decrementer_isr
979 .extern hal_default_isr
980
981 .globl hal_interrupt_handlers
982 hal_interrupt_handlers:
983 .long hal_default_decrementer_isr
984 .rept CYG_ISR_TABLE_SIZE-1
985 .long hal_default_isr
986 .endr
987
988 .globl hal_interrupt_data
989 hal_interrupt_data:
990 .rept CYG_ISR_TABLE_SIZE
991 .long 0
992 .endr
993
994 .globl hal_interrupt_objects
995 hal_interrupt_objects:
996 .rept CYG_ISR_TABLE_SIZE
997 .long 0
998 .endr
999
1000 #--------------------------------------------------------------------------- 815 #---------------------------------------------------------------------------
1001 ## Temporary interrupt stack 816 ## Temporary interrupt stack
1002 817
1003 .section ".bss" 818 .section ".bss"
1004 819