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comparison packages/hal/powerpc/mpc8xx/current/include/var_intr.h @ 70:c5536bad4c24 ecos-sw-2000-02-11

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Merge from eCos master repository on 2000-02-11-15:46:40-GMT
author jlarmour
date Fri, 11 Feb 2000 16:47:32 +0000
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children c37d3a9e1b28
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69:9a9babddf7e7 70:c5536bad4c24
1 #ifndef CYGONCE_VAR_INTR_H
2 #define CYGONCE_VAR_INTR_H
3 //=============================================================================
4 //
5 // var_intr.h
6 //
7 // Variant HAL interrupt and clock support
8 //
9 //=============================================================================
10 //####COPYRIGHTBEGIN####
11 //
12 // -------------------------------------------
13 // The contents of this file are subject to the Red Hat eCos Public License
14 // Version 1.1 (the "License"); you may not use this file except in
15 // compliance with the License. You may obtain a copy of the License at
16 // http://www.redhat.com/
17 //
18 // Software distributed under the License is distributed on an "AS IS"
19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
20 // License for the specific language governing rights and limitations under
21 // the License.
22 //
23 // The Original Code is eCos - Embedded Configurable Operating System,
24 // released September 30, 1998.
25 //
26 // The Initial Developer of the Original Code is Red Hat.
27 // Portions created by Red Hat are
28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
29 // All Rights Reserved.
30 // -------------------------------------------
31 //
32 //####COPYRIGHTEND####
33 //=============================================================================
34 //#####DESCRIPTIONBEGIN####
35 //
36 // Author(s): nickg
37 // Contributors:nickg, jskov, jlarmour, hmt
38 // Date: 2000-04-02
39 // Purpose: Variant interrupt support
40 // Description: The macros defined here provide the HAL APIs for handling
41 // interrupts and the clock on the MPC8xx variant CPUs.
42 // Usage: Is included via the architecture interrupt header:
43 // #include <cyg/hal/hal_intr.h>
44 // ...
45 //
46 //####DESCRIPTIONEND####
47 //
48 //=============================================================================
49
50 #include <pkgconf/hal.h>
51
52 #include <cyg/infra/cyg_type.h> // types
53
54 #include <cyg/hal/ppc_regs.h> // register definitions
55
56 #include <cyg/hal/hal_io.h> // io macros
57 #include <cyg/infra/cyg_ass.h> // CYG_FAIL
58
59 //-----------------------------------------------------------------------------
60 // Exception vectors.
61
62 // Additional exceptions on the MPC8xx CPUs
63 #define CYGNUM_HAL_VECTOR_RESERVED_F 15
64 #define CYGNUM_HAL_VECTOR_SW_EMUL 16
65 #define CYGNUM_HAL_VECTOR_ITLB_MISS 17
66 #define CYGNUM_HAL_VECTOR_DTLB_MISS 18
67 #define CYGNUM_HAL_VECTOR_ITLB_ERROR 19
68 #define CYGNUM_HAL_VECTOR_DTLB_ERROR 20
69 #define CYGNUM_HAL_VECTOR_RESERVED_15 21
70 #define CYGNUM_HAL_VECTOR_RESERVED_16 22
71 #define CYGNUM_HAL_VECTOR_RESERVED_17 23
72 #define CYGNUM_HAL_VECTOR_RESERVED_18 24
73 #define CYGNUM_HAL_VECTOR_RESERVED_19 25
74 #define CYGNUM_HAL_VECTOR_RESERVED_1A 26
75 #define CYGNUM_HAL_VECTOR_RESERVED_1B 27
76 #define CYGNUM_HAL_VECTOR_DATA_BP 28
77 #define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29
78 #define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30
79 #define CYGNUM_HAL_VECTOR_NMI 31
80
81 #define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI
82
83 // These are the values used when passed out to an
84 // external exception handler using cyg_hal_deliver_exception()
85
86 #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
87 #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
88 #ifdef CYGPKG_HAL_POWERPC_MPC860
89 // The MPC860 does not generate DSI and ISI: instead it goes to machine
90 // check, so that a software VM system can then call into vectors 0x300 or
91 // 0x400 if the address is truly invalid rather than merely not in the TLB
92 // right now. Shades of IBM wanting to port OS/MVS here!
93 // See pp 7-9/10 in "PowerQUICC - MPC860 User's Manual"
94 # undef CYGNUM_HAL_EXCEPTION_DATA_ACCESS
95 # define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_MACHINE_CHECK
96 // do not define catchers for DSI and ISI - should never happen.
97 # undef CYGNUM_HAL_EXCEPTION_MACHINE_CHECK
98 # undef CYGNUM_HAL_EXCEPTION_CODE_ACCESS
99 #else
100 # define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DSI
101 # define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ISI
102 #endif
103 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
104 CYGNUM_HAL_VECTOR_ALIGNMENT
105 #define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
106 #define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A
107 #define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B
108 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
109 #define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE
110 #define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST
111 #define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F
112 #define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL
113 #define CYGNUM_HAL_EXCEPTION_CODE_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_ITLB_MISS
114 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS CYGNUM_HAL_VECTOR_DTLB_MISS
115 #define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS \
116 CYGNUM_HAL_VECTOR_ITLB_ERROR
117 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS \
118 CYGNUM_HAL_VECTOR_DTLB_ERROR
119 #define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15
120 #define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16
121 #define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17
122 #define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18
123 #define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19
124 #define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A
125 #define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B
126 #define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP
127 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP
128 #define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP
129 #define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI
130
131 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0
132 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI
133
134 #define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
135
136 //-----------------------------------------------------------------------------
137 // Interrupts
138
139 // The first level of external interrupts
140 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1
141 #define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2
142 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3
143 #define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4
144 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5
145 #define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6
146 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7
147 #define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8
148 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9
149 #define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10
150 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11
151 #define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12
152 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13
153 #define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14
154 #define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15
155 #define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16
156
157 // Further decoded interrups
158 #define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17
159 #define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18
160 #define CYGNUM_HAL_INTERRUPT_SIU_PIT 19
161 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20
162 #define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21
163 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_IRQ 22
164 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_A_CHLVL 23
165 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_IRQ 24
166 #define CYGNUM_HAL_INTERRUPT_SIU_PCMCIA_B_CHLVL 25
167 #define CYGNUM_HAL_INTERRUPT_SIU_CPM 26
168
169 // Even further...
170 #define CYGNUM_HAL_INTERRUPT_CPM_PC15 27
171 #define CYGNUM_HAL_INTERRUPT_CPM_SCC1 28
172 #define CYGNUM_HAL_INTERRUPT_CPM_SCC2 29
173 #define CYGNUM_HAL_INTERRUPT_CPM_SCC3 30
174 #define CYGNUM_HAL_INTERRUPT_CPM_SCC4 31
175 #define CYGNUM_HAL_INTERRUPT_CPM_PC14 32
176 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER1 33
177 #define CYGNUM_HAL_INTERRUPT_CPM_PC13 34
178 #define CYGNUM_HAL_INTERRUPT_CPM_PC12 35
179 #define CYGNUM_HAL_INTERRUPT_CPM_SDMA 36
180 #define CYGNUM_HAL_INTERRUPT_CPM_IDMA1 37
181 #define CYGNUM_HAL_INTERRUPT_CPM_IDMA2 38
182 #define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_13 39
183 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER2 40
184 #define CYGNUM_HAL_INTERRUPT_CPM_RISCTT 41
185 #define CYGNUM_HAL_INTERRUPT_CPM_I2C 42
186 #define CYGNUM_HAL_INTERRUPT_CPM_PC11 43
187 #define CYGNUM_HAL_INTERRUPT_CPM_PC10 44
188 #define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_0D 45
189 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER3 46
190 #define CYGNUM_HAL_INTERRUPT_CPM_PC9 47
191 #define CYGNUM_HAL_INTERRUPT_CPM_PC8 48
192 #define CYGNUM_HAL_INTERRUPT_CPM_PC7 49
193 #define CYGNUM_HAL_INTERRUPT_CPM_RESERVED_08 50
194 #define CYGNUM_HAL_INTERRUPT_CPM_TIMER4 51
195 #define CYGNUM_HAL_INTERRUPT_CPM_PC6 52
196 #define CYGNUM_HAL_INTERRUPT_CPM_SPI 53
197 #define CYGNUM_HAL_INTERRUPT_CPM_SMC1 54
198 #define CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP 55
199 #define CYGNUM_HAL_INTERRUPT_CPM_PC5 56
200 #define CYGNUM_HAL_INTERRUPT_CPM_PC4 57
201 #define CYGNUM_HAL_INTERRUPT_CPM_ERROR 58
202
203 #define CYGNUM_HAL_INTERRUPT_CPM_FIRST CYGNUM_HAL_INTERRUPT_CPM_PC15
204 #define CYGNUM_HAL_INTERRUPT_CPM_LAST CYGNUM_HAL_INTERRUPT_CPM_ERROR
205
206 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_CPM_LAST
207 #endif
208
209
210 //--------------------------------------------------------------------------
211 // Interrupt controller access
212
213 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
214
215 #ifdef CYGPKG_HAL_POWERPC_MPC860
216
217 static __inline__ void
218 cyg_hal_interrupt_mask ( cyg_uint32 vector )
219 {
220 switch (vector) {
221 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
222 {
223 // SIU interrupt vectors
224 cyg_uint32 simask;
225
226 HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
227 simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0)
228 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
229 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
230 break;
231 }
232 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
233 {
234 // TimeBase A interrupt
235 cyg_uint16 tbscr;
236
237 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
238 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE);
239 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
240 break;
241 }
242 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
243 {
244 // TimeBase B interrupt
245 cyg_uint16 tbscr;
246
247 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
248 tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE);
249 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
250 break;
251 }
252 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
253 {
254 // Periodic Interrupt
255 cyg_uint16 piscr;
256
257 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
258 piscr &= ~(CYGARC_REG_IMM_PISCR_PIE);
259 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
260 break;
261 }
262 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
263 {
264 // Real Time Clock Second
265 cyg_uint16 rtcsc;
266
267 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
268 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE);
269 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
270 break;
271 }
272 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
273 {
274 // Real Time Clock Alarm
275 cyg_uint16 rtcsc;
276
277 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
278 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE);
279 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
280 break;
281 }
282 // PCMCIA_A_IRQ
283 // PCMCIA_A_CHLVL
284 // PCMCIA_B_IRQ
285 // PCMCIA_B_CHLVL
286 case CYGNUM_HAL_INTERRUPT_SIU_CPM:
287 {
288 // Communications Processor Module
289 cyg_uint32 cicr;
290
291 HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr);
292 cicr &= ~(CYGARC_REG_IMM_CICR_IEN);
293 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr);
294 break;
295 }
296 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
297 {
298 // CPM interrupts
299 cyg_uint32 cimr;
300
301 HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
302 cimr &= ~(((cyg_uint32) 0x80000000)
303 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST));
304 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
305 break;
306 }
307 default:
308 CYG_FAIL("Unknown Interrupt!!!");
309 break;
310 }
311 }
312
313 static __inline__ void
314 cyg_hal_interrupt_unmask ( cyg_uint32 vector )
315 {
316 switch (vector) {
317 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
318 {
319 // SIU interrupt vectors
320 cyg_uint32 simask;
321
322 HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
323 simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRQ0)
324 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
325 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
326 break;
327 }
328 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
329 {
330 // TimeBase A interrupt
331 cyg_uint16 tbscr;
332
333 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
334 tbscr |= CYGARC_REG_IMM_TBSCR_REFAE;
335 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
336 break;
337 }
338 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
339 {
340 // TimeBase B interrupt
341 cyg_uint16 tbscr;
342
343 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
344 tbscr |= CYGARC_REG_IMM_TBSCR_REFBE;
345 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
346 break;
347 }
348 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
349 {
350 // Periodic Interrupt
351 cyg_uint16 piscr;
352
353 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
354 piscr |= CYGARC_REG_IMM_PISCR_PIE;
355 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
356 break;
357 }
358 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
359 {
360 // Real Time Clock Second
361 cyg_uint16 rtcsc;
362
363 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
364 rtcsc |= CYGARC_REG_IMM_RTCSC_SIE;
365 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
366 break;
367 }
368 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
369 {
370 // Real Time Clock Alarm
371 cyg_uint16 rtcsc;
372
373 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
374 rtcsc |= CYGARC_REG_IMM_RTCSC_ALE;
375 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
376 break;
377 }
378 // PCMCIA_A_IRQ
379 // PCMCIA_A_CHLVL
380 // PCMCIA_B_IRQ
381 // PCMCIA_B_CHLVL
382 case CYGNUM_HAL_INTERRUPT_SIU_CPM:
383 {
384 // Communications Processor Module
385 cyg_uint32 cicr;
386
387 HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr);
388 cicr |= CYGARC_REG_IMM_CICR_IEN;
389 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr);
390 break;
391 }
392 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
393 {
394 // CPM interrupts
395 cyg_uint32 cimr;
396
397 HAL_READ_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
398 cimr |= (((cyg_uint32) 0x80000000)
399 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST));
400 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CIMR, cimr);
401 break;
402 }
403 default:
404 CYG_FAIL("Unknown Interrupt!!!");
405 break;
406 }
407 }
408
409 static __inline__ void
410 cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
411 {
412 switch (vector) {
413 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
414 {
415 // SIU interrupt vectors
416 cyg_uint32 sipend;
417
418 // When IRQx is configured as an edge interrupt it needs to be
419 // cleared. Write to INTx and IRQ/level bits are ignore so
420 // it's safe to do always.
421 HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
422 sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0)
423 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
424 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
425 break;
426 }
427 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
428 {
429 // TimeBase A interrupt
430 cyg_uint16 tbscr;
431
432 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
433 tbscr |= CYGARC_REG_IMM_TBSCR_REFA;
434 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
435 break;
436 }
437 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
438 {
439 // TimeBase B interrupt
440 cyg_uint16 tbscr;
441
442 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
443 tbscr |= CYGARC_REG_IMM_TBSCR_REFB;
444 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
445 break;
446 }
447 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
448 {
449 // Periodic Interrupt
450 cyg_uint16 piscr;
451
452 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
453 piscr |= CYGARC_REG_IMM_PISCR_PS;
454 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
455 break;
456 }
457 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
458 {
459 // Real Time Clock Second
460 cyg_uint16 rtcsc;
461
462 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
463 rtcsc |= CYGARC_REG_IMM_RTCSC_SEC;
464 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
465 break;
466 }
467 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
468 {
469 // Real Time Clock Alarm
470 cyg_uint16 rtcsc;
471
472 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
473 rtcsc |= CYGARC_REG_IMM_RTCSC_ALR;
474 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
475 break;
476 }
477 // PCMCIA_A_IRQ
478 // PCMCIA_A_CHLVL
479 // PCMCIA_B_IRQ
480 // PCMCIA_B_CHLVL
481 case CYGNUM_HAL_INTERRUPT_SIU_CPM:
482 // Communications Processor Module
483 // The CPM interrupts must be acknowledged individually.
484 break;
485 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
486 {
487 // CPM interrupts
488 cyg_uint32 cisr;
489
490 HAL_READ_UINT32 (CYGARC_REG_IMM_CISR, cisr);
491 cisr |= (((cyg_uint32) 0x80000000)
492 >> (vector - CYGNUM_HAL_INTERRUPT_CPM_FIRST));
493 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CISR, cisr);
494 break;
495 }
496 default:
497 CYG_FAIL("Unknown Interrupt!!!");
498 break;
499 }
500 }
501
502 static __inline__ void
503 cyg_hal_interrupt_configure ( cyg_uint32 vector,
504 cyg_bool level,
505 cyg_bool up )
506 {
507 switch (vector) {
508 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0:
509 case CYGNUM_HAL_INTERRUPT_SIU_IRQ1:
510 case CYGNUM_HAL_INTERRUPT_SIU_IRQ2:
511 case CYGNUM_HAL_INTERRUPT_SIU_IRQ3:
512 case CYGNUM_HAL_INTERRUPT_SIU_IRQ4:
513 case CYGNUM_HAL_INTERRUPT_SIU_IRQ5:
514 case CYGNUM_HAL_INTERRUPT_SIU_IRQ6:
515 case CYGNUM_HAL_INTERRUPT_SIU_IRQ7:
516 {
517 // External interrupts
518 cyg_uint32 siel, bit;
519
520 CYG_ASSERT( level || !up, "Only falling edge is supported");
521
522 bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_IRQ0)
523 >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
524
525 HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel);
526 siel &= ~bit;
527 if (!level) {
528 // Set edge detect bit.
529 siel |= bit;
530 }
531 HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel);
532 break;
533 }
534 case CYGNUM_HAL_INTERRUPT_SIU_LVL0:
535 case CYGNUM_HAL_INTERRUPT_SIU_LVL1:
536 case CYGNUM_HAL_INTERRUPT_SIU_LVL2:
537 case CYGNUM_HAL_INTERRUPT_SIU_LVL3:
538 case CYGNUM_HAL_INTERRUPT_SIU_LVL4:
539 case CYGNUM_HAL_INTERRUPT_SIU_LVL5:
540 case CYGNUM_HAL_INTERRUPT_SIU_LVL6:
541 case CYGNUM_HAL_INTERRUPT_SIU_LVL7:
542 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
543 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
544 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
545 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
546 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
547 // PCMCIA_A_IRQ
548 // PCMCIA_A_CHLVL
549 // PCMCIA_B_IRQ
550 // PCMCIA_B_CHLVL
551 case CYGNUM_HAL_INTERRUPT_SIU_CPM:
552 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
553 // These cannot be configured.
554 break;
555
556 default:
557 CYG_FAIL("Unknown Interrupt!!!");
558 break;
559 }
560 }
561
562 static __inline__ void
563 cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
564 {
565 // Note: highest priority has the lowest numerical value.
566 CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
567 CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
568
569 switch (vector) {
570 case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
571 // These cannot be configured.
572 break;
573 case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
574 case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
575 {
576 // TimeBase A+B interrupt
577 cyg_uint16 tbscr;
578
579 HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
580 tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK);
581 tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level;
582 HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
583 break;
584 }
585 case CYGNUM_HAL_INTERRUPT_SIU_PIT:
586 {
587 // Periodic Interrupt
588 cyg_uint16 piscr;
589
590 HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
591 piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK);
592 piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level;
593 HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
594 break;
595 }
596 case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
597 case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
598 {
599 // Real Time Clock Second & Real Time Clock Alarm
600 cyg_uint16 rtcsc;
601
602 HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
603 rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK);
604 rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level;
605 HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
606 break;
607 }
608 // PCMCIA_A_IRQ
609 // PCMCIA_A_CHLVL
610 // PCMCIA_B_IRQ
611 // PCMCIA_B_CHLVL
612 case CYGNUM_HAL_INTERRUPT_SIU_CPM:
613 {
614 // Communications Processor Module
615 cyg_uint32 cicr;
616
617 HAL_READ_UINT32 (CYGARC_REG_IMM_CICR, cicr);
618 cicr &= ~(CYGARC_REG_IMM_CICR_IRQMASK);
619 cicr |= level << CYGARC_REG_IMM_CICR_IRQ_SHIFT;
620 HAL_WRITE_UINT32 (CYGARC_REG_IMM_CICR, cicr);
621 break;
622 }
623 case CYGNUM_HAL_INTERRUPT_CPM_FIRST ... CYGNUM_HAL_INTERRUPT_CPM_LAST:
624 // CPM interrupt levels are for internal priority. All interrupts
625 // fed to the CPU use the CPM level set above.
626 // FIXME: Control of SCdP ordering.
627 break;
628 default:
629 CYG_FAIL("Unknown Interrupt!!!");
630 break;
631 }
632 }
633
634 // The decrementer interrupt cannnot be masked, configured or acknowledged.
635
636 #define HAL_INTERRUPT_MASK( _vector_ ) \
637 CYG_MACRO_START \
638 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
639 cyg_hal_interrupt_mask ( (_vector_) ); \
640 CYG_MACRO_END
641
642 #define HAL_INTERRUPT_UNMASK( _vector_ ) \
643 CYG_MACRO_START \
644 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
645 cyg_hal_interrupt_unmask ( (_vector_) ); \
646 CYG_MACRO_END
647
648 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
649 CYG_MACRO_START \
650 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
651 cyg_hal_interrupt_acknowledge ( (_vector_) ); \
652 CYG_MACRO_END
653
654 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
655 CYG_MACRO_START \
656 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
657 cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \
658 CYG_MACRO_END
659
660 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
661 CYG_MACRO_START \
662 if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
663 cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
664 CYG_MACRO_END
665
666 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
667
668 #endif
669
670 //--------------------------------------------------------------------------
671 // Interrupt arbiters
672
673 #ifdef CYGPKG_HAL_POWERPC_MPC860
674
675 externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector,
676 CYG_ADDRWORD data);
677 externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector,
678 CYG_ADDRWORD data);
679 externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector,
680 CYG_ADDRWORD data);
681 externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector,
682 CYG_ADDRWORD data);
683
684 #endif // ifdef CYGPKG_HAL_POWERPC_MPC860
685
686 //-----------------------------------------------------------------------------
687 #endif // ifndef CYGONCE_VAR_INTR_H
688 // End of var_intr.h